From 8fff6514ff0a0d803c1cf98adebebd45865a3f5c Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 7 Jul 2023 10:50:08 +0530 Subject: pinctrl: qcom-pmic-gpio: Add support for pm7550ba pm7550ba pmic support gpio controller so add compatible in the driver. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/1688707209-30151-4-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index b4cd66886f29..f1918fe5ed33 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1205,6 +1205,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm6350-gpio", .data = (void *) 9 }, { .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8}, { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 }, { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 }, -- cgit From 1e46c7430af766cc647c6a9cb469ac08ba603815 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 7 Jul 2023 10:50:09 +0530 Subject: pinctrl: qcom-pmic-gpio: Add support for pmx75 pmx75 pmic support gpio controller so add compatible in the driver. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/1688707209-30151-5-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index f1918fe5ed33..deded9c6fd7d 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1253,6 +1253,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */ { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 }, { .compatible = "qcom,pmx65-gpio", .data = (void *) 16 }, + { .compatible = "qcom,pmx75-gpio", .data = (void *) 16 }, { }, }; -- cgit From 28d8eb3687445f46b11216443e7ae3524681a2b1 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Tue, 4 Jul 2023 20:47:39 +0800 Subject: pinctrl: berlin: as370: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/20230704124742.9596-1-frank.li@vivo.com Signed-off-by: Linus Walleij --- drivers/pinctrl/berlin/pinctrl-as370.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/berlin/pinctrl-as370.c b/drivers/pinctrl/berlin/pinctrl-as370.c index 9dfdc275ee33..b631c14813a7 100644 --- a/drivers/pinctrl/berlin/pinctrl-as370.c +++ b/drivers/pinctrl/berlin/pinctrl-as370.c @@ -341,8 +341,7 @@ static int as370_pinctrl_probe(struct platform_device *pdev) if (!rmconfig) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(base)) return PTR_ERR(base); -- cgit From 2d357f25663ddfef47ffe26da21155302153d168 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Tue, 4 Jul 2023 20:47:40 +0800 Subject: pinctrl: mvebu: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/20230704124742.9596-2-frank.li@vivo.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mvebu/pinctrl-dove.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index 545486d98532..bd74daa9ed66 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c @@ -784,8 +784,7 @@ static int dove_pinctrl_probe(struct platform_device *pdev) } clk_prepare_enable(clk); - mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, mpp_res); + base = devm_platform_get_and_ioremap_resource(pdev, 0, &mpp_res); if (IS_ERR(base)) return PTR_ERR(base); -- cgit From 885b129f61350bbf77991f9f815cc26836745aa7 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Tue, 4 Jul 2023 20:47:41 +0800 Subject: pinctrl: pic32: Convert to devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/20230704124742.9596-3-frank.li@vivo.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-pic32.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index dad05294fa72..8ed6c5f8acc1 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -2162,7 +2162,6 @@ static const struct irq_chip pic32_gpio_irq_chip = { static int pic32_pinctrl_probe(struct platform_device *pdev) { struct pic32_pinctrl *pctl; - struct resource *res; int ret; pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); @@ -2171,8 +2170,7 @@ static int pic32_pinctrl_probe(struct platform_device *pdev) pctl->dev = &pdev->dev; dev_set_drvdata(&pdev->dev, pctl); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pctl->reg_base = devm_ioremap_resource(&pdev->dev, res); + pctl->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctl->reg_base)) return PTR_ERR(pctl->reg_base); -- cgit From 49104893fe97bdf92b3d5ed4401246d71f49a279 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Tue, 4 Jul 2023 20:47:42 +0800 Subject: pinctrl: ti: Convert to devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/20230704124742.9596-4-frank.li@vivo.com Signed-off-by: Linus Walleij --- drivers/pinctrl/ti/pinctrl-ti-iodelay.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c index 53abddaebce1..c1477f657839 100644 --- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -849,19 +849,12 @@ static int ti_iodelay_probe(struct platform_device *pdev) iod->reg_data = match->data; /* So far We can assume there is only 1 bank of registers */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(dev, "Missing MEM resource\n"); - ret = -ENODEV; - goto exit_out; - } - - iod->phys_base = res->start; - iod->reg_base = devm_ioremap_resource(dev, res); + iod->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(iod->reg_base)) { ret = PTR_ERR(iod->reg_base); goto exit_out; } + iod->phys_base = res->start; iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base, iod->reg_data->regmap_config); -- cgit From 99084881de88ffcd156b03aaeb7d4eb740005e3e Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 14 Jul 2023 10:19:01 +0200 Subject: pinctrl: cy8c95x0: Add reset support This patch adds support for an optional "reset" GPIO pin in the cy8c95x0 pinctrl driver. On probe, the reset pin is pulled low to bring chip out of reset. The reset pin has an internal pull-down and can be left floating if not required. The datasheet doesn't mention any timing related to the reset pin. Based on empirical tests, it was found that the chip requires a delay of 250 milliseconds before accepting I2C transfers after driving the reset pin low. Therefore, a delay of 250ms is added before proceeding with I2C transfers. Signed-off-by: Patrick Rudolph Signed-off-by: Naresh Solanki Link: https://lore.kernel.org/r/20230714081902.2621771-2-Naresh.Solanki@9elements.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 2ecc96691c55..58ca6fac7849 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -164,6 +164,7 @@ struct cy8c95x0_pinctrl { struct pinctrl_desc pinctrl_desc; char name[32]; unsigned int tpin; + struct gpio_desc *gpio_reset; }; static const struct pinctrl_pin_desc cy8c9560_pins[] = { @@ -1383,6 +1384,20 @@ static int cy8c95x0_probe(struct i2c_client *client) chip->regulator = reg; } + /* bring the chip out of reset if reset pin is provided */ + chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(chip->gpio_reset)) { + ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset), + "Failed to get GPIO 'reset'\n"); + goto err_exit; + } else if (chip->gpio_reset) { + usleep_range(1000, 2000); + gpiod_set_value_cansleep(chip->gpio_reset, 0); + usleep_range(250000, 300000); + + gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); + } + chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap); if (IS_ERR(chip->regmap)) { ret = PTR_ERR(chip->regmap); -- cgit From f14762422003863716064830e837d845c194946d Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 12 Jul 2023 18:19:59 +0100 Subject: pinctrl: sunxi: Add some defensiveness for regulators array The sunxi pinctrl has a fixed size array it uses to store regulators used in the driver. There is currently nothing that ensures that the number of elements in the array is large enough to map the regulators defined by the individual SoCs. While this is currently the case having an explicit check in there will make life easier for anyone debugging memory issues that manifest in the driver so let's add one. Signed-off-by: Mark Brown Reviewed-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230712-pinctrl-sunxi-boudns-v1-1-85f37de79b9f@kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 1dc1882cbdd7..1d1cd3d6d379 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -848,6 +848,9 @@ static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) char supply[16]; int ret; + if (WARN_ON_ONCE(bank_offset >= ARRAY_SIZE(pctl->regulators))) + return -EINVAL; + if (reg) { refcount_inc(&s_reg->refcount); return 0; -- cgit From d1cd5b51bc9152dc2b63c5f843590272d6694d50 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Fri, 14 Jul 2023 17:05:47 +0530 Subject: pinctrl: tegra: Add support to display pin function The current function for a given pin is not displayed via the debugfs. Add support to display the current function that is set for each pin. Signed-off-by: Prathamesh Shete Acked-by: Thierry Reding Reviewed-by: Jon Hunter Link: https://lore.kernel.org/r/20230714113547.15384-1-pshete@nvidia.com Signed-off-by: Linus Walleij --- drivers/pinctrl/tegra/pinctrl-tegra.c | 19 +++++++++++++++++-- drivers/pinctrl/tegra/pinctrl-tegra.h | 2 ++ 2 files changed, 19 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 4547cf66d03b..cb1d67239cd0 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -96,6 +96,7 @@ static const struct cfg_param { {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, + {"nvidia,function", TEGRA_PINCONF_PARAM_FUNCTION}, }; static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, @@ -470,6 +471,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, *bit = g->drvtype_bit; *width = 2; break; + case TEGRA_PINCONF_PARAM_FUNCTION: + *bank = g->mux_bank; + *reg = g->mux_reg; + *bit = g->mux_bit; + *width = 2; + break; default: dev_err(pmx->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; @@ -633,8 +640,16 @@ static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, val >>= bit; val &= (1 << width) - 1; - seq_printf(s, "\n\t%s=%u", - strip_prefix(cfg_params[i].property), val); + if (cfg_params[i].param == TEGRA_PINCONF_PARAM_FUNCTION) { + u8 idx = pmx->soc->groups[group].funcs[val]; + + seq_printf(s, "\n\t%s=%s", + strip_prefix(cfg_params[i].property), + pmx->functions[idx].name); + } else { + seq_printf(s, "\n\t%s=%u", + strip_prefix(cfg_params[i].property), val); + } } } diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index b3289bdf727d..e728efeaa4de 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -54,6 +54,8 @@ enum tegra_pinconf_param { TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, /* argument: Integer, range is HW-dependant */ TEGRA_PINCONF_PARAM_DRIVE_TYPE, + /* argument: pinmux settings */ + TEGRA_PINCONF_PARAM_FUNCTION, }; enum tegra_pinconf_pull { -- cgit From abf02e132cb6959e2da3c8d5ee839719a3191465 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 14 Jul 2023 14:40:46 +0200 Subject: pinctrl: qcom: lpass-lpi: Make the clocks optional, always Some platforms provide a single clock source to all LPASS peripherals, others provide two, and there are probably others that provide it through magic invisible-to-Linux wires. Rely on bindings to mandate the adequate number of clocks necessary. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230714-topic-lpass_lpi_cleanup-v1-1-dc18b5bd14f7@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index fdb6585a9234..6cf6c734db17 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -438,11 +438,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), "Slew resource not provided\n"); - if (of_property_read_bool(dev->of_node, "qcom,adsp-bypass-mode")) - ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); - else - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); - + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); if (ret) return ret; -- cgit From 060f03e95454a0f4a1deff3e5f912e461ae0f0c5 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:48:54 -0600 Subject: pinctrl: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Reviewed-by: Damien Le Moal Acked-by: Emil Renner Berthing Acked-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 4 ++-- drivers/pinctrl/bcm/pinctrl-nsp-gpio.c | 5 ++--- drivers/pinctrl/freescale/pinctrl-imx.c | 2 +- drivers/pinctrl/freescale/pinctrl-imx1-core.c | 3 ++- drivers/pinctrl/freescale/pinctrl-imx23.c | 3 ++- drivers/pinctrl/freescale/pinctrl-imx25.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx27.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx28.c | 3 ++- drivers/pinctrl/freescale/pinctrl-imx35.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx50.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx51.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx53.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx6dl.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx6q.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx6sl.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx6sll.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx6sx.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx6ul.c | 2 +- drivers/pinctrl/freescale/pinctrl-imx7d.c | 2 +- drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 5 ++--- drivers/pinctrl/freescale/pinctrl-imx8dxl.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx8mm.c | 2 +- drivers/pinctrl/freescale/pinctrl-imx8mq.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 3 ++- drivers/pinctrl/freescale/pinctrl-imx8ulp.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imx93.c | 4 ++-- drivers/pinctrl/freescale/pinctrl-imxrt1050.c | 2 +- drivers/pinctrl/freescale/pinctrl-imxrt1170.c | 2 +- drivers/pinctrl/freescale/pinctrl-vf610.c | 4 ++-- drivers/pinctrl/mediatek/pinctrl-mt2701.c | 1 - drivers/pinctrl/mediatek/pinctrl-mt2712.c | 1 - drivers/pinctrl/mediatek/pinctrl-mt6397.c | 1 - drivers/pinctrl/mediatek/pinctrl-mt8127.c | 1 - drivers/pinctrl/mediatek/pinctrl-mt8135.c | 1 - drivers/pinctrl/mediatek/pinctrl-mt8167.c | 1 - drivers/pinctrl/mediatek/pinctrl-mt8173.c | 1 - drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 - drivers/pinctrl/mediatek/pinctrl-mt8516.c | 1 - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 -- drivers/pinctrl/meson/pinctrl-meson.c | 1 - drivers/pinctrl/mvebu/pinctrl-ac5.c | 1 - drivers/pinctrl/mvebu/pinctrl-armada-370.c | 1 - drivers/pinctrl/mvebu/pinctrl-armada-375.c | 1 - drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 2 -- drivers/pinctrl/mvebu/pinctrl-mvebu.c | 2 -- drivers/pinctrl/nxp/pinctrl-s32cc.c | 2 +- drivers/pinctrl/nxp/pinctrl-s32g2.c | 2 +- drivers/pinctrl/pinctrl-axp209.c | 1 - drivers/pinctrl/pinctrl-k210.c | 2 +- drivers/pinctrl/pinctrl-lpc18xx.c | 4 ++-- drivers/pinctrl/pinctrl-ocelot.c | 4 +--- drivers/pinctrl/pinctrl-oxnas.c | 1 - drivers/pinctrl/pinctrl-palmas.c | 1 - drivers/pinctrl/pinctrl-pic32.c | 1 - drivers/pinctrl/pinctrl-rockchip.c | 5 ++--- drivers/pinctrl/pinctrl-single.c | 3 +-- drivers/pinctrl/pinctrl-sx150x.c | 1 - drivers/pinctrl/pxa/pinctrl-pxa25x.c | 1 - drivers/pinctrl/pxa/pinctrl-pxa27x.c | 1 - drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 3 ++- drivers/pinctrl/qcom/pinctrl-sdx75.c | 1 - drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c | 2 +- drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 2 +- drivers/pinctrl/renesas/core.c | 1 - drivers/pinctrl/renesas/pinctrl-rza1.c | 3 +-- drivers/pinctrl/renesas/pinctrl-rza2.c | 3 ++- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 3 ++- drivers/pinctrl/renesas/pinctrl-rzv2m.c | 3 ++- drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +- drivers/pinctrl/spear/pinctrl-spear1310.c | 2 +- drivers/pinctrl/spear/pinctrl-spear1340.c | 2 +- drivers/pinctrl/spear/pinctrl-spear300.c | 2 +- drivers/pinctrl/spear/pinctrl-spear310.c | 2 +- drivers/pinctrl/spear/pinctrl-spear320.c | 2 +- drivers/pinctrl/sprd/pinctrl-sprd.c | 1 - drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c | 5 +---- drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c | 2 -- drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c | 1 - drivers/pinctrl/stm32/pinctrl-stm32.c | 3 +-- drivers/pinctrl/sunplus/sppctl.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun5i.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 1 - drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c | 1 - drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 --- drivers/pinctrl/tegra/pinctrl-tegra194.c | 1 - 107 files changed, 80 insertions(+), 145 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index cc3eb7409ab3..dcec671661e2 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -21,8 +21,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index 5045a7e57f1d..e8a5ecd7fb3b 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -15,12 +15,11 @@ #include #include #include -#include -#include -#include +#include #include #include #include +#include #include #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 93ffb5fc04e7..9bc16943014f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index 3726c0ac2560..90c696046b38 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -15,7 +15,8 @@ #include #include #include -#include +#include +#include #include #include diff --git a/drivers/pinctrl/freescale/pinctrl-imx23.c b/drivers/pinctrl/freescale/pinctrl-imx23.c index 144020764a4b..0404efbf2a86 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx23.c +++ b/drivers/pinctrl/freescale/pinctrl-imx23.c @@ -6,7 +6,8 @@ // Copyright 2012 Freescale Semiconductor, Inc. #include -#include +#include +#include #include #include "pinctrl-mxs.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c index 51748da1668f..d2b0b6aad306 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx25.c +++ b/drivers/pinctrl/freescale/pinctrl-imx25.c @@ -14,8 +14,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c index 67e7105be4f3..1738df461235 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx27.c +++ b/drivers/pinctrl/freescale/pinctrl-imx27.c @@ -9,8 +9,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx1.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx28.c b/drivers/pinctrl/freescale/pinctrl-imx28.c index 13730dd193f1..eb847151713a 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx28.c +++ b/drivers/pinctrl/freescale/pinctrl-imx28.c @@ -6,7 +6,8 @@ // Copyright 2012 Freescale Semiconductor, Inc. #include -#include +#include +#include #include #include "pinctrl-mxs.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c index c8671ad5214c..1546517d8110 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx35.c +++ b/drivers/pinctrl/freescale/pinctrl-imx35.c @@ -12,8 +12,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c index a245b4011c00..9b044aee4f7c 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx50.c +++ b/drivers/pinctrl/freescale/pinctrl-imx50.c @@ -9,8 +9,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c index 307cf5fe4d15..e580c022bebe 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx51.c +++ b/drivers/pinctrl/freescale/pinctrl-imx51.c @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c index 02bf3bda69ac..1034192ab410 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx53.c +++ b/drivers/pinctrl/freescale/pinctrl-imx53.c @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c index 2b6d5141a477..09542fdcd405 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6dl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c index a7507def26a9..ae5cec74a3e8 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6q.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c index 236f3bf120c2..3111f50263f6 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sll.c b/drivers/pinctrl/freescale/pinctrl-imx6sll.c index dfefcecbe072..72a7214811ab 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sll.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sll.c @@ -7,8 +7,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c index b7b97c274dcc..aa76bc6d7402 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c index 3b8747482e36..9cb02444f8aa 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6ul.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c index 4126387344cb..8acf2b73aefa 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7d.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c index 1915378d92b2..ba0ef1ea5722 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c @@ -8,9 +8,8 @@ #include #include #include -#include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c index f947b1d0d1aa..7dec709ebd9a 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c @@ -8,10 +8,10 @@ #include #include #include +#include #include -#include -#include #include +#include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mm.c b/drivers/pinctrl/freescale/pinctrl-imx8mm.c index 39dc73281ce6..47d14902a01a 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8mm.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8mm.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mq.c b/drivers/pinctrl/freescale/pinctrl-imx8mq.c index 3ed3c98bcedb..529eebe46298 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8mq.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8mq.c @@ -8,10 +8,10 @@ #include #include #include +#include #include -#include -#include #include +#include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c index 0a0acc0038d0..37ef3229231b 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c @@ -10,10 +10,11 @@ #include #include #include +#include #include #include -#include #include +#include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c index f8572597a54e..2e86ca9fc7ac 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c @@ -6,10 +6,10 @@ #include #include #include +#include #include -#include -#include #include +#include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx93.c b/drivers/pinctrl/freescale/pinctrl-imx93.c index 91b3ee1e6fa9..5977dda3b759 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx93.c +++ b/drivers/pinctrl/freescale/pinctrl-imx93.c @@ -6,10 +6,10 @@ #include #include #include +#include #include -#include -#include #include +#include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c index def683839ebe..f6435227d4fb 100644 --- a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c +++ b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1170.c b/drivers/pinctrl/freescale/pinctrl-imxrt1170.c index 5da1545fde91..d8857f329e25 100644 --- a/drivers/pinctrl/freescale/pinctrl-imxrt1170.c +++ b/drivers/pinctrl/freescale/pinctrl-imxrt1170.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c index 700e5a136814..76adcc5abdec 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -7,8 +7,8 @@ #include #include #include -#include -#include +#include +#include #include #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index b185538452a0..5fb377c1668b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index 730a496848dc..8a6daa0db54b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c index bc5c3dfcdc76..03d0f65d7bcc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index e8772dcfe69e..f5030a9ea40b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index cdb0252071fb..77c6ac464e86 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index 866da2c4a890..ba7f30c3296f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index 37d8cec1c3ce..455eec018f93 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 75a505035e96..1db04bbdb423 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index e929339dd2cb..950275c47122 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 665dec419e7c..74b15952b742 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -8,8 +8,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 530f3f934e19..524424ee6c4e 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -43,7 +43,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mvebu/pinctrl-ac5.c b/drivers/pinctrl/mvebu/pinctrl-ac5.c index 292633e61129..09ddfc434c6b 100644 --- a/drivers/pinctrl/mvebu/pinctrl-ac5.c +++ b/drivers/pinctrl/mvebu/pinctrl-ac5.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include "pinctrl-mvebu.h" diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index d3195557a901..a50c2183e49a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include "pinctrl-mvebu.h" diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index e6aaa3708e58..64e2096a05e4 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include "pinctrl-mvebu.h" diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 67c6751a6f06..1e1f3fdaba21 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -13,8 +13,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 8e6aac4164df..84a119718f86 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -11,8 +11,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index 3ae043b27463..7daff9f186cd 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinctrl-s32g2.c index 224a12ce70ed..440ff1879424 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include "pinctrl-s32.h" diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index b3ba25435c34..9f5b3ab8e184 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index 97920fb517bc..b6d1ed9ec9a3 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index 13c041dd2ce0..0f5a7bed2f81 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -12,8 +12,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 1dcbd0937ef5..f8ae2e974221 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -11,9 +11,7 @@ #include #include #include -#include -#include -#include +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c index fb10a8473ebe..2b2f36994323 100644 --- a/drivers/pinctrl/pinctrl-oxnas.c +++ b/drivers/pinctrl/pinctrl-oxnas.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c index fecc25d35d02..9e272f9deb4f 100644 --- a/drivers/pinctrl/pinctrl-palmas.c +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index 8ed6c5f8acc1..bf827ab081a1 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 0276b52f3716..45e416f68e74 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -21,9 +21,8 @@ #include #include #include -#include -#include -#include +#include +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 0dabbcf68b9f..f056923ecc98 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -12,14 +12,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include -#include #include #include diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 35faea8dfb0b..fef1ee7b7945 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/pxa/pinctrl-pxa25x.c b/drivers/pinctrl/pxa/pinctrl-pxa25x.c index 95640698422f..2a4842557bb2 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa25x.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa25x.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include "pinctrl-pxa2xx.h" diff --git a/drivers/pinctrl/pxa/pinctrl-pxa27x.c b/drivers/pinctrl/pxa/pinctrl-pxa27x.c index ff9302e4803a..b3acbaf8c85f 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa27x.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa27x.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include "pinctrl-pxa2xx.h" diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 6cf6c734db17..e5a418026ba3 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -8,7 +8,8 @@ #include #include #include -#include +#include +#include #include #include diff --git a/drivers/pinctrl/qcom/pinctrl-sdx75.c b/drivers/pinctrl/qcom/pinctrl-sdx75.c index 2ade7866dbc5..3cfe8c7f04df 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx75.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx75.c @@ -5,7 +5,6 @@ #include #include -#include #include #include "pinctrl-msm.h" diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index dec1ffc49ffd..e0d43d076c01 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index b5aed540f07e..985d1a0ee8f8 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 0c8d081da6a8..6e250a9225a4 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/renesas/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c index 68c7af5d86bc..f43f1196fea8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza1.c +++ b/drivers/pinctrl/renesas/pinctrl-rza1.c @@ -19,11 +19,10 @@ #include #include #include -#include -#include #include #include #include +#include #include #include diff --git a/drivers/pinctrl/renesas/pinctrl-rza2.c b/drivers/pinctrl/renesas/pinctrl-rza2.c index 40b1326a1077..0b454a31c4bd 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza2.c +++ b/drivers/pinctrl/renesas/pinctrl-rza2.c @@ -14,8 +14,9 @@ #include #include #include -#include +#include #include +#include #include "../core.h" #include "../pinmux.h" diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 9511d920565e..87ca761a1aec 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -11,8 +11,9 @@ #include #include #include -#include +#include #include +#include #include #include diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c index e5472293bc7f..dd2342b757be 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -14,7 +14,8 @@ #include #include #include -#include +#include +#include #include #include diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 833e170e3d99..e54847040b4a 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c index 0180eb544f02..fb624a051e26 100644 --- a/drivers/pinctrl/spear/pinctrl-spear1310.c +++ b/drivers/pinctrl/spear/pinctrl-spear1310.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include #include "pinctrl-spear.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c index 0ca961219b3b..48f068cf5e24 100644 --- a/drivers/pinctrl/spear/pinctrl-spear1340.c +++ b/drivers/pinctrl/spear/pinctrl-spear1340.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include #include "pinctrl-spear.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c index d53a04597cbe..7530252ef7bc 100644 --- a/drivers/pinctrl/spear/pinctrl-spear300.c +++ b/drivers/pinctrl/spear/pinctrl-spear300.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include #include "pinctrl-spear3xx.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c index 9d9facc4a6e4..c476e5478646 100644 --- a/drivers/pinctrl/spear/pinctrl-spear310.c +++ b/drivers/pinctrl/spear/pinctrl-spear310.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include #include "pinctrl-spear3xx.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c index e629e3035543..401477cfbf57 100644 --- a/drivers/pinctrl/spear/pinctrl-spear320.c +++ b/drivers/pinctrl/spear/pinctrl-spear320.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include #include "pinctrl-spear3xx.h" diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c index ca9659f4e4b1..ccdcc91c7fa5 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c index 8cf28aaed254..4bfe3aa57f8a 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c @@ -10,11 +10,8 @@ #include #include #include +#include #include -#include -#include -#include -#include #include #include #include diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c index bc279a39613f..20c85db1cd3a 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c @@ -13,8 +13,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c index 5fe729b4a03d..b9081805c8f6 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 4b97bd00191b..cbdb28358965 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -13,9 +13,8 @@ #include #include #include -#include -#include #include +#include #include #include #include diff --git a/drivers/pinctrl/sunplus/sppctl.c b/drivers/pinctrl/sunplus/sppctl.c index 150996949ede..bb5ef391dbe4 100644 --- a/drivers/pinctrl/sunplus/sppctl.c +++ b/drivers/pinctrl/sunplus/sppctl.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c index 9cc94be1046d..8e2aab542fcf 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c index 0c7c361ebac5..fa47fe36ee5b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c index b82ad135bf2a..6d121bec4445 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c @@ -8,7 +8,6 @@ #include #include -#include #include #include diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c index f682e0e4244d..df90c75fb3c5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c @@ -8,7 +8,6 @@ #include #include -#include #include #include diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c index ef261eccda56..8693cd4877e1 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c @@ -21,7 +21,6 @@ */ #include -#include #include #include diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c index 7b83d3755a0e..1c23ce9df52f 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c index 96a350e70668..669793c6578e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c index 3aba0aec3d78..394476a35cad 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c index 3cc1121589c9..517118341316 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c index c39ea46046c2..d1f7cfa824c5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c index d6ca720ee8d8..73f012823a98 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i.c b/drivers/pinctrl/sunxi/pinctrl-sun5i.c index 27ec99e81c4c..06ecb121c827 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c index 2486cdf345e1..c983243cd6fb 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c index 82ffaf466892..82ac064931df 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c index 4fae12c905b7..de00d3ef5e82 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c index 402fd7d21e7b..f6b01a8a8977 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c index f043afa1aac5..f48f3e8cbe87 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c index 0cb6c1a970c9..c6a3ab3461ac 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c @@ -24,7 +24,6 @@ */ #include -#include #include #include diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c index b5c1a8f363f3..fd1c65c0180c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c index b795a199e240..45e1531697fb 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c index d1719a738c20..1c0823d50250 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index ca85438e379a..49c9a0b6a0eb 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c index f11cb5bba0f7..919b6a20af83 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c index 0633a03d5e13..61137c7f09b6 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c index b8fc88a23cf4..bfc39cc3b3e3 100644 --- a/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c +++ b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 1d1cd3d6d379..73bcf806af0e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -18,10 +18,7 @@ #include #include #include -#include #include -#include -#include #include #include #include diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c index 69f58df62897..6d77954d286b 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include -- cgit From ea90ca106c3fbb35508073bd2439ec04d2ff3fc5 Mon Sep 17 00:00:00 2001 From: Huqiang Qin Date: Fri, 14 Jul 2023 20:24:41 +0800 Subject: pinctrl: Add driver support for Amlogic C3 SoCs Add a new pinctrl driver for Amlogic C3 SoCs which share the same register layout as the previous Amlogic S4. Signed-off-by: Huqiang Qin Link: https://lore.kernel.org/r/20230714122441.3098337-3-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/Kconfig | 6 + drivers/pinctrl/meson/Makefile | 1 + drivers/pinctrl/meson/pinctrl-amlogic-c3.c | 1108 ++++++++++++++++++++++++++++ 3 files changed, 1115 insertions(+) create mode 100644 drivers/pinctrl/meson/pinctrl-amlogic-c3.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index 64fb9e074ac6..71fa7431df67 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -67,4 +67,10 @@ config PINCTRL_MESON_S4 select PINCTRL_MESON_AXG_PMX default y +config PINCTRL_AMLOGIC_C3 + tristate "Amlogic C3 SoC pinctrl driver" + depends on ARM64 + select PINCTRL_MESON_AXG_PMX + default y + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 694f0596bfbc..7ecddf7f683e 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o +obj-$(CONFIG_PINCTRL_AMLOGIC_C3) += pinctrl-amlogic-c3.o diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-c3.c b/drivers/pinctrl/meson/pinctrl-amlogic-c3.c new file mode 100644 index 000000000000..04f1e87bae99 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-amlogic-c3.c @@ -0,0 +1,1108 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Pin controller and GPIO driver for Amlogic C3 SoC. + * + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Huqiang Qin + */ + +#include +#include "pinctrl-meson.h" +#include "pinctrl-meson-axg-pmx.h" + +static const struct pinctrl_pin_desc c3_periphs_pins[] = { + MESON_PIN(GPIOE_0), + MESON_PIN(GPIOE_1), + MESON_PIN(GPIOE_2), + MESON_PIN(GPIOE_3), + MESON_PIN(GPIOE_4), + MESON_PIN(GPIOB_0), + MESON_PIN(GPIOB_1), + MESON_PIN(GPIOB_2), + MESON_PIN(GPIOB_3), + MESON_PIN(GPIOB_4), + MESON_PIN(GPIOB_5), + MESON_PIN(GPIOB_6), + MESON_PIN(GPIOB_7), + MESON_PIN(GPIOB_8), + MESON_PIN(GPIOB_9), + MESON_PIN(GPIOB_10), + MESON_PIN(GPIOB_11), + MESON_PIN(GPIOB_12), + MESON_PIN(GPIOB_13), + MESON_PIN(GPIOB_14), + MESON_PIN(GPIOC_0), + MESON_PIN(GPIOC_1), + MESON_PIN(GPIOC_2), + MESON_PIN(GPIOC_3), + MESON_PIN(GPIOC_4), + MESON_PIN(GPIOC_5), + MESON_PIN(GPIOC_6), + MESON_PIN(GPIOX_0), + MESON_PIN(GPIOX_1), + MESON_PIN(GPIOX_2), + MESON_PIN(GPIOX_3), + MESON_PIN(GPIOX_4), + MESON_PIN(GPIOX_5), + MESON_PIN(GPIOX_6), + MESON_PIN(GPIOX_7), + MESON_PIN(GPIOX_8), + MESON_PIN(GPIOX_9), + MESON_PIN(GPIOX_10), + MESON_PIN(GPIOX_11), + MESON_PIN(GPIOX_12), + MESON_PIN(GPIOX_13), + MESON_PIN(GPIOD_0), + MESON_PIN(GPIOD_1), + MESON_PIN(GPIOD_2), + MESON_PIN(GPIOD_3), + MESON_PIN(GPIOD_4), + MESON_PIN(GPIOD_5), + MESON_PIN(GPIOD_6), + MESON_PIN(GPIOA_0), + MESON_PIN(GPIOA_1), + MESON_PIN(GPIOA_2), + MESON_PIN(GPIOA_3), + MESON_PIN(GPIOA_4), + MESON_PIN(GPIOA_5), + MESON_PIN(GPIO_TEST_N), +}; + +/* Bank E func1 */ +static const unsigned int pwm_a_pins[] = { GPIOE_0 }; +static const unsigned int pwm_b_pins[] = { GPIOE_1 }; +static const unsigned int i2c2_sda_pins[] = { GPIOE_2 }; +static const unsigned int i2c2_scl_pins[] = { GPIOE_3 }; +static const unsigned int gen_clk_e_pins[] = { GPIOE_4 }; + +/* Bank E func2 */ +static const unsigned int i2c0_sda_e_pins[] = { GPIOE_0 }; +static const unsigned int i2c0_scl_e_pins[] = { GPIOE_1 }; +static const unsigned int clk_32k_in_pins[] = { GPIOE_4 }; + +/* Bank E func3 */ +static const unsigned int i2c_slave_scl_pins[] = { GPIOE_0 }; +static const unsigned int i2c_slave_sda_pins[] = { GPIOE_1 }; +static const unsigned int clk12_24_e_pins[] = { GPIOE_4 }; + +/* Bank B func1 */ +static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; +static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; +static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; +static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; +static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; +static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; +static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; +static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; +static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; +static const unsigned int emmc_rst_pins[] = { GPIOB_9 }; +static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; +static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 }; + +/* Bank B func2 */ +static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 }; +static const unsigned int nand_ale_pins[] = { GPIOB_9 }; +static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 }; +static const unsigned int nand_cle_pins[] = { GPIOB_11 }; +static const unsigned int nand_ce0_pins[] = { GPIOB_12 }; + +/* Bank B func3 */ +static const unsigned int pwm_g_b_pins[] = { GPIOB_0 }; +static const unsigned int pwm_h_b_pins[] = { GPIOB_1 }; +static const unsigned int pwm_i_b_pins[] = { GPIOB_2 }; +static const unsigned int spif_hold_pins[] = { GPIOB_3 }; +static const unsigned int spif_mo_pins[] = { GPIOB_4 }; +static const unsigned int spif_mi_pins[] = { GPIOB_5 }; +static const unsigned int spif_clk_pins[] = { GPIOB_6 }; +static const unsigned int spif_wp_pins[] = { GPIOB_7 }; +static const unsigned int pwm_j_b_pins[] = { GPIOB_8 }; +static const unsigned int pwm_k_b_pins[] = { GPIOB_9 }; +static const unsigned int pwm_l_b_pins[] = { GPIOB_10 }; +static const unsigned int pwm_m_b_pins[] = { GPIOB_11 }; +static const unsigned int pwm_n_b_pins[] = { GPIOB_12 }; +static const unsigned int spif_cs_pins[] = { GPIOB_13 }; +static const unsigned int spif_clk_loop_pins[] = { GPIOB_14 }; + +/* Bank B func4 */ +static const unsigned int lcd_d0_pins[] = { GPIOB_0 }; +static const unsigned int lcd_d1_pins[] = { GPIOB_1 }; +static const unsigned int lcd_d2_pins[] = { GPIOB_2 }; +static const unsigned int lcd_d3_pins[] = { GPIOB_8 }; +static const unsigned int lcd_d4_pins[] = { GPIOB_9 }; +static const unsigned int lcd_d5_pins[] = { GPIOB_10 }; +static const unsigned int lcd_d6_pins[] = { GPIOB_11 }; +static const unsigned int lcd_d7_pins[] = { GPIOB_12 }; + +/* Bank B func5 */ +static const unsigned int spi_a_mosi_b_pins[] = { GPIOB_0 }; +static const unsigned int spi_a_miso_b_pins[] = { GPIOB_1 }; +static const unsigned int spi_a_clk_b_pins[] = { GPIOB_2 }; +static const unsigned int spi_a_ss0_b_pins[] = { GPIOB_8 }; +static const unsigned int spi_a_ss1_b_pins[] = { GPIOB_9 }; +static const unsigned int spi_a_ss2_b_pins[] = { GPIOB_10 }; +static const unsigned int i2c1_sda_b_pins[] = { GPIOB_11 }; +static const unsigned int i2c1_scl_b_pins[] = { GPIOB_12 }; + +/* Bank B func6 */ +static const unsigned int uart_a_tx_b_pins[] = { GPIOB_0 }; +static const unsigned int uart_a_rx_b_pins[] = { GPIOB_1 }; +static const unsigned int uart_a_cts_b_pins[] = { GPIOB_2 }; +static const unsigned int uart_a_rts_b_pins[] = { GPIOB_8 }; +static const unsigned int uart_d_tx_b_pins[] = { GPIOB_9 }; +static const unsigned int uart_d_rx_b_pins[] = { GPIOB_10 }; +static const unsigned int pdm_dclk_b_pins[] = { GPIOB_11 }; +static const unsigned int pdm_din0_b_pins[] = { GPIOB_12 }; + +/* Bank C func1 */ +static const unsigned int sdcard_d0_pins[] = { GPIOC_0 }; +static const unsigned int sdcard_d1_pins[] = { GPIOC_1 }; +static const unsigned int sdcard_d2_pins[] = { GPIOC_2 }; +static const unsigned int sdcard_d3_pins[] = { GPIOC_3 }; +static const unsigned int sdcard_clk_pins[] = { GPIOC_4 }; +static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 }; +static const unsigned int sdcard_cd_pins[] = { GPIOC_6 }; + +/* Bank C func2 */ +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; +static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 }; +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; +static const unsigned int gen_clk_c_pins[] = { GPIOC_6 }; + +/* Bank C func3 */ +static const unsigned int tdm_d3_pins[] = { GPIOC_0 }; +static const unsigned int tdm_d2_pins[] = { GPIOC_1 }; +static const unsigned int mclk_1_pins[] = { GPIOC_2 }; +static const unsigned int tdm_sclk1_pins[] = { GPIOC_3 }; +static const unsigned int tdm_fs1_pins[] = { GPIOC_4 }; +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_5 }; +static const unsigned int pdm_din0_c_pins[] = { GPIOC_6 }; + +/* Bank C func4 */ +static const unsigned int spi_a_mosi_c_pins[] = { GPIOC_0 }; +static const unsigned int spi_a_miso_c_pins[] = { GPIOC_1 }; +static const unsigned int spi_a_clk_c_pins[] = { GPIOC_2 }; +static const unsigned int spi_a_ss0_c_pins[] = { GPIOC_3 }; +static const unsigned int spi_a_ss1_c_pins[] = { GPIOC_4 }; + +/* Bank C func5 */ +static const unsigned int pwm_g_c_pins[] = { GPIOC_0 }; +static const unsigned int pwm_h_c_pins[] = { GPIOC_1 }; +static const unsigned int pwm_i_c_pins[] = { GPIOC_2 }; +static const unsigned int pwm_j_c_pins[] = { GPIOC_3 }; +static const unsigned int pwm_k_c_pins[] = { GPIOC_4 }; +static const unsigned int pwm_l_c_pins[] = { GPIOC_5 }; +static const unsigned int pwm_m_c_pins[] = { GPIOC_6 }; + +/* Bank C func6 */ +static const unsigned int uart_a_rx_c_pins[] = { GPIOC_0 }; +static const unsigned int uart_a_tx_c_pins[] = { GPIOC_1 }; +static const unsigned int uart_c_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_c_tx_c_pins[] = { GPIOC_3 }; +static const unsigned int i2c3_sda_c_pins[] = { GPIOC_4 }; +static const unsigned int i2c3_scl_c_pins[] = { GPIOC_5 }; +static const unsigned int clk12_24_c_pins[] = { GPIOC_6 }; + +/* Bank X func1 */ +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; +static const unsigned int clk12_24_x_pins[] = { GPIOX_6 }; +static const unsigned int uart_e_tx_x_pins[] = { GPIOX_7 }; +static const unsigned int uart_e_rx_x_pins[] = { GPIOX_8 }; +static const unsigned int uart_e_cts_pins[] = { GPIOX_9 }; +static const unsigned int uart_e_rts_pins[] = { GPIOX_10 }; +static const unsigned int pwm_e_pins[] = { GPIOX_11 }; +static const unsigned int pwm_j_x12_pins[] = { GPIOX_12 }; +static const unsigned int pwm_k_x13_pins[] = { GPIOX_13 }; + +/* Bank X func2 */ +static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_0 }; +static const unsigned int spi_a_miso_x_pins[] = { GPIOX_1 }; +static const unsigned int spi_a_clk_x_pins[] = { GPIOX_2 }; +static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_3 }; +static const unsigned int spi_a_ss1_x_pins[] = { GPIOX_4 }; +static const unsigned int spi_a_ss2_x_pins[] = { GPIOX_5 }; +static const unsigned int spi_b_ss2_x6_pins[] = { GPIOX_6 }; +static const unsigned int spi_b_miso_x_pins[] = { GPIOX_7 }; +static const unsigned int spi_b_clk_x_pins[] = { GPIOX_8 }; +static const unsigned int spi_b_mosi_x_pins[] = { GPIOX_9 }; +static const unsigned int spi_b_ss0_x_pins[] = { GPIOX_10 }; +static const unsigned int spi_b_ss1_x_pins[] = { GPIOX_11 }; +static const unsigned int spi_b_ss2_x12_pins[] = { GPIOX_12 }; +static const unsigned int gen_clk_x_pins[] = { GPIOX_13 }; + +/* Bank X func3 */ +static const unsigned int tdm_d1_x_pins[] = { GPIOX_0 }; +static const unsigned int tdm_d0_x_pins[] = { GPIOX_1 }; +static const unsigned int mclk_0_x_pins[] = { GPIOX_2 }; +static const unsigned int tdm_sclk0_x_pins[] = { GPIOX_3 }; +static const unsigned int tdm_fs0_x_pins[] = { GPIOX_4 }; +static const unsigned int pdm_dclk_x5_pins[] = { GPIOX_5 }; +static const unsigned int pdm_din0_x6_pins[] = { GPIOX_6 }; +static const unsigned int pdm_din0_x9_pins[] = { GPIOX_9 }; +static const unsigned int pdm_dclk_x10_pins[] = { GPIOX_10 }; +static const unsigned int clk12_24_x13_pins[] = { GPIOX_13 }; + +/* Bank X func4 */ +static const unsigned int lcd_d8_pins[] = { GPIOX_0 }; +static const unsigned int lcd_d9_pins[] = { GPIOX_1 }; +static const unsigned int lcd_d10_pins[] = { GPIOX_2 }; +static const unsigned int lcd_d11_pins[] = { GPIOX_3 }; +static const unsigned int lcd_d12_pins[] = { GPIOX_4 }; +static const unsigned int lcd_d13_pins[] = { GPIOX_5 }; +static const unsigned int lcd_d14_pins[] = { GPIOX_6 }; +static const unsigned int lcd_d15_pins[] = { GPIOX_7 }; +static const unsigned int lcd_vs_pins[] = { GPIOX_8 }; +static const unsigned int lcd_hs_pins[] = { GPIOX_9 }; +static const unsigned int lcd_den_pins[] = { GPIOX_10 }; +static const unsigned int lcd_d16_pins[] = { GPIOX_11 }; +static const unsigned int lcd_clk_x_pins[] = { GPIOX_12 }; +static const unsigned int lcd_d17_pins[] = { GPIOX_13 }; + +/* Bank X func5 */ +static const unsigned int pwm_g_x0_pins[] = { GPIOX_0 }; +static const unsigned int pwm_h_x1_pins[] = { GPIOX_1 }; +static const unsigned int pwm_i_x2_pins[] = { GPIOX_2 }; +static const unsigned int pwm_j_x3_pins[] = { GPIOX_3 }; +static const unsigned int pwm_k_x4_pins[] = { GPIOX_4 }; +static const unsigned int pwm_l_x_pins[] = { GPIOX_5 }; +static const unsigned int pwm_m_x_pins[] = { GPIOX_6 }; +static const unsigned int pwm_n_x_pins[] = { GPIOX_7 }; +static const unsigned int pwm_g_x8_pins[] = { GPIOX_8 }; +static const unsigned int pwm_h_x9_pins[] = { GPIOX_9 }; +static const unsigned int pwm_i_x10_pins[] = { GPIOX_10 }; +static const unsigned int clk12_24_x11_pins[] = { GPIOX_11 }; + +/* Bank X func6 */ +static const unsigned int uart_a_rx_x_pins[] = { GPIOX_0 }; +static const unsigned int uart_a_tx_x_pins[] = { GPIOX_1 }; +static const unsigned int uart_c_rx_x_pins[] = { GPIOX_2 }; +static const unsigned int uart_c_tx_x_pins[] = { GPIOX_3 }; +static const unsigned int i2c3_sda_x_pins[] = { GPIOX_4 }; +static const unsigned int i2c3_scl_x_pins[] = { GPIOX_5 }; +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_7 }; +static const unsigned int i2c1_scl_x_pins[] = { GPIOX_8 }; +static const unsigned int uart_d_tx_x_pins[] = { GPIOX_9 }; +static const unsigned int uart_d_rx_x_pins[] = { GPIOX_10 }; + +/* Bank D func1 */ +static const unsigned int pwm_g_d_pins[] = { GPIOD_0 }; +static const unsigned int pwm_h_d_pins[] = { GPIOD_1 }; +static const unsigned int eth_led_act_pins[] = { GPIOD_2 }; +static const unsigned int eth_led_link_pins[] = { GPIOD_3 }; +static const unsigned int pwm_d_pins[] = { GPIOD_4 }; +static const unsigned int pwm_f_pins[] = { GPIOD_5 }; +static const unsigned int pwm_k_d_pins[] = { GPIOD_6 }; + +/* Bank D func2 */ +static const unsigned int uart_a_tx_d_pins[] = { GPIOD_0 }; +static const unsigned int uart_a_rx_d_pins[] = { GPIOD_1 }; +static const unsigned int spi_b_miso_d_pins[] = { GPIOD_2 }; +static const unsigned int spi_b_clk_d_pins[] = { GPIOD_3 }; +static const unsigned int spi_b_mosi_d_pins[] = { GPIOD_4 }; +static const unsigned int spi_b_ss0_d_pins[] = { GPIOD_5 }; +static const unsigned int spi_b_ss1_d_pins[] = { GPIOD_6 }; + +/* Bank D func3 */ +static const unsigned int i2c0_sda_d_pins[] = { GPIOD_0 }; +static const unsigned int i2c0_scl_d_pins[] = { GPIOD_1 }; +static const unsigned int i2c1_sda_d_pins[] = { GPIOD_2 }; +static const unsigned int i2c1_scl_d_pins[] = { GPIOD_3 }; +static const unsigned int pdm_dclk_d_pins[] = { GPIOD_4 }; +static const unsigned int pdm_din0_d_pins[] = { GPIOD_5 }; +static const unsigned int ir_in_d6_pins[] = { GPIOD_6 }; + +/* Bank D func4 */ +static const unsigned int ir_in_d0_pins[] = { GPIOD_0 }; +static const unsigned int ir_out_pins[] = { GPIOD_1 }; +static const unsigned int pwm_i_d_pins[] = { GPIOD_2 }; +static const unsigned int pwm_j_d_pins[] = { GPIOD_3 }; +static const unsigned int i2c3_sda_d_pins[] = { GPIOD_4 }; +static const unsigned int i2c3_scl_d_pins[] = { GPIOD_5 }; + +/* Bank D func5 */ +static const unsigned int tdm_fs0_d_pins[] = { GPIOD_2 }; +static const unsigned int tdm_sclk0_d_pins[] = { GPIOD_3 }; +static const unsigned int mclk_0_d_pins[] = { GPIOD_4 }; +static const unsigned int tdm_d1_d_pins[] = { GPIOD_5 }; +static const unsigned int tdm_d0_d_pins[] = { GPIOD_6 }; + +/* Bank D func6 */ +static const unsigned int uart_d_tx_d_pins[] = { GPIOD_0 }; +static const unsigned int uart_d_rx_d_pins[] = { GPIOD_1 }; +static const unsigned int uart_c_tx_d_pins[] = { GPIOD_2 }; +static const unsigned int uart_c_rx_d_pins[] = { GPIOD_3 }; + +/* Bank A func1 */ +static const unsigned int uart_b_tx_a_pins[] = { GPIOA_0 }; +static const unsigned int uart_b_rx_a_pins[] = { GPIOA_1 }; +static const unsigned int pwm_c_pins[] = { GPIOA_2 }; +static const unsigned int pwm_l_a_pins[] = { GPIOA_3 }; +static const unsigned int i2c1_sda_a_pins[] = { GPIOA_4 }; +static const unsigned int i2c1_scl_a_pins[] = { GPIOA_5 }; + +/* Bank A func2 */ +static const unsigned int pwm_c_hiz_pins[] = { GPIOA_2 }; +static const unsigned int gen_clk_a_pins[] = { GPIOA_3 }; +static const unsigned int pdm_dclk_z_pins[] = { GPIOA_4 }; +static const unsigned int pdm_din0_a_pins[] = { GPIOA_5 }; + +/* Bank A func3 */ +static const unsigned int jtag_a_clk_pins[] = { GPIOA_2 }; +static const unsigned int jtag_a_tms_pins[] = { GPIOA_3 }; +static const unsigned int jtag_a_tdi_pins[] = { GPIOA_4 }; +static const unsigned int jtag_a_tdo_pins[] = { GPIOA_5 }; + +/* Bank A func4 */ +static const unsigned int lcd_clk_a_pins[] = { GPIOA_3 }; +static const unsigned int uart_f_tx_a_pins[] = { GPIOA_4 }; +static const unsigned int uart_f_rx_a_pins[] = { GPIOA_5 }; + +/* Bank A func5 */ +static const unsigned int uart_e_tx_a_pins[] = { GPIOA_2 }; +static const unsigned int uart_e_rx_a_pins[] = { GPIOA_3 }; +static const unsigned int pwm_m_a_pins[] = { GPIOA_4 }; +static const unsigned int pwm_n_a_pins[] = { GPIOA_5 }; + +/* Bank A func6 */ +static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_3 }; +static const unsigned int gen_clk_a4_pins[] = { GPIOA_4 }; +static const unsigned int clk12_24_a_pins[] = { GPIOA_5 }; + +static struct meson_pmx_group c3_periphs_groups[] = { + GPIO_GROUP(GPIOE_0), + GPIO_GROUP(GPIOE_1), + GPIO_GROUP(GPIOE_2), + GPIO_GROUP(GPIOE_3), + GPIO_GROUP(GPIOE_4), + GPIO_GROUP(GPIOB_0), + GPIO_GROUP(GPIOB_1), + GPIO_GROUP(GPIOB_2), + GPIO_GROUP(GPIOB_3), + GPIO_GROUP(GPIOB_4), + GPIO_GROUP(GPIOB_5), + GPIO_GROUP(GPIOB_6), + GPIO_GROUP(GPIOB_7), + GPIO_GROUP(GPIOB_8), + GPIO_GROUP(GPIOB_9), + GPIO_GROUP(GPIOB_10), + GPIO_GROUP(GPIOB_11), + GPIO_GROUP(GPIOB_12), + GPIO_GROUP(GPIOB_13), + GPIO_GROUP(GPIOB_14), + GPIO_GROUP(GPIOC_0), + GPIO_GROUP(GPIOC_1), + GPIO_GROUP(GPIOC_2), + GPIO_GROUP(GPIOC_3), + GPIO_GROUP(GPIOC_4), + GPIO_GROUP(GPIOC_5), + GPIO_GROUP(GPIOC_6), + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOD_0), + GPIO_GROUP(GPIOD_1), + GPIO_GROUP(GPIOD_2), + GPIO_GROUP(GPIOD_3), + GPIO_GROUP(GPIOD_4), + GPIO_GROUP(GPIOD_5), + GPIO_GROUP(GPIOD_6), + GPIO_GROUP(GPIOA_0), + GPIO_GROUP(GPIOA_1), + GPIO_GROUP(GPIOA_2), + GPIO_GROUP(GPIOA_3), + GPIO_GROUP(GPIOA_4), + GPIO_GROUP(GPIOA_5), + GPIO_GROUP(GPIO_TEST_N), + + /* Bank E func1 */ + GROUP(pwm_a, 1), + GROUP(pwm_b, 1), + GROUP(i2c2_sda, 1), + GROUP(i2c2_scl, 1), + GROUP(gen_clk_e, 1), + + /* Bank E func2 */ + GROUP(i2c0_sda_e, 2), + GROUP(i2c0_scl_e, 2), + GROUP(clk_32k_in, 2), + + /* Bank E func3 */ + GROUP(i2c_slave_scl, 3), + GROUP(i2c_slave_sda, 3), + GROUP(clk12_24_e, 3), + + /* Bank B func1 */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_rst, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_nand_ds, 1), + + /* Bank B func2 */ + GROUP(nand_wen_clk, 2), + GROUP(nand_ale, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_cle, 2), + GROUP(nand_ce0, 2), + + /* Bank B func3 */ + GROUP(pwm_g_b, 3), + GROUP(pwm_h_b, 3), + GROUP(pwm_i_b, 3), + GROUP(spif_hold, 3), + GROUP(spif_mo, 3), + GROUP(spif_mi, 3), + GROUP(spif_clk, 3), + GROUP(spif_wp, 3), + GROUP(pwm_j_b, 3), + GROUP(pwm_k_b, 3), + GROUP(pwm_l_b, 3), + GROUP(pwm_m_b, 3), + GROUP(pwm_n_b, 3), + GROUP(spif_cs, 3), + GROUP(spif_clk_loop, 3), + + /* Bank B func4 */ + GROUP(lcd_d0, 4), + GROUP(lcd_d1, 4), + GROUP(lcd_d2, 4), + GROUP(lcd_d3, 4), + GROUP(lcd_d4, 4), + GROUP(lcd_d5, 4), + GROUP(lcd_d6, 4), + GROUP(lcd_d7, 4), + + /* Bank B func5 */ + GROUP(spi_a_mosi_b, 5), + GROUP(spi_a_miso_b, 5), + GROUP(spi_a_clk_b, 5), + GROUP(spi_a_ss0_b, 5), + GROUP(spi_a_ss1_b, 5), + GROUP(spi_a_ss2_b, 5), + GROUP(i2c1_sda_b, 5), + GROUP(i2c1_scl_b, 5), + + /* Bank B func6 */ + GROUP(uart_a_tx_b, 6), + GROUP(uart_a_rx_b, 6), + GROUP(uart_a_cts_b, 6), + GROUP(uart_a_rts_b, 6), + GROUP(uart_d_tx_b, 6), + GROUP(uart_d_rx_b, 6), + GROUP(pdm_dclk_b, 6), + GROUP(pdm_din0_b, 6), + + /* Bank C func1 */ + GROUP(sdcard_d0, 1), + GROUP(sdcard_d1, 1), + GROUP(sdcard_d2, 1), + GROUP(sdcard_d3, 1), + GROUP(sdcard_clk, 1), + GROUP(sdcard_cmd, 1), + GROUP(sdcard_cd, 1), + + /* Bank C func2 */ + GROUP(jtag_b_tdo, 2), + GROUP(jtag_b_tdi, 2), + GROUP(uart_b_rx_c, 2), + GROUP(uart_b_tx_c, 2), + GROUP(jtag_b_clk, 2), + GROUP(jtag_b_tms, 2), + GROUP(gen_clk_c, 2), + + /* Bank C func3 */ + GROUP(tdm_d3, 3), + GROUP(tdm_d2, 3), + GROUP(mclk_1, 3), + GROUP(tdm_sclk1, 3), + GROUP(tdm_fs1, 3), + GROUP(pdm_dclk_c, 3), + GROUP(pdm_din0_c, 3), + + /* Bank C func4 */ + GROUP(spi_a_mosi_c, 4), + GROUP(spi_a_miso_c, 4), + GROUP(spi_a_clk_c, 4), + GROUP(spi_a_ss0_c, 4), + GROUP(spi_a_ss1_c, 4), + + /* Bank C func5 */ + GROUP(pwm_g_c, 5), + GROUP(pwm_h_c, 5), + GROUP(pwm_i_c, 5), + GROUP(pwm_j_c, 5), + GROUP(pwm_k_c, 5), + GROUP(pwm_l_c, 5), + GROUP(pwm_m_c, 5), + + /* Bank C func6 */ + GROUP(uart_a_rx_c, 6), + GROUP(uart_a_tx_c, 6), + GROUP(uart_c_rx_c, 6), + GROUP(uart_c_tx_c, 6), + GROUP(i2c3_sda_c, 6), + GROUP(i2c3_scl_c, 6), + GROUP(clk12_24_c, 6), + + /* Bank X func1 */ + GROUP(sdio_d0, 1), + GROUP(sdio_d1, 1), + GROUP(sdio_d2, 1), + GROUP(sdio_d3, 1), + GROUP(sdio_clk, 1), + GROUP(sdio_cmd, 1), + GROUP(clk12_24_x, 1), + GROUP(uart_e_tx_x, 1), + GROUP(uart_e_rx_x, 1), + GROUP(uart_e_cts, 1), + GROUP(uart_e_rts, 1), + GROUP(pwm_e, 1), + GROUP(pwm_j_x12, 1), + GROUP(pwm_k_x13, 1), + + /* Bank X func2 */ + GROUP(spi_a_mosi_x, 2), + GROUP(spi_a_miso_x, 2), + GROUP(spi_a_clk_x, 2), + GROUP(spi_a_ss0_x, 2), + GROUP(spi_a_ss1_x, 2), + GROUP(spi_a_ss2_x, 2), + GROUP(spi_b_ss2_x6, 2), + GROUP(spi_b_miso_x, 2), + GROUP(spi_b_clk_x, 2), + GROUP(spi_b_mosi_x, 2), + GROUP(spi_b_ss0_x, 2), + GROUP(spi_b_ss1_x, 2), + GROUP(spi_b_ss2_x12, 2), + GROUP(gen_clk_x, 2), + + /* Bank X func3 */ + GROUP(tdm_d1_x, 3), + GROUP(tdm_d0_x, 3), + GROUP(mclk_0_x, 3), + GROUP(tdm_sclk0_x, 3), + GROUP(tdm_fs0_x, 3), + GROUP(pdm_dclk_x5, 3), + GROUP(pdm_din0_x6, 3), + GROUP(pdm_din0_x9, 3), + GROUP(pdm_dclk_x10, 3), + GROUP(clk12_24_x13, 3), + + /* Bank X func4 */ + GROUP(lcd_d8, 4), + GROUP(lcd_d9, 4), + GROUP(lcd_d10, 4), + GROUP(lcd_d11, 4), + GROUP(lcd_d12, 4), + GROUP(lcd_d13, 4), + GROUP(lcd_d14, 4), + GROUP(lcd_d15, 4), + GROUP(lcd_vs, 4), + GROUP(lcd_hs, 4), + GROUP(lcd_den, 4), + GROUP(lcd_d16, 4), + GROUP(lcd_clk_x, 4), + GROUP(lcd_d17, 4), + + /* Bank X func5 */ + GROUP(pwm_g_x0, 5), + GROUP(pwm_h_x1, 5), + GROUP(pwm_i_x2, 5), + GROUP(pwm_j_x3, 5), + GROUP(pwm_k_x4, 5), + GROUP(pwm_l_x, 5), + GROUP(pwm_m_x, 5), + GROUP(pwm_n_x, 5), + GROUP(pwm_g_x8, 5), + GROUP(pwm_h_x9, 5), + GROUP(pwm_i_x10, 5), + GROUP(clk12_24_x11, 5), + + /* Bank X func6 */ + GROUP(uart_a_rx_x, 6), + GROUP(uart_a_tx_x, 6), + GROUP(uart_c_rx_x, 6), + GROUP(uart_c_tx_x, 6), + GROUP(i2c3_sda_x, 6), + GROUP(i2c3_scl_x, 6), + GROUP(i2c1_sda_x, 6), + GROUP(i2c1_scl_x, 6), + GROUP(uart_d_tx_x, 6), + GROUP(uart_d_rx_x, 6), + + /* Bank D func1 */ + GROUP(pwm_g_d, 1), + GROUP(pwm_h_d, 1), + GROUP(eth_led_act, 1), + GROUP(eth_led_link, 1), + GROUP(pwm_d, 1), + GROUP(pwm_f, 1), + GROUP(pwm_k_d, 1), + + /* Bank D func2 */ + GROUP(uart_a_tx_d, 2), + GROUP(uart_a_rx_d, 2), + GROUP(spi_b_miso_d, 2), + GROUP(spi_b_clk_d, 2), + GROUP(spi_b_mosi_d, 2), + GROUP(spi_b_ss0_d, 2), + GROUP(spi_b_ss1_d, 2), + + /* Bank D func3 */ + GROUP(i2c0_sda_d, 3), + GROUP(i2c0_scl_d, 3), + GROUP(i2c1_sda_d, 3), + GROUP(i2c1_scl_d, 3), + GROUP(pdm_dclk_d, 3), + GROUP(pdm_din0_d, 3), + GROUP(ir_in_d6, 3), + + /* Bank D func4 */ + GROUP(ir_in_d0, 4), + GROUP(ir_out, 4), + GROUP(pwm_i_d, 4), + GROUP(pwm_j_d, 4), + GROUP(i2c3_sda_d, 4), + GROUP(i2c3_scl_d, 4), + + /* Bank D func5 */ + GROUP(tdm_fs0_d, 5), + GROUP(tdm_sclk0_d, 5), + GROUP(mclk_0_d, 5), + GROUP(tdm_d1_d, 5), + GROUP(tdm_d0_d, 5), + + /* Bank D func6 */ + GROUP(uart_d_tx_d, 6), + GROUP(uart_d_rx_d, 6), + GROUP(uart_c_tx_d, 6), + GROUP(uart_c_rx_d, 6), + + /* Bank A func1 */ + GROUP(uart_b_tx_a, 1), + GROUP(uart_b_rx_a, 1), + GROUP(pwm_c, 1), + GROUP(pwm_l_a, 1), + GROUP(i2c1_sda_a, 1), + GROUP(i2c1_scl_a, 1), + + /* Bank A func2 */ + GROUP(pwm_c_hiz, 2), + GROUP(gen_clk_a, 2), + GROUP(pdm_dclk_z, 2), + GROUP(pdm_din0_a, 2), + + /* Bank A func3 */ + GROUP(jtag_a_clk, 3), + GROUP(jtag_a_tms, 3), + GROUP(jtag_a_tdi, 3), + GROUP(jtag_a_tdo, 3), + + /* Bank A func4 */ + GROUP(lcd_clk_a, 4), + GROUP(uart_f_tx_a, 4), + GROUP(uart_f_rx_a, 4), + + /* Bank A func5 */ + GROUP(uart_e_tx_a, 5), + GROUP(uart_e_rx_a, 5), + GROUP(pwm_m_a, 5), + GROUP(pwm_n_a, 5), + + /* Bank A func6 */ + GROUP(spi_a_mosi_a, 6), + GROUP(gen_clk_a4, 6), + GROUP(clk12_24_a, 6), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIO_TEST_N", + + "GPIOE_0", "GPIOE_1", "GPIOE_2", "GPIOE_3", "GPIOE_4", + + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", + "GPIOB_5", "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", + "GPIOB_10", "GPIOB_11", "GPIOB_12", "GPIOB_13", + "GPIOB_14", + + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", + "GPIOC_5", "GPIOC_6", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", + + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", + "GPIOD_5", "GPIOD_6", + + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", + "GPIOA_5", +}; + +static const char * const uart_a_groups[] = { + "uart_a_tx_b", "uart_a_rx_b", "uart_a_cts_b", "uart_a_rts_b", + "uart_a_rx_c", "uart_a_tx_c", "uart_a_rx_x", "uart_a_tx_x", + "uart_a_tx_d", "uart_a_rx_d", +}; + +static const char * const uart_b_groups[] = { + "uart_b_rx_c", "uart_b_tx_c", "uart_b_tx_a", "uart_b_rx_a", +}; + +static const char * const uart_c_groups[] = { + "uart_c_rx_c", "uart_c_tx_c", + "uart_c_rx_x", "uart_c_tx_x", + "uart_c_tx_d", "uart_c_rx_d", +}; + +static const char * const uart_d_groups[] = { + "uart_d_tx_b", "uart_d_rx_b", "uart_d_tx_d", "uart_d_rx_d", + "uart_d_rx_x", "uart_d_tx_x", +}; + +static const char * const uart_e_groups[] = { + "uart_e_cts", "uart_e_tx_x", "uart_e_rx_x", "uart_e_rts", + "uart_e_tx_a", "uart_e_rx_a", +}; + +static const char * const i2c0_groups[] = { + "i2c0_sda_e", "i2c0_scl_e", + "i2c0_sda_d", "i2c0_scl_d", +}; + +static const char * const i2c1_groups[] = { + "i2c1_sda_x", "i2c1_scl_x", + "i2c1_sda_d", "i2c1_scl_d", + "i2c1_sda_a", "i2c1_scl_a", + "i2c1_sda_b", "i2c1_scl_b", +}; + +static const char * const i2c2_groups[] = { + "i2c2_sda", "i2c2_scl", +}; + +static const char * const i2c3_groups[] = { + "i2c3_sda_c", "i2c3_scl_c", + "i2c3_sda_x", "i2c3_scl_x", + "i2c3_sda_d", "i2c3_scl_d", +}; + +static const char * const i2c_slave_groups[] = { + "i2c_slave_scl", "i2c_slave_sda", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f", +}; + +static const char * const pwm_g_groups[] = { + "pwm_g_b", "pwm_g_c", "pwm_g_d", "pwm_g_x0", "pwm_g_x8", +}; + +static const char * const pwm_h_groups[] = { + "pwm_h_b", "pwm_h_c", "pwm_h_d", "pwm_h_x1", "pwm_h_x9", +}; + +static const char * const pwm_i_groups[] = { + "pwm_i_b", "pwm_i_c", "pwm_i_d", "pwm_i_x2", "pwm_i_x10", +}; + +static const char * const pwm_j_groups[] = { + "pwm_j_c", "pwm_j_d", "pwm_j_b", "pwm_j_x3", "pwm_j_x12", +}; + +static const char * const pwm_k_groups[] = { + "pwm_k_c", "pwm_k_d", "pwm_k_b", "pwm_k_x4", "pwm_k_x13", +}; + +static const char * const pwm_l_groups[] = { + "pwm_l_c", "pwm_l_x", "pwm_l_b", "pwm_l_a", +}; + +static const char * const pwm_m_groups[] = { + "pwm_m_c", "pwm_m_x", "pwm_m_a", "pwm_m_b", +}; + +static const char * const pwm_n_groups[] = { + "pwm_n_x", "pwm_n_a", "pwm_n_b", +}; + +static const char * const pwm_c_hiz_groups[] = { + "pwm_c_hiz", +}; + +static const char * const ir_out_groups[] = { + "ir_out", +}; + +static const char * const ir_in_groups[] = { + "ir_in_d0", "ir_in_d6", +}; + +static const char * const jtag_a_groups[] = { + "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo", +}; + +static const char * const jtag_b_groups[] = { + "jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms", +}; + +static const char * const gen_clk_groups[] = { + "gen_clk_e", "gen_clk_c", "gen_clk_a", "gen_clk_x", + "gen_clk_a4", +}; + +static const char * const clk12_24_groups[] = { + "clk12_24_e", "clk12_24_c", "clk12_24_x", "clk12_24_a", + "clk12_24_x13", "clk12_24_x11", +}; + +static const char * const clk_32k_in_groups[] = { + "clk_32k_in", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds", + "nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", + "nand_ce0", +}; + +static const char * const spif_groups[] = { + "spif_mo", "spif_mi", "spif_wp", "spif_cs", + "spif_clk", "spif_hold", "spif_clk_loop", +}; + +static const char * const spi_a_groups[] = { + "spi_a_clk_b", "spi_a_ss0_b", "spi_a_ss1_b", "spi_a_ss2_b", + "spi_a_mosi_b", "spi_a_miso_b", + + "spi_a_clk_c", "spi_a_ss0_c", "spi_a_ss1_c", + "spi_a_mosi_c", "spi_a_miso_c", + + "spi_a_clk_x", "spi_a_ss0_x", "spi_a_ss1_x", "spi_a_ss2_x", + "spi_a_mosi_x", "spi_a_miso_x", + "spi_a_mosi_a", +}; + +static const char * const spi_b_groups[] = { + "spi_b_clk_x", "spi_b_ss0_x", "spi_b_ss1_x", "spi_b_ss2_x6", + "spi_b_miso_x", "spi_b_mosi_x", "spi_b_ss2_x12", + + "spi_b_clk_d", "spi_b_ss0_d", "spi_b_ss1_d", "spi_b_miso_d", + "spi_b_mosi_d", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", + "sdcard_cd", "sdcard_clk", "sdcard_cmd", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", + "sdio_clk", "sdio_cmd", +}; + +static const char * const pdm_groups[] = { + "pdm_dclk_c", "pdm_din0_c", "pdm_dclk_d", "pdm_din0_d", + "pdm_dclk_z", "pdm_din0_a", "pdm_dclk_b", "pdm_din0_b", + "pdm_dclk_x5", "pdm_din0_x6", "pdm_din0_x9", "pdm_dclk_x10", +}; + +static const char * const eth_groups[] = { + "eth_led_act", "eth_led_link", +}; + +static const char * const mclk_0_groups[] = { + "mclk_0_x", "mclk_0_d", +}; + +static const char * const mclk_1_groups[] = { + "mclk_1", +}; + +static const char * const tdm_groups[] = { + "tdm_d3", "tdm_d2", "tdm_fs1", "tdm_d1_x", "tdm_d0_x", + "tdm_d1_d", "tdm_d0_d", "tdm_sclk1", "tdm_fs0_x", "tdm_fs0_d", + "tdm_sclk0_x", "tdm_sclk0_d", +}; + +static const char * const lcd_groups[] = { + "lcd_d0", "lcd_d1", "lcd_d2", "lcd_d3", "lcd_d4", + "lcd_d5", "lcd_d6", "lcd_d7", "lcd_d8", "lcd_d9", + "lcd_d10", "lcd_d11", "lcd_d12", "lcd_d13", "lcd_d14", + "lcd_d15", "lcd_d16", "lcd_d17", "lcd_den", + "lcd_clk_a", "lcd_clk_x", "lcd_hs", "lcd_vs", +}; + +static struct meson_pmx_func c3_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(uart_d), + FUNCTION(uart_e), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(i2c_slave), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(pwm_g), + FUNCTION(pwm_h), + FUNCTION(pwm_i), + FUNCTION(pwm_j), + FUNCTION(pwm_k), + FUNCTION(pwm_l), + FUNCTION(pwm_m), + FUNCTION(pwm_n), + FUNCTION(pwm_c_hiz), + FUNCTION(ir_out), + FUNCTION(ir_in), + FUNCTION(jtag_a), + FUNCTION(jtag_b), + FUNCTION(gen_clk), + FUNCTION(clk12_24), + FUNCTION(clk_32k_in), + FUNCTION(emmc), + FUNCTION(nand), + FUNCTION(spif), + FUNCTION(spi_a), + FUNCTION(spi_b), + FUNCTION(sdcard), + FUNCTION(sdio), + FUNCTION(pdm), + FUNCTION(eth), + FUNCTION(mclk_0), + FUNCTION(mclk_1), + FUNCTION(tdm), + FUNCTION(lcd), +}; + +static struct meson_bank c3_periphs_banks[] = { + /* name first last irq pullen pull dir out in ds */ + BANK_DS("X", GPIOX_0, GPIOX_13, 40, 53, + 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0), + BANK_DS("D", GPIOD_0, GPIOD_6, 33, 39, + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0), + BANK_DS("E", GPIOE_0, GPIOE_4, 22, 26, + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0), + BANK_DS("C", GPIOC_0, GPIOC_6, 15, 21, + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0), + BANK_DS("B", GPIOB_0, GPIOB_14, 0, 14, + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0), + BANK_DS("A", GPIOA_0, GPIOA_5, 27, 32, + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0), + BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 54, 54, + 0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0, 0x77, 0), +}; + +static struct meson_pmx_bank c3_periphs_pmx_banks[] = { + /* name first last reg offset */ + BANK_PMX("B", GPIOB_0, GPIOB_14, 0x00, 0), + BANK_PMX("X", GPIOX_0, GPIOX_13, 0x03, 0), + BANK_PMX("C", GPIOC_0, GPIOC_6, 0x09, 0), + BANK_PMX("A", GPIOA_0, GPIOA_5, 0x0b, 0), + BANK_PMX("D", GPIOD_0, GPIOD_6, 0x10, 0), + BANK_PMX("E", GPIOE_0, GPIOE_4, 0x12, 0), + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x02, 0), +}; + +static struct meson_axg_pmx_data c3_periphs_pmx_banks_data = { + .pmx_banks = c3_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(c3_periphs_pmx_banks), +}; + +static struct meson_pinctrl_data c3_periphs_pinctrl_data = { + .name = "periphs-banks", + .pins = c3_periphs_pins, + .groups = c3_periphs_groups, + .funcs = c3_periphs_functions, + .banks = c3_periphs_banks, + .num_pins = ARRAY_SIZE(c3_periphs_pins), + .num_groups = ARRAY_SIZE(c3_periphs_groups), + .num_funcs = ARRAY_SIZE(c3_periphs_functions), + .num_banks = ARRAY_SIZE(c3_periphs_banks), + .pmx_ops = &meson_axg_pmx_ops, + .pmx_data = &c3_periphs_pmx_banks_data, + .parse_dt = &meson_a1_parse_dt_extra, +}; + +static const struct of_device_id c3_pinctrl_dt_match[] = { + { + .compatible = "amlogic,c3-periphs-pinctrl", + .data = &c3_periphs_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, c3_pinctrl_dt_match); + +static struct platform_driver c3_pinctrl_driver = { + .probe = meson_pinctrl_probe, + .driver = { + .name = "amlogic-c3-pinctrl", + .of_match_table = c3_pinctrl_dt_match, + }, +}; +module_platform_driver(c3_pinctrl_driver); + +MODULE_AUTHOR("Huqiang Qin "); +MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic C3 SoC"); +MODULE_LICENSE("Dual BSD/GPL"); -- cgit From 87b549efcb0f7934b0916d2a00607a878b6f1e0f Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Mon, 17 Jul 2023 15:16:52 -0500 Subject: pinctrl: amd: Don't show `Invalid config param` errors On some systems amd_pinconf_set() is called with parameters 0x8 (PIN_CONFIG_DRIVE_PUSH_PULL) or 0x14 (PIN_CONFIG_PERSIST_STATE) which are not supported by pinctrl-amd. Don't show an err message when called with an invalid parameter, downgrade this to debug instead. Cc: stable@vger.kernel.org # 6.1 Fixes: 635a750d958e1 ("pinctrl: amd: Use amd_pinconf_set() for all config options") Signed-off-by: Mario Limonciello Link: https://lore.kernel.org/r/20230717201652.17168-1-mario.limonciello@amd.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 3c4220be30ec..baa3629f71a2 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -769,7 +769,7 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev, break; default: - dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", + dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; } @@ -822,7 +822,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, break; default: - dev_err(&gpio_dev->pdev->dev, + dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", param); ret = -ENOTSUPP; } -- cgit From be9f6d56381d995f600524ad99fa8a9cc5bd5c49 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Jul 2023 21:20:57 +0200 Subject: pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM Add driver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8250 LPASS pin controller, with difference in one new pin (gpio14) belonging to swr_tx_data. Link: https://lore.kernel.org/r/20230719192058.433517-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/qcom/Kconfig | 10 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c | 167 ++++++++++++++++++++++++ 3 files changed, 178 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 634c75336983..643f1d7a531e 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -77,6 +77,16 @@ config PINCTRL_SM8250_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform. +config PINCTRL_SM8350_LPASS_LPI + tristate "Qualcomm Technologies Inc SM8350 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM8350 + platform. + config PINCTRL_SM8450_LPASS_LPI tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 426ddbf35f32..76ffcfbffc8e 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o +obj-$(CONFIG_PINCTRL_SM8350_LPASS_LPI) += pinctrl-sm8350-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8550) += pinctrl-sm8550.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c new file mode 100644 index 000000000000..f889c779bccd --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023 Linaro Ltd. + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; + +static const struct pinctrl_pin_desc sm8350_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; + +static const struct lpi_pingroup sm8350_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), + LPI_PINGROUP(14, 6, swr_tx_data, _, _, _), +}; + +static const struct lpi_function sm8350_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sm8350_lpi_data = { + .pins = sm8350_lpi_pins, + .npins = ARRAY_SIZE(sm8350_lpi_pins), + .groups = sm8350_groups, + .ngroups = ARRAY_SIZE(sm8350_groups), + .functions = sm8350_functions, + .nfunctions = ARRAY_SIZE(sm8350_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm8350-lpass-lpi-pinctrl", + .data = &sm8350_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm8350-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; +module_platform_driver(lpi_pinctrl_driver); + +MODULE_AUTHOR("Krzysztof Kozlowski "); +MODULE_DESCRIPTION("QTI SM8350 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); -- cgit From f4b2ce40fd99ddb5c2ab9f1193454080f6714dfe Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Jul 2023 17:09:59 +0200 Subject: pinctrl: renesas: rzv2m: Use devm_clk_get_enabled() helper Simplify clock handling by using the devm_clk_get_enabled() helper, instead of open-coding the same operations. Move the clock pointer from the driver-private data to a local variable, as it is not needed outside the .probe() callback. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/cca0b1795fd0335401bdf2be393ab84445e04095.1688396836.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl-rzv2m.c | 32 +++++--------------------------- 1 file changed, 5 insertions(+), 27 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c index 35b23c1a5684..f0852296c1d3 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -118,7 +118,6 @@ struct rzv2m_pinctrl { const struct rzv2m_pinctrl_data *data; void __iomem *base; struct device *dev; - struct clk *clk; struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; @@ -1039,14 +1038,10 @@ static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl) return 0; } -static void rzv2m_pinctrl_clk_disable(void *data) -{ - clk_disable_unprepare(data); -} - static int rzv2m_pinctrl_probe(struct platform_device *pdev) { struct rzv2m_pinctrl *pctrl; + struct clk *clk; int ret; pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); @@ -1063,32 +1058,15 @@ static int rzv2m_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pctrl->base)) return PTR_ERR(pctrl->base); - pctrl->clk = devm_clk_get(pctrl->dev, NULL); - if (IS_ERR(pctrl->clk)) { - ret = PTR_ERR(pctrl->clk); - dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); - return ret; - } + clk = devm_clk_get_enabled(pctrl->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(pctrl->dev, PTR_ERR(clk), + "failed to enable GPIO clk\n"); spin_lock_init(&pctrl->lock); platform_set_drvdata(pdev, pctrl); - ret = clk_prepare_enable(pctrl->clk); - if (ret) { - dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); - return ret; - } - - ret = devm_add_action_or_reset(&pdev->dev, rzv2m_pinctrl_clk_disable, - pctrl->clk); - if (ret) { - dev_err(pctrl->dev, - "failed to register GPIO clk disable action, %i\n", - ret); - return ret; - } - ret = rzv2m_pinctrl_register(pctrl); if (ret) return ret; -- cgit From 95eb19869401850f069723b296170b8b3bd5be9e Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 22 Jul 2023 22:41:56 +0200 Subject: pinctrl: renesas: rzg2l: Use devm_clk_get_enabled() helper The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the need of a dedicated function used with devm_add_action_or_reset(). While at it, use dev_err_probe() which filters -EPROBE_DEFER. Signed-off-by: Christophe JAILLET Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/a4a586337d692f0ca396b80d275ba634eb419593.1690058500.git.christophe.jaillet@wanadoo.fr [geert: Make clk local to rzg2l_pinctrl_probe()] Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 32 +++++--------------------------- 1 file changed, 5 insertions(+), 27 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index b53d26167da5..0b8d27eb66c0 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -144,7 +144,6 @@ struct rzg2l_pinctrl { const struct rzg2l_pinctrl_data *data; void __iomem *base; struct device *dev; - struct clk *clk; struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; @@ -1470,14 +1469,10 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) return 0; } -static void rzg2l_pinctrl_clk_disable(void *data) -{ - clk_disable_unprepare(data); -} - static int rzg2l_pinctrl_probe(struct platform_device *pdev) { struct rzg2l_pinctrl *pctrl; + struct clk *clk; int ret; BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > @@ -1500,33 +1495,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pctrl->base)) return PTR_ERR(pctrl->base); - pctrl->clk = devm_clk_get(pctrl->dev, NULL); - if (IS_ERR(pctrl->clk)) { - ret = PTR_ERR(pctrl->clk); - dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); - return ret; - } + clk = devm_clk_get_enabled(pctrl->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(pctrl->dev, PTR_ERR(clk), + "failed to enable GPIO clk\n"); spin_lock_init(&pctrl->lock); spin_lock_init(&pctrl->bitmap_lock); platform_set_drvdata(pdev, pctrl); - ret = clk_prepare_enable(pctrl->clk); - if (ret) { - dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); - return ret; - } - - ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, - pctrl->clk); - if (ret) { - dev_err(pctrl->dev, - "failed to register GPIO clk disable action, %i\n", - ret); - return ret; - } - ret = rzg2l_pinctrl_register(pctrl); if (ret) return ret; -- cgit From 63f7c8445ffe6667ac4cc9720ca36ad7d407709f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 24 Jul 2023 13:39:57 +0200 Subject: pinctrl: qcom: Introduce SM6115 LPI pinctrl driver Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/qcom/Kconfig | 9 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 175 ++++++++++++++++++++++++ 3 files changed, 185 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 643f1d7a531e..f84c0d3b7951 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,15 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform. +config PINCTRL_SM6115_LPASS_LPI + tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform. + config PINCTRL_SM8250_LPASS_LPI tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 76ffcfbffc8e..5910e08c84ce 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c new file mode 100644 index 000000000000..2b09bf171a2c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, 2023 Linaro Ltd. + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic01_clk, + LPI_MUX_dmic01_data, + LPI_MUX_dmic23_clk, + LPI_MUX_dmic23_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_mclk, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; +static int gpio15_pins[] = { 15 }; +static int gpio16_pins[] = { 16 }; +static int gpio17_pins[] = { 17 }; +static int gpio18_pins[] = { 18 }; + +static const struct pinctrl_pin_desc sm6115_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), +}; + +static const char * const dmic01_clk_groups[] = { "gpio6" }; +static const char * const dmic01_data_groups[] = { "gpio7" }; +static const char * const dmic23_clk_groups[] = { "gpio8" }; +static const char * const dmic23_data_groups[] = { "gpio9" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const i2s3_clk_groups[] = { "gpio14" }; +static const char * const i2s3_data_groups[] = { "gpio16", "gpio17" }; +static const char * const i2s3_ws_groups[] = { "gpio15" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2" }; +static const char * const wsa_mclk_groups[] = { "gpio18" }; + +static const struct lpi_pingroup sm6115_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, _, _), + LPI_PINGROUP(10, LPI_NO_SLEW, i2s2_clk, _, _, _), + LPI_PINGROUP(11, LPI_NO_SLEW, i2s2_ws, _, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(18, 14, wsa_mclk, _, _, _), +}; + +static const struct lpi_function sm6115_functions[] = { + LPI_FUNCTION(dmic01_clk), + LPI_FUNCTION(dmic01_data), + LPI_FUNCTION(dmic23_clk), + LPI_FUNCTION(dmic23_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_mclk), +}; + +static const struct lpi_pinctrl_variant_data sm6115_lpi_data = { + .pins = sm6115_lpi_pins, + .npins = ARRAY_SIZE(sm6115_lpi_pins), + .groups = sm6115_groups, + .ngroups = ARRAY_SIZE(sm6115_groups), + .functions = sm6115_functions, + .nfunctions = ARRAY_SIZE(sm6115_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { .compatible = "qcom,sm6115-lpass-lpi-pinctrl", .data = &sm6115_lpi_data }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm6115-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM6115 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); -- cgit From b56e23bf0c606b68df2919317f7065dabe3c4e86 Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Wed, 19 Jul 2023 23:22:51 +0300 Subject: pinctrl: core: handle radix_tree_insert() errors in pinctrl_generic_add_group() pinctrl_generic_add_group() doesn't check the result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20230719202253.13469-2-s.shtylyov@omp.ru Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 401886c81344..3c3fc4ae0f2f 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -633,7 +633,7 @@ int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name, int *pins, int num_pins, void *data) { struct group_desc *group; - int selector; + int selector, error; if (!name) return -EINVAL; @@ -653,7 +653,9 @@ int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name, group->num_pins = num_pins; group->data = data; - radix_tree_insert(&pctldev->pin_group_tree, selector, group); + error = radix_tree_insert(&pctldev->pin_group_tree, selector, group); + if (error) + return error; pctldev->num_groups++; -- cgit From ecfe9a015d3e1e46504d5b3de7eef1f2d186194a Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Wed, 19 Jul 2023 23:22:52 +0300 Subject: pinctrl: core: handle radix_tree_insert() errors in pinctrl_register_one_pin() pinctrl_register_one_pin() doesn't check the result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20230719202253.13469-3-s.shtylyov@omp.ru Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 3c3fc4ae0f2f..e9dc9638120a 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -205,6 +205,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin) { struct pin_desc *pindesc; + int error; pindesc = pin_desc_get(pctldev, pin->number); if (pindesc) { @@ -226,18 +227,25 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, } else { pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", pin->number); if (!pindesc->name) { - kfree(pindesc); - return -ENOMEM; + error = -ENOMEM; + goto failed; } pindesc->dynamic_name = true; } pindesc->drv_data = pin->drv_data; - radix_tree_insert(&pctldev->pin_desc_tree, pin->number, pindesc); + error = radix_tree_insert(&pctldev->pin_desc_tree, pin->number, pindesc); + if (error) + goto failed; + pr_debug("registered pin %d (%s) on %s\n", pin->number, pindesc->name, pctldev->desc->name); return 0; + +failed: + kfree(pindesc); + return error; } static int pinctrl_register_pins(struct pinctrl_dev *pctldev, -- cgit From 6ec89cd4d17bd5e818c335b72c736a5094ea66d7 Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Wed, 19 Jul 2023 23:22:53 +0300 Subject: pinctrl: pinmux: handle radix_tree_insert() errors in pinmux_generic_add_function() pinctrl_generic_add_function() doesn't check result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20230719202253.13469-4-s.shtylyov@omp.ru Signed-off-by: Linus Walleij --- drivers/pinctrl/pinmux.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 82c750a31952..2a180a5d64a4 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -872,7 +872,7 @@ int pinmux_generic_add_function(struct pinctrl_dev *pctldev, void *data) { struct function_desc *function; - int selector; + int selector, error; if (!name) return -EINVAL; @@ -892,7 +892,9 @@ int pinmux_generic_add_function(struct pinctrl_dev *pctldev, function->num_group_names = num_groups; function->data = data; - radix_tree_insert(&pctldev->pin_function_tree, selector, function); + error = radix_tree_insert(&pctldev->pin_function_tree, selector, function); + if (error) + return error; pctldev->num_functions++; -- cgit From 0516dd657246165016e0cdb4b4fc5e34e58c2372 Mon Sep 17 00:00:00 2001 From: Sai Krishna Potthuri Date: Mon, 31 Jul 2023 15:20:26 +0530 Subject: pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high impedance Add support to handle 'output-enable' and 'bias-high-impedance' configurations. Using these pinctrl properties observed hang issues with older PMUFW(Xilinx ZynqMP Platform Management Firmware), hence reverted the patch. Commit 9989bc33c4894e075167 ("Revert "pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high-impedance""). Support for configuring these properties added in PMUFW Configuration Set version 2.0. When there is a request for these configurations from pinctrl driver for ZynqMP platform, xilinx firmware driver checks for this version before configuring these properties to avoid the hang issue and proceeds further only when firmware version is >=2 otherwise it returns error. Signed-off-by: Sai Krishna Potthuri Reviewed-by: Michal Simek Link: https://lore.kernel.org/r/20230731095026.3766675-5-sai.krishna.potthuri@amd.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-zynqmp.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 8d2cb0999f2f..f2be341f73e1 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -415,6 +415,10 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_ENABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; case PIN_CONFIG_MODE_LOW_POWER: /* * These cases are mentioned in dts but configurable @@ -423,6 +427,11 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, */ ret = 0; break; + case PIN_CONFIG_OUTPUT_ENABLE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_DISABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; default: dev_warn(pctldev->dev, "unsupported configuration parameter '%u'\n", -- cgit From 1b1db9e02af40cb7b44693dd46d488321cac72cb Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 24 Jul 2023 13:39:57 +0200 Subject: pinctrl: qcom: Introduce SM6115 LPI pinctrl driver Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 9 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 175 ++++++++++++++++++++++++ 3 files changed, 185 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 634c75336983..c6ef38032c05 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,15 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform. +config PINCTRL_SM6115_LPASS_LPI + tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform. + config PINCTRL_SM8250_LPASS_LPI tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 426ddbf35f32..d1179d8b2c42 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c new file mode 100644 index 000000000000..2b09bf171a2c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, 2023 Linaro Ltd. + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic01_clk, + LPI_MUX_dmic01_data, + LPI_MUX_dmic23_clk, + LPI_MUX_dmic23_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_mclk, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; +static int gpio15_pins[] = { 15 }; +static int gpio16_pins[] = { 16 }; +static int gpio17_pins[] = { 17 }; +static int gpio18_pins[] = { 18 }; + +static const struct pinctrl_pin_desc sm6115_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), +}; + +static const char * const dmic01_clk_groups[] = { "gpio6" }; +static const char * const dmic01_data_groups[] = { "gpio7" }; +static const char * const dmic23_clk_groups[] = { "gpio8" }; +static const char * const dmic23_data_groups[] = { "gpio9" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const i2s3_clk_groups[] = { "gpio14" }; +static const char * const i2s3_data_groups[] = { "gpio16", "gpio17" }; +static const char * const i2s3_ws_groups[] = { "gpio15" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2" }; +static const char * const wsa_mclk_groups[] = { "gpio18" }; + +static const struct lpi_pingroup sm6115_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, _, _), + LPI_PINGROUP(10, LPI_NO_SLEW, i2s2_clk, _, _, _), + LPI_PINGROUP(11, LPI_NO_SLEW, i2s2_ws, _, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(18, 14, wsa_mclk, _, _, _), +}; + +static const struct lpi_function sm6115_functions[] = { + LPI_FUNCTION(dmic01_clk), + LPI_FUNCTION(dmic01_data), + LPI_FUNCTION(dmic23_clk), + LPI_FUNCTION(dmic23_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_mclk), +}; + +static const struct lpi_pinctrl_variant_data sm6115_lpi_data = { + .pins = sm6115_lpi_pins, + .npins = ARRAY_SIZE(sm6115_lpi_pins), + .groups = sm6115_groups, + .ngroups = ARRAY_SIZE(sm6115_groups), + .functions = sm6115_functions, + .nfunctions = ARRAY_SIZE(sm6115_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { .compatible = "qcom,sm6115-lpass-lpi-pinctrl", .data = &sm6115_lpi_data }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm6115-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM6115 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); -- cgit From 0a80e1d3cfc0effa9679da157a63b668ae7e651f Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Fri, 21 Jul 2023 15:42:41 +0530 Subject: pinctrl: qcom: Remove the unused _groups variable build warning When building with clang toolchain and arm64-randconfig-r015-20230712 kernel test robot reports the below warning. drivers/pinctrl/qcom/pinctrl-ipq5018.c:244:27: warning: unused variable '_groups' [-Wunused-const-variable] static const char * const _groups[] = { ^ 1 warning generated. static const char * const _groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", }; Fixing it by removing the variable. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202307120814.vWPY6URk-lkp@intel.com/ Fixes: 725d1c891658 ("pinctrl: qcom: Add IPQ5018 pinctrl driver") Signed-off-by: Sricharan Ramabadhran Reviewed-by: Nick Desaulniers Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1689934361-32642-1-git-send-email-quic_srichara@quicinc.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-ipq5018.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c index ed58f750f1eb..e2951f81c3ee 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c @@ -241,16 +241,6 @@ static const char * const atest_char_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio37", }; -static const char * const _groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", - "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", - "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", - "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", - "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", "gpio46", -}; - static const char * const wci_txd_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio42", "gpio43", "gpio44", "gpio45", -- cgit From eb3d3349a3de70cd8b5994dcf87389219e719261 Mon Sep 17 00:00:00 2001 From: Huqiang Qin Date: Mon, 24 Jul 2023 14:01:07 +0800 Subject: pinctrl: Replace the IRQ number in the driver with the IRQID macro definition Replacing IRQ numbers with IRQID macro definitions makes driver code easier to understand. Associated platforms: - Amlogic Meson-G12A - Amlogic Meson-G12B - Amlogic Meson-SM1 Signed-off-by: Huqiang Qin Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20230724060108.1403662-3-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-g12a.c | 35 +++++++++++++++--------------- 1 file changed, 18 insertions(+), 17 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index d182a575981e..3cd86d6a0a60 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -8,6 +8,7 @@ */ #include +#include #include "pinctrl-meson.h" #include "pinctrl-meson-axg-pmx.h" @@ -1318,31 +1319,31 @@ static struct meson_pmx_func meson_g12a_aobus_functions[] = { static struct meson_bank meson_g12a_periphs_banks[] = { /* name first last irq pullen pull dir out in ds */ - BANK_DS("Z", GPIOZ_0, GPIOZ_15, 12, 27, - 4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0), - BANK_DS("H", GPIOH_0, GPIOH_8, 28, 36, - 3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0), - BANK_DS("BOOT", BOOT_0, BOOT_15, 37, 52, - 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0), - BANK_DS("C", GPIOC_0, GPIOC_7, 53, 60, - 1, 0, 1, 0, 3, 0, 4, 0, 5, 0, 1, 0), - BANK_DS("A", GPIOA_0, GPIOA_15, 61, 76, - 5, 0, 5, 0, 16, 0, 17, 0, 18, 0, 6, 0), - BANK_DS("X", GPIOX_0, GPIOX_19, 77, 96, - 2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0), + BANK_DS("Z", GPIOZ_0, GPIOZ_15, IRQID_GPIOZ_0, IRQID_GPIOZ_15, + 4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0), + BANK_DS("H", GPIOH_0, GPIOH_8, IRQID_GPIOH_0, IRQID_GPIOH_8, + 3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0), + BANK_DS("BOOT", BOOT_0, BOOT_15, IRQID_BOOT_0, IRQID_BOOT_15, + 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0), + BANK_DS("C", GPIOC_0, GPIOC_7, IRQID_GPIOC_0, IRQID_GPIOC_7, + 1, 0, 1, 0, 3, 0, 4, 0, 5, 0, 1, 0), + BANK_DS("A", GPIOA_0, GPIOA_15, IRQID_GPIOA_0, IRQID_GPIOA_15, + 5, 0, 5, 0, 16, 0, 17, 0, 18, 0, 6, 0), + BANK_DS("X", GPIOX_0, GPIOX_19, IRQID_GPIOX_0, IRQID_GPIOX_19, + 2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0), }; static struct meson_bank meson_g12a_aobus_banks[] = { /* name first last irq pullen pull dir out in ds */ - BANK_DS("AO", GPIOAO_0, GPIOAO_11, 0, 11, 3, 0, 2, 0, 0, 0, 4, 0, 1, 0, - 0, 0), + BANK_DS("AO", GPIOAO_0, GPIOAO_11, IRQID_GPIOAO_0, IRQID_GPIOAO_11, + 3, 0, 2, 0, 0, 0, 4, 0, 1, 0, 0, 0), /* GPIOE actually located in the AO bank */ - BANK_DS("E", GPIOE_0, GPIOE_2, 97, 99, 3, 16, 2, 16, 0, 16, 4, 16, 1, - 16, 1, 0), + BANK_DS("E", GPIOE_0, GPIOE_2, IRQID_GPIOE_0, IRQID_GPIOE_2, + 3, 16, 2, 16, 0, 16, 4, 16, 1, 16, 1, 0), }; static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { - /* name first lask reg offset */ + /* name first last reg offset */ BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0), BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0), BANK_PMX("BOOT", BOOT_0, BOOT_15, 0x0, 0), -- cgit From f941714a7c7698eadb59bc27d34d6d6f38982705 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 21 Jun 2023 13:04:09 +0300 Subject: pinctrl: mcp23s08: check return value of devm_kasprintf() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit devm_kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 0f04a81784fe ("pinctrl: mcp23s08: Split to three parts: core, I²C, SPI") Signed-off-by: Claudiu Beznea Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230621100409.1608395-1-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08_spi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-mcp23s08_spi.c b/drivers/pinctrl/pinctrl-mcp23s08_spi.c index 9ae10318f6f3..ea059b9c5542 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08_spi.c +++ b/drivers/pinctrl/pinctrl-mcp23s08_spi.c @@ -91,18 +91,28 @@ static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, mcp->reg_shift = 0; mcp->chip.ngpio = 8; mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s08.%d", addr); + if (!mcp->chip.label) + return -ENOMEM; config = &mcp23x08_regmap; name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + if (!name) + return -ENOMEM; + break; case MCP_TYPE_S17: mcp->reg_shift = 1; mcp->chip.ngpio = 16; mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s17.%d", addr); + if (!mcp->chip.label) + return -ENOMEM; config = &mcp23x17_regmap; name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + if (!name) + return -ENOMEM; + break; case MCP_TYPE_S18: -- cgit From c7351b46d0da5f0f1bc35187a3c924bface884e0 Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Wed, 2 Aug 2023 23:47:46 +0300 Subject: pinctrl: at91-pio4: drop useless check in atmel_conf_pin_config_dbg_show() In atmel_conf_pin_config_dbg_show(), checking atmel_pioctrl->pins[pin_id] against being NULL doesn't make any sense as it gets derefenced first and the driver's probe() method immediately returns -ENOMEM when devm_kzalloc() returns NULL for any atmel_pioctrl->pins[] element anyway, thus failing to register the device... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov Link: https://lore.kernel.org/r/4ab2f59f-45c1-76a2-94da-3331e8ec4e35@omp.ru Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91-pio4.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 5d360ba3abc2..383309e533c3 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -939,10 +939,9 @@ static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, if (!atmel_pioctrl->pins[pin_id]->device) return; - if (atmel_pioctrl->pins[pin_id]) - seq_printf(s, " (%s, ioset %u) ", - atmel_pioctrl->pins[pin_id]->device, - atmel_pioctrl->pins[pin_id]->ioset); + seq_printf(s, " (%s, ioset %u) ", + atmel_pioctrl->pins[pin_id]->device, + atmel_pioctrl->pins[pin_id]->ioset); conf = atmel_pin_config_read(pctldev, pin_id); if (conf & ATMEL_PIO_PUEN_MASK) -- cgit From fc8a2041bee341e1fc07df9685cd0be4ffc80a91 Mon Sep 17 00:00:00 2001 From: Ruan Jinjie Date: Thu, 3 Aug 2023 17:43:04 +0800 Subject: pinctrl: stmfx: Do not check for 0 return after calling platform_get_irq() Since commit ce753ad1549c ("platform: finally disallow IRQ0 in platform_get_irq() and its ilk"), there is no possible for platform_get_irq() to return 0. Use the return value from platform_get_irq(). Signed-off-by: Ruan Jinjie Link: https://lore.kernel.org/r/20230803094304.733371-1-ruanjinjie@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-stmfx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index ab23d7ac3107..0974bbf57b54 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -659,8 +659,8 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq <= 0) - return -ENXIO; + if (irq < 0) + return irq; mutex_init(&pctl->lock); -- cgit From 32c170ff15b044579b1f8b8cdabf543406dde9da Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 20 Jun 2023 12:43:49 +0200 Subject: pinctrl: stm32: set default gpio line names using pin names Add stm32_pctrl_get_desc_pin_from_gpio function to find a stm32 pin descriptor which is matching with a gpio. Most of the time pin number is equal to pin index in array. So the first part of the function is useful to speed up. And during gpio bank register, we set default gpio names with pin names. Signed-off-by: Valentin Caron Acked-by: Alexandre TORGUE Link: https://lore.kernel.org/r/20230620104349.834687-1-valentin.caron@foss.st.com Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index cbdb28358965..a73385a431de 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -1274,6 +1274,28 @@ static const struct pinconf_ops stm32_pconf_ops = { .pin_config_dbg_show = stm32_pconf_dbg_show, }; +static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl, + struct stm32_gpio_bank *bank, + unsigned int offset) +{ + unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset; + struct stm32_desc_pin *pin_desc; + int i; + + /* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */ + pin_desc = pctl->pins + stm32_pin_nb; + if (pin_desc->pin.number == stm32_pin_nb) + return pin_desc; + + /* Otherwise, loop all array to find the pin with the right number */ + for (i = 0; i < pctl->npins; i++) { + pin_desc = pctl->pins + i; + if (pin_desc->pin.number == stm32_pin_nb) + return pin_desc; + } + return NULL; +} + static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode) { struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; @@ -1284,6 +1306,8 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode struct resource res; int npins = STM32_GPIO_PINS_PER_BANK; int bank_nr, err, i = 0; + struct stm32_desc_pin *stm32_pin; + char **names; if (!IS_ERR(bank->rstc)) reset_control_deassert(bank->rstc); @@ -1353,6 +1377,17 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode } } + names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL); + for (i = 0; i < npins; i++) { + stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i); + if (stm32_pin && stm32_pin->pin.name) + names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name); + else + names[i] = NULL; + } + + bank->gpio_chip.names = (const char * const *)names; + err = gpiochip_add_data(&bank->gpio_chip, bank); if (err) { dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); -- cgit From 0cec950d3f3435ae39c8a1a4b1423f4ffbf9ec7a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 8 Aug 2023 15:52:08 +0530 Subject: pinctrl: single: Add compatible for ti,am654-padconf Use the "ti,am654-padconf" compatible to enable the use of wake-up enable and event bits on K3 SOCs that support the daisychain feature Signed-off-by: Tony Lindgren Signed-off-by: Dhruva Gole Link: https://lore.kernel.org/r/20230808102207.130177-3-d-gole@ti.com [Alphabetized the compatible list] Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index f056923ecc98..461a7c02d4a3 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1954,6 +1954,12 @@ static const struct pcs_soc_data pinctrl_single_am437x = { .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ }; +static const struct pcs_soc_data pinctrl_single_am654 = { + .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, + .irq_enable_mask = (1 << 29), /* WKUP_EN */ + .irq_status_mask = (1 << 30), /* WKUP_EVT */ +}; + static const struct pcs_soc_data pinctrl_single = { }; @@ -1962,11 +1968,12 @@ static const struct pcs_soc_data pinconf_single = { }; static const struct of_device_id pcs_of_match[] = { + { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, + { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 }, + { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, - { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, - { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, { .compatible = "pinctrl-single", .data = &pinctrl_single }, { .compatible = "pinconf-single", .data = &pinconf_single }, { }, -- cgit From d2606a6365bde17ee7b1efda9443d6b2e15f6d5a Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 8 Aug 2023 11:07:32 -0700 Subject: pinctrl: iproc-gpio: Silence probe deferral messages We can have gpiochip_add_data() return -EPROBE_DEFER which will make us produce the "unable to add GPIO chip" message which is confusing. Use dev_err_probe() to silence probe deferral messages. Signed-off-by: Florian Fainelli Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230808180733.2081353-2-florian.fainelli@broadcom.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index dcec671661e2..bc7bb9876e57 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -891,10 +891,8 @@ static int iproc_gpio_probe(struct platform_device *pdev) } ret = gpiochip_add_data(gc, chip); - if (ret < 0) { - dev_err(dev, "unable to add GPIO chip\n"); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "unable to add GPIO chip\n"); if (!no_pinconf) { ret = iproc_gpio_register_pinconf(chip); -- cgit From c9b2572f488c3ed3974a0ff6885bb059b1751c86 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 8 Aug 2023 11:07:33 -0700 Subject: pinctrl: nsp-gpio: Silence probe deferral messages We can have gpiochip_add_data() return -EPROBE_DEFER which will make us produce the "unable to add GPIO chip" message which is confusing. Use dev_err_probe() to silence probe deferral messages. Signed-off-by: Florian Fainelli Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230808180733.2081353-3-florian.fainelli@broadcom.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-nsp-gpio.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index e8a5ecd7fb3b..84af6aae36d1 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -685,10 +685,8 @@ static int nsp_gpio_probe(struct platform_device *pdev) } ret = devm_gpiochip_add_data(dev, gc, chip); - if (ret < 0) { - dev_err(dev, "unable to add GPIO chip\n"); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "unable to add GPIO chip\n"); ret = nsp_gpio_register_pinconf(chip); if (ret) { -- cgit From e693b6a896871c7114ae700181ebe55137f2d136 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 14 Aug 2023 10:16:37 +0200 Subject: pinctrl: pinctrl-oxnas: remove obsolete pinctrl driver Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 pinctrl & gpio. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Acked-by: Andy Shevchenko Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-1-04a0c5cdda52@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 11 - drivers/pinctrl/Makefile | 1 - drivers/pinctrl/pinctrl-oxnas.c | 1291 --------------------------------------- 3 files changed, 1303 deletions(-) delete mode 100644 drivers/pinctrl/pinctrl-oxnas.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 57d57af1f624..7dfb7190580e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -355,17 +355,6 @@ config PINCTRL_OCELOT If conpiled as a module, the module name will be pinctrl-ocelot. -config PINCTRL_OXNAS - bool - depends on OF - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GPIOLIB - select OF_GPIO - select GPIOLIB_IRQCHIP - select MFD_SYSCON - config PINCTRL_PALMAS tristate "Pinctrl driver for the PALMAS Series MFD devices" depends on OF && MFD_PALMAS diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 482b391b5deb..dd6cda270294 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o obj-$(CONFIG_PINCTRL_MLXBF3) += pinctrl-mlxbf3.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o -obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c deleted file mode 100644 index 2b2f36994323..000000000000 --- a/drivers/pinctrl/pinctrl-oxnas.c +++ /dev/null @@ -1,1291 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Oxford Semiconductor OXNAS SoC Family pinctrl driver - * - * Copyright (C) 2016 Neil Armstrong - * - * Based on pinctrl-pic32.c - * Joshua Henderson, - * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-utils.h" - -#define PINS_PER_BANK 32 - -#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) - -/* OX810 Regmap Offsets */ -#define PINMUX_810_PRIMARY_SEL0 0x0c -#define PINMUX_810_SECONDARY_SEL0 0x14 -#define PINMUX_810_TERTIARY_SEL0 0x8c -#define PINMUX_810_PRIMARY_SEL1 0x10 -#define PINMUX_810_SECONDARY_SEL1 0x18 -#define PINMUX_810_TERTIARY_SEL1 0x90 -#define PINMUX_810_PULLUP_CTRL0 0xac -#define PINMUX_810_PULLUP_CTRL1 0xb0 - -/* OX820 Regmap Offsets */ -#define PINMUX_820_BANK_OFFSET 0x100000 -#define PINMUX_820_SECONDARY_SEL 0x14 -#define PINMUX_820_TERTIARY_SEL 0x8c -#define PINMUX_820_QUATERNARY_SEL 0x94 -#define PINMUX_820_DEBUG_SEL 0x9c -#define PINMUX_820_ALTERNATIVE_SEL 0xa4 -#define PINMUX_820_PULLUP_CTRL 0xac - -/* GPIO Registers */ -#define INPUT_VALUE 0x00 -#define OUTPUT_EN 0x04 -#define IRQ_PENDING 0x0c -#define OUTPUT_SET 0x14 -#define OUTPUT_CLEAR 0x18 -#define OUTPUT_EN_SET 0x1c -#define OUTPUT_EN_CLEAR 0x20 -#define RE_IRQ_ENABLE 0x28 -#define FE_IRQ_ENABLE 0x2c - -struct oxnas_function { - const char *name; - const char * const *groups; - unsigned int ngroups; -}; - -struct oxnas_pin_group { - const char *name; - unsigned int pin; - unsigned int bank; - struct oxnas_desc_function *functions; -}; - -struct oxnas_desc_function { - const char *name; - unsigned int fct; -}; - -struct oxnas_gpio_bank { - void __iomem *reg_base; - struct gpio_chip gpio_chip; - struct irq_chip irq_chip; - unsigned int id; -}; - -struct oxnas_pinctrl { - struct regmap *regmap; - struct device *dev; - struct pinctrl_dev *pctldev; - const struct oxnas_function *functions; - unsigned int nfunctions; - const struct oxnas_pin_group *groups; - unsigned int ngroups; - struct oxnas_gpio_bank *gpio_banks; - unsigned int nbanks; -}; - -struct oxnas_pinctrl_data { - struct pinctrl_desc *desc; - struct oxnas_pinctrl *pctl; -}; - -static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = { - PINCTRL_PIN(0, "gpio0"), - PINCTRL_PIN(1, "gpio1"), - PINCTRL_PIN(2, "gpio2"), - PINCTRL_PIN(3, "gpio3"), - PINCTRL_PIN(4, "gpio4"), - PINCTRL_PIN(5, "gpio5"), - PINCTRL_PIN(6, "gpio6"), - PINCTRL_PIN(7, "gpio7"), - PINCTRL_PIN(8, "gpio8"), - PINCTRL_PIN(9, "gpio9"), - PINCTRL_PIN(10, "gpio10"), - PINCTRL_PIN(11, "gpio11"), - PINCTRL_PIN(12, "gpio12"), - PINCTRL_PIN(13, "gpio13"), - PINCTRL_PIN(14, "gpio14"), - PINCTRL_PIN(15, "gpio15"), - PINCTRL_PIN(16, "gpio16"), - PINCTRL_PIN(17, "gpio17"), - PINCTRL_PIN(18, "gpio18"), - PINCTRL_PIN(19, "gpio19"), - PINCTRL_PIN(20, "gpio20"), - PINCTRL_PIN(21, "gpio21"), - PINCTRL_PIN(22, "gpio22"), - PINCTRL_PIN(23, "gpio23"), - PINCTRL_PIN(24, "gpio24"), - PINCTRL_PIN(25, "gpio25"), - PINCTRL_PIN(26, "gpio26"), - PINCTRL_PIN(27, "gpio27"), - PINCTRL_PIN(28, "gpio28"), - PINCTRL_PIN(29, "gpio29"), - PINCTRL_PIN(30, "gpio30"), - PINCTRL_PIN(31, "gpio31"), - PINCTRL_PIN(32, "gpio32"), - PINCTRL_PIN(33, "gpio33"), - PINCTRL_PIN(34, "gpio34"), -}; - -static const struct pinctrl_pin_desc oxnas_ox820_pins[] = { - PINCTRL_PIN(0, "gpio0"), - PINCTRL_PIN(1, "gpio1"), - PINCTRL_PIN(2, "gpio2"), - PINCTRL_PIN(3, "gpio3"), - PINCTRL_PIN(4, "gpio4"), - PINCTRL_PIN(5, "gpio5"), - PINCTRL_PIN(6, "gpio6"), - PINCTRL_PIN(7, "gpio7"), - PINCTRL_PIN(8, "gpio8"), - PINCTRL_PIN(9, "gpio9"), - PINCTRL_PIN(10, "gpio10"), - PINCTRL_PIN(11, "gpio11"), - PINCTRL_PIN(12, "gpio12"), - PINCTRL_PIN(13, "gpio13"), - PINCTRL_PIN(14, "gpio14"), - PINCTRL_PIN(15, "gpio15"), - PINCTRL_PIN(16, "gpio16"), - PINCTRL_PIN(17, "gpio17"), - PINCTRL_PIN(18, "gpio18"), - PINCTRL_PIN(19, "gpio19"), - PINCTRL_PIN(20, "gpio20"), - PINCTRL_PIN(21, "gpio21"), - PINCTRL_PIN(22, "gpio22"), - PINCTRL_PIN(23, "gpio23"), - PINCTRL_PIN(24, "gpio24"), - PINCTRL_PIN(25, "gpio25"), - PINCTRL_PIN(26, "gpio26"), - PINCTRL_PIN(27, "gpio27"), - PINCTRL_PIN(28, "gpio28"), - PINCTRL_PIN(29, "gpio29"), - PINCTRL_PIN(30, "gpio30"), - PINCTRL_PIN(31, "gpio31"), - PINCTRL_PIN(32, "gpio32"), - PINCTRL_PIN(33, "gpio33"), - PINCTRL_PIN(34, "gpio34"), - PINCTRL_PIN(35, "gpio35"), - PINCTRL_PIN(36, "gpio36"), - PINCTRL_PIN(37, "gpio37"), - PINCTRL_PIN(38, "gpio38"), - PINCTRL_PIN(39, "gpio39"), - PINCTRL_PIN(40, "gpio40"), - PINCTRL_PIN(41, "gpio41"), - PINCTRL_PIN(42, "gpio42"), - PINCTRL_PIN(43, "gpio43"), - PINCTRL_PIN(44, "gpio44"), - PINCTRL_PIN(45, "gpio45"), - PINCTRL_PIN(46, "gpio46"), - PINCTRL_PIN(47, "gpio47"), - PINCTRL_PIN(48, "gpio48"), - PINCTRL_PIN(49, "gpio49"), -}; - -static const char * const oxnas_ox810se_fct0_group[] = { - "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24", "gpio25", "gpio26", "gpio27", - "gpio28", "gpio29", "gpio30", "gpio31", - "gpio32", "gpio33", "gpio34" -}; - -static const char * const oxnas_ox810se_fct3_group[] = { - "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", - "gpio20", - "gpio22", "gpio23", "gpio24", "gpio25", - "gpio26", "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32", "gpio33", - "gpio34" -}; - -static const char * const oxnas_ox820_fct0_group[] = { - "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24", "gpio25", "gpio26", "gpio27", - "gpio28", "gpio29", "gpio30", "gpio31", - "gpio32", "gpio33", "gpio34", "gpio35", - "gpio36", "gpio37", "gpio38", "gpio39", - "gpio40", "gpio41", "gpio42", "gpio43", - "gpio44", "gpio45", "gpio46", "gpio47", - "gpio48", "gpio49" -}; - -static const char * const oxnas_ox820_fct1_group[] = { - "gpio3", "gpio4", - "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24" -}; - -static const char * const oxnas_ox820_fct4_group[] = { - "gpio5", "gpio6", "gpio7", "gpio8", - "gpio24", "gpio25", "gpio26", "gpio27", - "gpio40", "gpio41", "gpio42", "gpio43" -}; - -static const char * const oxnas_ox820_fct5_group[] = { - "gpio28", "gpio29", "gpio30", "gpio31" -}; - -#define FUNCTION(_name, _gr) \ - { \ - .name = #_name, \ - .groups = oxnas_##_gr##_group, \ - .ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \ - } - -static const struct oxnas_function oxnas_ox810se_functions[] = { - FUNCTION(gpio, ox810se_fct0), - FUNCTION(fct3, ox810se_fct3), -}; - -static const struct oxnas_function oxnas_ox820_functions[] = { - FUNCTION(gpio, ox820_fct0), - FUNCTION(fct1, ox820_fct1), - FUNCTION(fct4, ox820_fct4), - FUNCTION(fct5, ox820_fct5), -}; - -#define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \ - { \ - .name = #_name, \ - .pin = _pin, \ - .bank = _pin / PINS_PER_BANK, \ - .functions = (struct oxnas_desc_function[]){ \ - __VA_ARGS__, { } }, \ - } - -#define OXNAS_PINCTRL_FUNCTION(_name, _fct) \ - { \ - .name = #_name, \ - .fct = _fct, \ - } - -static const struct oxnas_pin_group oxnas_ox810se_groups[] = { - OXNAS_PINCTRL_GROUP(0, gpio0, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(1, gpio1, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(2, gpio2, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(3, gpio3, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(4, gpio4, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(5, gpio5, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(6, gpio6, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(7, gpio7, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(8, gpio8, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(9, gpio9, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(10, gpio10, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(11, gpio11, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(12, gpio12, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(13, gpio13, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(14, gpio14, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(15, gpio15, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(16, gpio16, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(17, gpio17, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(18, gpio18, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(19, gpio19, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(20, gpio20, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(21, gpio21, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(22, gpio22, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(23, gpio23, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(24, gpio24, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(25, gpio25, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(26, gpio26, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(27, gpio27, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(28, gpio28, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(29, gpio29, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(30, gpio30, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(31, gpio31, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(32, gpio32, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(33, gpio33, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(34, gpio34, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), -}; - -static const struct oxnas_pin_group oxnas_ox820_groups[] = { - OXNAS_PINCTRL_GROUP(0, gpio0, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(1, gpio1, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(2, gpio2, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(3, gpio3, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(4, gpio4, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(5, gpio5, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(6, gpio6, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(7, gpio7, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(8, gpio8, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(9, gpio9, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(10, gpio10, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(11, gpio11, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(12, gpio12, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(13, gpio13, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(14, gpio14, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(15, gpio15, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(16, gpio16, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(17, gpio17, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(18, gpio18, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(19, gpio19, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(20, gpio20, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(21, gpio21, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(22, gpio22, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(23, gpio23, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(24, gpio24, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1), - OXNAS_PINCTRL_FUNCTION(fct4, 5)), - OXNAS_PINCTRL_GROUP(25, gpio25, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(26, gpio26, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(27, gpio27, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(28, gpio28, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(29, gpio29, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(30, gpio30, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(31, gpio31, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(32, gpio32, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(33, gpio33, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(34, gpio34, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(35, gpio35, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(36, gpio36, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(37, gpio37, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(38, gpio38, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(39, gpio39, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(40, gpio40, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(41, gpio41, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(42, gpio42, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(43, gpio43, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(44, gpio44, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(45, gpio45, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(46, gpio46, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(47, gpio47, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(48, gpio48, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(49, gpio49, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), -}; - -static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl, - unsigned int pin) -{ - return &pctl->gpio_banks[pin / PINS_PER_BANK]; -} - -static int oxnas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->ngroups; -} - -static const char *oxnas_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->groups[group].name; -} - -static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int group, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - *pins = &pctl->groups[group].pin; - *num_pins = 1; - - return 0; -} - -static const struct pinctrl_ops oxnas_pinctrl_ops = { - .get_groups_count = oxnas_pinctrl_get_groups_count, - .get_group_name = oxnas_pinctrl_get_group_name, - .get_group_pins = oxnas_pinctrl_get_group_pins, - .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, - .dt_free_map = pinctrl_utils_free_map, -}; - -static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->nfunctions; -} - -static const char * -oxnas_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->functions[func].name; -} - -static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int func, - const char * const **groups, - unsigned int * const num_groups) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pctl->functions[func].groups; - *num_groups = pctl->functions[func].ngroups; - - return 0; -} - -static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned int func, unsigned int group) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - const struct oxnas_pin_group *pg = &pctl->groups[group]; - const struct oxnas_function *pf = &pctl->functions[func]; - const char *fname = pf->name; - struct oxnas_desc_function *functions = pg->functions; - u32 mask = BIT(pg->pin); - - while (functions->name) { - if (!strcmp(functions->name, fname)) { - dev_dbg(pctl->dev, - "setting function %s bank %d pin %d fct %d mask %x\n", - fname, pg->bank, pg->pin, - functions->fct, mask); - - regmap_write_bits(pctl->regmap, - (pg->bank ? - PINMUX_810_PRIMARY_SEL1 : - PINMUX_810_PRIMARY_SEL0), - mask, - (functions->fct == 1 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - (pg->bank ? - PINMUX_810_SECONDARY_SEL1 : - PINMUX_810_SECONDARY_SEL0), - mask, - (functions->fct == 2 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - (pg->bank ? - PINMUX_810_TERTIARY_SEL1 : - PINMUX_810_TERTIARY_SEL0), - mask, - (functions->fct == 3 ? - mask : 0)); - - return 0; - } - - functions++; - } - - dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); - - return -EINVAL; -} - -static int oxnas_ox820_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned int func, unsigned int group) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - const struct oxnas_pin_group *pg = &pctl->groups[group]; - const struct oxnas_function *pf = &pctl->functions[func]; - const char *fname = pf->name; - struct oxnas_desc_function *functions = pg->functions; - unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0); - u32 mask = BIT(pg->pin); - - while (functions->name) { - if (!strcmp(functions->name, fname)) { - dev_dbg(pctl->dev, - "setting function %s bank %d pin %d fct %d mask %x\n", - fname, pg->bank, pg->pin, - functions->fct, mask); - - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_SECONDARY_SEL, - mask, - (functions->fct == 1 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_TERTIARY_SEL, - mask, - (functions->fct == 2 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_QUATERNARY_SEL, - mask, - (functions->fct == 3 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_DEBUG_SEL, - mask, - (functions->fct == 4 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_ALTERNATIVE_SEL, - mask, - (functions->fct == 5 ? - mask : 0)); - - return 0; - } - - functions++; - } - - dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); - - return -EINVAL; -} - -static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); - u32 mask = BIT(offset - bank->gpio_chip.base); - - dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n", - offset, bank->gpio_chip.base, bank->id, mask); - - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_PRIMARY_SEL1 : - PINMUX_810_PRIMARY_SEL0), - mask, 0); - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_SECONDARY_SEL1 : - PINMUX_810_SECONDARY_SEL0), - mask, 0); - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_TERTIARY_SEL1 : - PINMUX_810_TERTIARY_SEL0), - mask, 0); - - return 0; -} - -static int oxnas_ox820_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); - unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); - u32 mask = BIT(offset - bank->gpio_chip.base); - - dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n", - offset, bank->gpio_chip.base, bank->id, mask); - - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_SECONDARY_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_TERTIARY_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_QUATERNARY_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_DEBUG_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_ALTERNATIVE_SEL, - mask, 0); - - return 0; -} - -static int oxnas_gpio_get_direction(struct gpio_chip *chip, - unsigned int offset) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - if (readl_relaxed(bank->reg_base + OUTPUT_EN) & mask) - return GPIO_LINE_DIRECTION_OUT; - - return GPIO_LINE_DIRECTION_IN; -} - -static int oxnas_gpio_direction_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR); - - return 0; -} - -static int oxnas_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0; -} - -static void oxnas_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - if (value) - writel_relaxed(mask, bank->reg_base + OUTPUT_SET); - else - writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR); -} - -static int oxnas_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - oxnas_gpio_set(chip, offset, value); - writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET); - - return 0; -} - -static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset, bool input) -{ - struct gpio_chip *chip = range->gc; - - if (input) - oxnas_gpio_direction_input(chip, offset); - else - oxnas_gpio_direction_output(chip, offset, 0); - - return 0; -} - -static const struct pinmux_ops oxnas_ox810se_pinmux_ops = { - .get_functions_count = oxnas_pinmux_get_functions_count, - .get_function_name = oxnas_pinmux_get_function_name, - .get_function_groups = oxnas_pinmux_get_function_groups, - .set_mux = oxnas_ox810se_pinmux_enable, - .gpio_request_enable = oxnas_ox810se_gpio_request_enable, - .gpio_set_direction = oxnas_gpio_set_direction, -}; - -static const struct pinmux_ops oxnas_ox820_pinmux_ops = { - .get_functions_count = oxnas_pinmux_get_functions_count, - .get_function_name = oxnas_pinmux_get_function_name, - .get_function_groups = oxnas_pinmux_get_function_groups, - .set_mux = oxnas_ox820_pinmux_enable, - .gpio_request_enable = oxnas_ox820_gpio_request_enable, - .gpio_set_direction = oxnas_gpio_set_direction, -}; - -static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int param = pinconf_to_config_param(*config); - u32 mask = BIT(pin - bank->gpio_chip.base); - int ret; - u32 arg; - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - ret = regmap_read(pctl->regmap, - (bank->id ? - PINMUX_810_PULLUP_CTRL1 : - PINMUX_810_PULLUP_CTRL0), - &arg); - if (ret) - return ret; - - arg = !!(arg & mask); - break; - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int oxnas_ox820_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int param = pinconf_to_config_param(*config); - unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); - u32 mask = BIT(pin - bank->gpio_chip.base); - int ret; - u32 arg; - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - ret = regmap_read(pctl->regmap, - bank_offset + PINMUX_820_PULLUP_CTRL, - &arg); - if (ret) - return ret; - - arg = !!(arg & mask); - break; - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned int num_configs) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int param; - unsigned int i; - u32 offset = pin - bank->gpio_chip.base; - u32 mask = BIT(offset); - - dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n", - pin, bank->gpio_chip.base, mask); - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - dev_dbg(pctl->dev, " pullup\n"); - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_PULLUP_CTRL1 : - PINMUX_810_PULLUP_CTRL0), - mask, mask); - break; - default: - dev_err(pctl->dev, "Property %u not supported\n", - param); - return -ENOTSUPP; - } - } - - return 0; -} - -static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned int num_configs) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); - unsigned int param; - unsigned int i; - u32 offset = pin - bank->gpio_chip.base; - u32 mask = BIT(offset); - - dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n", - pin, bank->gpio_chip.base, mask); - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - dev_dbg(pctl->dev, " pullup\n"); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_PULLUP_CTRL, - mask, mask); - break; - default: - dev_err(pctl->dev, "Property %u not supported\n", - param); - return -ENOTSUPP; - } - } - - return 0; -} - -static const struct pinconf_ops oxnas_ox810se_pinconf_ops = { - .pin_config_get = oxnas_ox810se_pinconf_get, - .pin_config_set = oxnas_ox810se_pinconf_set, - .is_generic = true, -}; - -static const struct pinconf_ops oxnas_ox820_pinconf_ops = { - .pin_config_get = oxnas_ox820_pinconf_get, - .pin_config_set = oxnas_ox820_pinconf_set, - .is_generic = true, -}; - -static void oxnas_gpio_irq_ack(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(data->hwirq); - - writel(mask, bank->reg_base + IRQ_PENDING); -} - -static void oxnas_gpio_irq_mask(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - unsigned int type = irqd_get_trigger_type(data); - u32 mask = BIT(data->hwirq); - - if (type & IRQ_TYPE_EDGE_RISING) - writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask, - bank->reg_base + RE_IRQ_ENABLE); - - if (type & IRQ_TYPE_EDGE_FALLING) - writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask, - bank->reg_base + FE_IRQ_ENABLE); -} - -static void oxnas_gpio_irq_unmask(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - unsigned int type = irqd_get_trigger_type(data); - u32 mask = BIT(data->hwirq); - - if (type & IRQ_TYPE_EDGE_RISING) - writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask, - bank->reg_base + RE_IRQ_ENABLE); - - if (type & IRQ_TYPE_EDGE_FALLING) - writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask, - bank->reg_base + FE_IRQ_ENABLE); -} - -static unsigned int oxnas_gpio_irq_startup(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - - oxnas_gpio_direction_input(chip, data->hwirq); - oxnas_gpio_irq_unmask(data); - - return 0; -} - -static int oxnas_gpio_irq_set_type(struct irq_data *data, unsigned int type) -{ - if ((type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) == 0) - return -EINVAL; - - irq_set_handler_locked(data, handle_edge_irq); - - return 0; -} - -static void oxnas_gpio_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct oxnas_gpio_bank *bank = gpiochip_get_data(gc); - struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned long stat; - unsigned int pin; - - chained_irq_enter(chip, desc); - - stat = readl(bank->reg_base + IRQ_PENDING); - - for_each_set_bit(pin, &stat, BITS_PER_LONG) - generic_handle_domain_irq(gc->irq.domain, pin); - - chained_irq_exit(chip, desc); -} - -#define GPIO_BANK(_bank) \ - { \ - .gpio_chip = { \ - .label = "GPIO" #_bank, \ - .request = gpiochip_generic_request, \ - .free = gpiochip_generic_free, \ - .get_direction = oxnas_gpio_get_direction, \ - .direction_input = oxnas_gpio_direction_input, \ - .direction_output = oxnas_gpio_direction_output, \ - .get = oxnas_gpio_get, \ - .set = oxnas_gpio_set, \ - .ngpio = PINS_PER_BANK, \ - .base = GPIO_BANK_START(_bank), \ - .owner = THIS_MODULE, \ - .can_sleep = 0, \ - }, \ - .irq_chip = { \ - .name = "GPIO" #_bank, \ - .irq_startup = oxnas_gpio_irq_startup, \ - .irq_ack = oxnas_gpio_irq_ack, \ - .irq_mask = oxnas_gpio_irq_mask, \ - .irq_unmask = oxnas_gpio_irq_unmask, \ - .irq_set_type = oxnas_gpio_irq_set_type, \ - }, \ - } - -static struct oxnas_gpio_bank oxnas_gpio_banks[] = { - GPIO_BANK(0), - GPIO_BANK(1), -}; - -static struct oxnas_pinctrl ox810se_pinctrl = { - .functions = oxnas_ox810se_functions, - .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions), - .groups = oxnas_ox810se_groups, - .ngroups = ARRAY_SIZE(oxnas_ox810se_groups), - .gpio_banks = oxnas_gpio_banks, - .nbanks = ARRAY_SIZE(oxnas_gpio_banks), -}; - -static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = { - .name = "oxnas-pinctrl", - .pins = oxnas_ox810se_pins, - .npins = ARRAY_SIZE(oxnas_ox810se_pins), - .pctlops = &oxnas_pinctrl_ops, - .pmxops = &oxnas_ox810se_pinmux_ops, - .confops = &oxnas_ox810se_pinconf_ops, - .owner = THIS_MODULE, -}; - -static struct oxnas_pinctrl ox820_pinctrl = { - .functions = oxnas_ox820_functions, - .nfunctions = ARRAY_SIZE(oxnas_ox820_functions), - .groups = oxnas_ox820_groups, - .ngroups = ARRAY_SIZE(oxnas_ox820_groups), - .gpio_banks = oxnas_gpio_banks, - .nbanks = ARRAY_SIZE(oxnas_gpio_banks), -}; - -static struct pinctrl_desc oxnas_ox820_pinctrl_desc = { - .name = "oxnas-pinctrl", - .pins = oxnas_ox820_pins, - .npins = ARRAY_SIZE(oxnas_ox820_pins), - .pctlops = &oxnas_pinctrl_ops, - .pmxops = &oxnas_ox820_pinmux_ops, - .confops = &oxnas_ox820_pinconf_ops, - .owner = THIS_MODULE, -}; - -static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = { - .desc = &oxnas_ox810se_pinctrl_desc, - .pctl = &ox810se_pinctrl, -}; - -static struct oxnas_pinctrl_data oxnas_ox820_pinctrl_data = { - .desc = &oxnas_ox820_pinctrl_desc, - .pctl = &ox820_pinctrl, -}; - -static const struct of_device_id oxnas_pinctrl_of_match[] = { - { .compatible = "oxsemi,ox810se-pinctrl", - .data = &oxnas_ox810se_pinctrl_data - }, - { .compatible = "oxsemi,ox820-pinctrl", - .data = &oxnas_ox820_pinctrl_data, - }, - { }, -}; - -static int oxnas_pinctrl_probe(struct platform_device *pdev) -{ - const struct of_device_id *id; - const struct oxnas_pinctrl_data *data; - struct oxnas_pinctrl *pctl; - - id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node); - if (!id) - return -ENODEV; - - data = id->data; - if (!data || !data->pctl || !data->desc) - return -EINVAL; - - pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); - if (!pctl) - return -ENOMEM; - pctl->dev = &pdev->dev; - dev_set_drvdata(&pdev->dev, pctl); - - pctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "oxsemi,sys-ctrl"); - if (IS_ERR(pctl->regmap)) { - dev_err(&pdev->dev, "failed to get sys ctrl regmap\n"); - return -ENODEV; - } - - pctl->functions = data->pctl->functions; - pctl->nfunctions = data->pctl->nfunctions; - pctl->groups = data->pctl->groups; - pctl->ngroups = data->pctl->ngroups; - pctl->gpio_banks = data->pctl->gpio_banks; - pctl->nbanks = data->pctl->nbanks; - - pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl); - if (IS_ERR(pctl->pctldev)) { - dev_err(&pdev->dev, "Failed to register pinctrl device\n"); - return PTR_ERR(pctl->pctldev); - } - - return 0; -} - -static int oxnas_gpio_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct of_phandle_args pinspec; - struct oxnas_gpio_bank *bank; - unsigned int id, ngpios; - int irq, ret; - struct gpio_irq_chip *girq; - - if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", - 3, 0, &pinspec)) { - dev_err(&pdev->dev, "gpio-ranges property not found\n"); - return -EINVAL; - } - - id = pinspec.args[1] / PINS_PER_BANK; - ngpios = pinspec.args[2]; - - if (id >= ARRAY_SIZE(oxnas_gpio_banks)) { - dev_err(&pdev->dev, "invalid gpio-ranges base arg\n"); - return -EINVAL; - } - - if (ngpios > PINS_PER_BANK) { - dev_err(&pdev->dev, "invalid gpio-ranges count arg\n"); - return -EINVAL; - } - - bank = &oxnas_gpio_banks[id]; - - bank->reg_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(bank->reg_base)) - return PTR_ERR(bank->reg_base); - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - - bank->id = id; - bank->gpio_chip.parent = &pdev->dev; - bank->gpio_chip.ngpio = ngpios; - girq = &bank->gpio_chip.irq; - girq->chip = &bank->irq_chip; - girq->parent_handler = oxnas_gpio_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] = irq; - girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_level_irq; - - ret = gpiochip_add_data(&bank->gpio_chip, bank); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n", - id, ret); - return ret; - } - - return 0; -} - -static struct platform_driver oxnas_pinctrl_driver = { - .driver = { - .name = "oxnas-pinctrl", - .of_match_table = oxnas_pinctrl_of_match, - .suppress_bind_attrs = true, - }, - .probe = oxnas_pinctrl_probe, -}; - -static const struct of_device_id oxnas_gpio_of_match[] = { - { .compatible = "oxsemi,ox810se-gpio", }, - { .compatible = "oxsemi,ox820-gpio", }, - { }, -}; - -static struct platform_driver oxnas_gpio_driver = { - .driver = { - .name = "oxnas-gpio", - .of_match_table = oxnas_gpio_of_match, - .suppress_bind_attrs = true, - }, - .probe = oxnas_gpio_probe, -}; - -static int __init oxnas_gpio_register(void) -{ - return platform_driver_register(&oxnas_gpio_driver); -} -arch_initcall(oxnas_gpio_register); - -static int __init oxnas_pinctrl_register(void) -{ - return platform_driver_register(&oxnas_pinctrl_driver); -} -arch_initcall(oxnas_pinctrl_register); -- cgit From 4cfff5b7af8b9df3f1e55ff774944c2f8c8bb9ba Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Tue, 8 Aug 2023 14:19:01 +0530 Subject: pinctrl: baytrail: consolidate common mask operation Consolidate common mask operation outside of switch cases and limit IO operations to positive cases. Signed-off-by: Raag Jadav Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 34 ++++++++++++++------------------ 1 file changed, 15 insertions(+), 19 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 27aef62fc7c0..02ab5fd7cbd5 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -995,8 +995,8 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); + u32 conf, val, db_pulse, debounce; unsigned long flags; - u32 conf, val, debounce; int i, ret = 0; raw_spin_lock_irqsave(&byt_lock, flags); @@ -1053,8 +1053,6 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, break; case PIN_CONFIG_INPUT_DEBOUNCE: - debounce = readl(db_reg); - if (arg) conf |= BYT_DEBOUNCE_EN; else @@ -1062,32 +1060,25 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, switch (arg) { case 375: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_375US; + db_pulse = BYT_DEBOUNCE_PULSE_375US; break; case 750: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_750US; + db_pulse = BYT_DEBOUNCE_PULSE_750US; break; case 1500: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_1500US; + db_pulse = BYT_DEBOUNCE_PULSE_1500US; break; case 3000: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_3MS; + db_pulse = BYT_DEBOUNCE_PULSE_3MS; break; case 6000: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_6MS; + db_pulse = BYT_DEBOUNCE_PULSE_6MS; break; case 12000: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_12MS; + db_pulse = BYT_DEBOUNCE_PULSE_12MS; break; case 24000: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_24MS; + db_pulse = BYT_DEBOUNCE_PULSE_24MS; break; default: if (arg) @@ -1095,8 +1086,13 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, break; } - if (!ret) - writel(debounce, db_reg); + if (ret) + break; + + debounce = readl(db_reg); + debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse; + writel(debounce, db_reg); + break; default: ret = -ENOTSUPP; -- cgit From 79433559d25516c23bfcd21ad7495c99cbe1d9db Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Mon, 14 Aug 2023 11:10:31 +0530 Subject: pinctrl: tangier: Introduce Intel Tangier driver Intel Tangier implements the common pinctrl functionalities for Merrifield and Moorefield platforms. Signed-off-by: Raag Jadav Link: https://lore.kernel.org/r/20230814054033.12004-2-raag.jadav@intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/Kconfig | 1 + drivers/pinctrl/intel/Kconfig.tng | 17 + drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl-tangier.c | 589 ++++++++++++++++++++++++++++++++ drivers/pinctrl/intel/pinctrl-tangier.h | 92 +++++ 5 files changed, 700 insertions(+) create mode 100644 drivers/pinctrl/intel/Kconfig.tng create mode 100644 drivers/pinctrl/intel/pinctrl-tangier.c create mode 100644 drivers/pinctrl/intel/pinctrl-tangier.h (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index b3ec00624416..f2bdb0726e31 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -187,4 +187,5 @@ config PINCTRL_TIGERLAKE This pinctrl driver provides an interface that allows configuring of Intel Tiger Lake PCH pins and using them as GPIOs. +source "drivers/pinctrl/intel/Kconfig.tng" endmenu diff --git a/drivers/pinctrl/intel/Kconfig.tng b/drivers/pinctrl/intel/Kconfig.tng new file mode 100644 index 000000000000..8d7757913b21 --- /dev/null +++ b/drivers/pinctrl/intel/Kconfig.tng @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Intel Tangier and compatible pin control drivers + +if X86_INTEL_MID || COMPILE_TEST + +config PINCTRL_TANGIER + tristate + select PINMUX + select PINCONF + select GENERIC_PINCONF + help + This is a library driver for Intel Tangier pin controller and to + be selected and used by respective compatible platform drivers. + + If built as a module its name will be pinctrl-tangier. + +endif diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 906dd6c8d837..f6d30f2d973a 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o +obj-$(CONFIG_PINCTRL_TANGIER) += pinctrl-tangier.o obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o obj-$(CONFIG_PINCTRL_MOOREFIELD) += pinctrl-moorefield.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o diff --git a/drivers/pinctrl/intel/pinctrl-tangier.c b/drivers/pinctrl/intel/pinctrl-tangier.c new file mode 100644 index 000000000000..40dd60c9e526 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-tangier.c @@ -0,0 +1,589 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Tangier pinctrl driver + * + * Copyright (C) 2016, 2023 Intel Corporation + * + * Authors: Andy Shevchenko + * Raag Jadav + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "../core.h" +#include "pinctrl-intel.h" +#include "pinctrl-tangier.h" + +#define SLEW_OFFSET 0x000 +#define BUFCFG_OFFSET 0x100 +#define MISC_OFFSET 0x300 + +#define BUFCFG_PINMODE_SHIFT 0 +#define BUFCFG_PINMODE_MASK GENMASK(2, 0) +#define BUFCFG_PINMODE_GPIO 0 +#define BUFCFG_PUPD_VAL_SHIFT 4 +#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4) +#define BUFCFG_PUPD_VAL_2K 0 +#define BUFCFG_PUPD_VAL_20K 1 +#define BUFCFG_PUPD_VAL_50K 2 +#define BUFCFG_PUPD_VAL_910 3 +#define BUFCFG_PU_EN BIT(8) +#define BUFCFG_PD_EN BIT(9) +#define BUFCFG_Px_EN_MASK GENMASK(9, 8) +#define BUFCFG_SLEWSEL BIT(10) +#define BUFCFG_OVINEN BIT(12) +#define BUFCFG_OVINEN_EN BIT(13) +#define BUFCFG_OVINEN_MASK GENMASK(13, 12) +#define BUFCFG_OVOUTEN BIT(14) +#define BUFCFG_OVOUTEN_EN BIT(15) +#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14) +#define BUFCFG_INDATAOV_VAL BIT(16) +#define BUFCFG_INDATAOV_EN BIT(17) +#define BUFCFG_INDATAOV_MASK GENMASK(17, 16) +#define BUFCFG_OUTDATAOV_VAL BIT(18) +#define BUFCFG_OUTDATAOV_EN BIT(19) +#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18) +#define BUFCFG_OD_EN BIT(21) + +#define pin_to_bufno(f, p) ((p) - (f)->pin_base) + +static const struct tng_family *tng_get_family(struct tng_pinctrl *tp, + unsigned int pin) +{ + const struct tng_family *family; + unsigned int i; + + for (i = 0; i < tp->nfamilies; i++) { + family = &tp->families[i]; + if (pin >= family->pin_base && + pin < family->pin_base + family->npins) + return family; + } + + dev_warn(tp->dev, "failed to find family for pin %u\n", pin); + return NULL; +} + +static bool tng_buf_available(struct tng_pinctrl *tp, unsigned int pin) +{ + const struct tng_family *family; + + family = tng_get_family(tp, pin); + if (!family) + return false; + + return !family->protected; +} + +static void __iomem *tng_get_bufcfg(struct tng_pinctrl *tp, unsigned int pin) +{ + const struct tng_family *family; + unsigned int bufno; + + family = tng_get_family(tp, pin); + if (!family) + return NULL; + + bufno = pin_to_bufno(family, pin); + return family->regs + BUFCFG_OFFSET + bufno * 4; +} + +static int tng_read_bufcfg(struct tng_pinctrl *tp, unsigned int pin, u32 *value) +{ + void __iomem *bufcfg; + + if (!tng_buf_available(tp, pin)) + return -EBUSY; + + bufcfg = tng_get_bufcfg(tp, pin); + *value = readl(bufcfg); + + return 0; +} + +static void tng_update_bufcfg(struct tng_pinctrl *tp, unsigned int pin, + u32 bits, u32 mask) +{ + void __iomem *bufcfg; + u32 value; + + bufcfg = tng_get_bufcfg(tp, pin); + + value = readl(bufcfg); + value = (value & ~mask) | (bits & mask); + writel(value, bufcfg); +} + +static int tng_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + return tp->ngroups; +} + +static const char *tng_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + return tp->groups[group].grp.name; +} + +static int tng_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, + const unsigned int **pins, unsigned int *npins) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + *pins = tp->groups[group].grp.pins; + *npins = tp->groups[group].grp.npins; + return 0; +} + +static void tng_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int pin) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + u32 value, mode; + int ret; + + ret = tng_read_bufcfg(tp, pin, &value); + if (ret) { + seq_puts(s, "not available"); + return; + } + + mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; + if (mode == BUFCFG_PINMODE_GPIO) + seq_puts(s, "GPIO "); + else + seq_printf(s, "mode %d ", mode); + + seq_printf(s, "0x%08x", value); +} + +static const struct pinctrl_ops tng_pinctrl_ops = { + .get_groups_count = tng_get_groups_count, + .get_group_name = tng_get_group_name, + .get_group_pins = tng_get_group_pins, + .pin_dbg_show = tng_pin_dbg_show, +}; + +static int tng_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + return tp->nfunctions; +} + +static const char *tng_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + return tp->functions[function].func.name; +} + +static int tng_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const ngroups) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + *groups = tp->functions[function].func.groups; + *ngroups = tp->functions[function].func.ngroups; + return 0; +} + +static int tng_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + const struct intel_pingroup *grp = &tp->groups[group]; + u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT; + u32 mask = BUFCFG_PINMODE_MASK; + unsigned long flags; + unsigned int i; + + /* + * All pins in the groups needs to be accessible and writable + * before we can enable the mux for this group. + */ + for (i = 0; i < grp->grp.npins; i++) { + if (!tng_buf_available(tp, grp->grp.pins[i])) + return -EBUSY; + } + + /* Now enable the mux setting for each pin in the group */ + raw_spin_lock_irqsave(&tp->lock, flags); + for (i = 0; i < grp->grp.npins; i++) + tng_update_bufcfg(tp, grp->grp.pins[i], bits, mask); + raw_spin_unlock_irqrestore(&tp->lock, flags); + + return 0; +} + +static int tng_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT; + u32 mask = BUFCFG_PINMODE_MASK; + unsigned long flags; + + if (!tng_buf_available(tp, pin)) + return -EBUSY; + + raw_spin_lock_irqsave(&tp->lock, flags); + tng_update_bufcfg(tp, pin, bits, mask); + raw_spin_unlock_irqrestore(&tp->lock, flags); + + return 0; +} + +static const struct pinmux_ops tng_pinmux_ops = { + .get_functions_count = tng_get_functions_count, + .get_function_name = tng_get_function_name, + .get_function_groups = tng_get_function_groups, + .set_mux = tng_pinmux_set_mux, + .gpio_request_enable = tng_gpio_request_enable, +}; + +static int tng_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 value, term; + u16 arg = 0; + int ret; + + ret = tng_read_bufcfg(tp, pin, &value); + if (ret) + return -ENOTSUPP; + + term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (value & BUFCFG_Px_EN_MASK) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN) + return -EINVAL; + + switch (term) { + case BUFCFG_PUPD_VAL_910: + arg = 910; + break; + case BUFCFG_PUPD_VAL_2K: + arg = 2000; + break; + case BUFCFG_PUPD_VAL_20K: + arg = 20000; + break; + case BUFCFG_PUPD_VAL_50K: + arg = 50000; + break; + } + + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN) + return -EINVAL; + + switch (term) { + case BUFCFG_PUPD_VAL_910: + arg = 910; + break; + case BUFCFG_PUPD_VAL_2K: + arg = 2000; + break; + case BUFCFG_PUPD_VAL_20K: + arg = 20000; + break; + case BUFCFG_PUPD_VAL_50K: + arg = 50000; + break; + } + + break; + + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (value & BUFCFG_OD_EN) + return -EINVAL; + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!(value & BUFCFG_OD_EN)) + return -EINVAL; + break; + + case PIN_CONFIG_SLEW_RATE: + if (value & BUFCFG_SLEWSEL) + arg = 1; + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int tng_config_set_pin(struct tng_pinctrl *tp, unsigned int pin, + unsigned long config) +{ + unsigned int param = pinconf_to_config_param(config); + unsigned int arg = pinconf_to_config_argument(config); + u32 mask, term, value = 0; + unsigned long flags; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + /* Set default strength value in case none is given */ + if (arg == 1) + arg = 20000; + + switch (arg) { + case 50000: + term = BUFCFG_PUPD_VAL_50K; + break; + case 20000: + term = BUFCFG_PUPD_VAL_20K; + break; + case 2000: + term = BUFCFG_PUPD_VAL_2K; + break; + default: + return -EINVAL; + } + + mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; + value = BUFCFG_PU_EN | (term << BUFCFG_PUPD_VAL_SHIFT); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + /* Set default strength value in case none is given */ + if (arg == 1) + arg = 20000; + + switch (arg) { + case 50000: + term = BUFCFG_PUPD_VAL_50K; + break; + case 20000: + term = BUFCFG_PUPD_VAL_20K; + break; + case 2000: + term = BUFCFG_PUPD_VAL_2K; + break; + default: + return -EINVAL; + } + + mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; + value = BUFCFG_PD_EN | (term << BUFCFG_PUPD_VAL_SHIFT); + break; + + case PIN_CONFIG_DRIVE_PUSH_PULL: + mask = BUFCFG_OD_EN; + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + mask = BUFCFG_OD_EN; + value = BUFCFG_OD_EN; + break; + + case PIN_CONFIG_SLEW_RATE: + mask = BUFCFG_SLEWSEL; + if (arg) + value = BUFCFG_SLEWSEL; + break; + + default: + return -EINVAL; + } + + raw_spin_lock_irqsave(&tp->lock, flags); + tng_update_bufcfg(tp, pin, value, mask); + raw_spin_unlock_irqrestore(&tp->lock, flags); + + return 0; +} + +static int tng_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int nconfigs) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + unsigned int i; + int ret; + + if (!tng_buf_available(tp, pin)) + return -ENOTSUPP; + + for (i = 0; i < nconfigs; i++) { + switch (pinconf_to_config_param(configs[i])) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_DRIVE_PUSH_PULL: + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + case PIN_CONFIG_SLEW_RATE: + ret = tng_config_set_pin(tp, pin, configs[i]); + if (ret) + return ret; + break; + + default: + return -ENOTSUPP; + } + } + + return 0; +} + +static int tng_config_group_get(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *config) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret = tng_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + return tng_config_get(pctldev, pins[0], config); +} + +static int tng_config_group_set(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int npins; + int i, ret; + + ret = tng_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = tng_config_set(pctldev, pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops tng_pinconf_ops = { + .is_generic = true, + .pin_config_get = tng_config_get, + .pin_config_set = tng_config_set, + .pin_config_group_get = tng_config_group_get, + .pin_config_group_set = tng_config_group_set, +}; + +static const struct pinctrl_desc tng_pinctrl_desc = { + .pctlops = &tng_pinctrl_ops, + .pmxops = &tng_pinmux_ops, + .confops = &tng_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int tng_pinctrl_probe(struct platform_device *pdev, + const struct tng_pinctrl *data) +{ + struct device *dev = &pdev->dev; + struct tng_family *families; + struct tng_pinctrl *tp; + size_t families_len; + void __iomem *regs; + unsigned int i; + + tp = devm_kmemdup(dev, data, sizeof(*data), GFP_KERNEL); + if (!tp) + return -ENOMEM; + + tp->dev = dev; + raw_spin_lock_init(&tp->lock); + + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + /* + * Make a copy of the families which we can use to hold pointers + * to the registers. + */ + families_len = size_mul(sizeof(*families), tp->nfamilies); + families = devm_kmemdup(dev, tp->families, families_len, GFP_KERNEL); + if (!families) + return -ENOMEM; + + /* Splice memory resource by chunk per family */ + for (i = 0; i < tp->nfamilies; i++) { + struct tng_family *family = &families[i]; + + family->regs = regs + family->barno * TNG_FAMILY_LEN; + } + + tp->families = families; + tp->pctldesc = tng_pinctrl_desc; + tp->pctldesc.name = dev_name(dev); + tp->pctldesc.pins = tp->pins; + tp->pctldesc.npins = tp->npins; + + tp->pctldev = devm_pinctrl_register(dev, &tp->pctldesc, tp); + if (IS_ERR(tp->pctldev)) + return dev_err_probe(dev, PTR_ERR(tp->pctldev), + "failed to register pinctrl driver\n"); + + return 0; +} + +int devm_tng_pinctrl_probe(struct platform_device *pdev) +{ + const struct tng_pinctrl *data; + + data = device_get_match_data(&pdev->dev); + if (!data) + return -ENODATA; + + return tng_pinctrl_probe(pdev, data); +} +EXPORT_SYMBOL_NS_GPL(devm_tng_pinctrl_probe, PINCTRL_TANGIER); + +MODULE_AUTHOR("Andy Shevchenko "); +MODULE_AUTHOR("Raag Jadav "); +MODULE_DESCRIPTION("Intel Tangier pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/intel/pinctrl-tangier.h b/drivers/pinctrl/intel/pinctrl-tangier.h new file mode 100644 index 000000000000..955cc967c0bc --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-tangier.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel Tangier pinctrl functions + * + * Copyright (C) 2016, 2023 Intel Corporation + * + * Authors: Andy Shevchenko + * Raag Jadav + */ + +#ifndef PINCTRL_TANGIER_H +#define PINCTRL_TANGIER_H + +#include +#include + +#include + +#include "pinctrl-intel.h" + +struct device; +struct platform_device; + +#define TNG_FAMILY_NR 64 +#define TNG_FAMILY_LEN 0x400 + +/** + * struct tng_family - Tangier pin family description + * @barno: MMIO BAR number where registers for this family reside + * @pin_base: Starting pin of pins in this family + * @npins: Number of pins in this family + * @protected: True if family is protected by access + * @regs: Family specific common registers + */ +struct tng_family { + unsigned int barno; + unsigned int pin_base; + size_t npins; + bool protected; + void __iomem *regs; +}; + +#define TNG_FAMILY(b, s, e) \ + { \ + .barno = (b), \ + .pin_base = (s), \ + .npins = (e) - (s) + 1, \ + } + +#define TNG_FAMILY_PROTECTED(b, s, e) \ + { \ + .barno = (b), \ + .pin_base = (s), \ + .npins = (e) - (s) + 1, \ + .protected = true, \ + } + +/** + * struct tng_pinctrl - Tangier pinctrl private structure + * @dev: Pointer to the device structure + * @lock: Lock to serialize register access + * @pctldesc: Pin controller description + * @pctldev: Pointer to the pin controller device + * @families: Array of families this pinctrl handles + * @nfamilies: Number of families in the array + * @functions: Array of functions + * @nfunctions: Number of functions in the array + * @groups: Array of pin groups + * @ngroups: Number of groups in the array + * @pins: Array of pins this pinctrl controls + * @npins: Number of pins in the array + */ +struct tng_pinctrl { + struct device *dev; + raw_spinlock_t lock; + struct pinctrl_desc pctldesc; + struct pinctrl_dev *pctldev; + + /* Pin controller configuration */ + const struct tng_family *families; + size_t nfamilies; + const struct intel_function *functions; + size_t nfunctions; + const struct intel_pingroup *groups; + size_t ngroups; + const struct pinctrl_pin_desc *pins; + size_t npins; +}; + +int devm_tng_pinctrl_probe(struct platform_device *pdev); + +#endif /* PINCTRL_TANGIER_H */ -- cgit From 4e1edcc7a92ced481641ed21be91b5c2e5223e41 Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Mon, 14 Aug 2023 11:10:32 +0530 Subject: pinctrl: merrifield: Adapt to Intel Tangier driver Make use of Intel Tangier as a library driver for Merrifield. Signed-off-by: Raag Jadav Link: https://lore.kernel.org/r/20230814054033.12004-3-raag.jadav@intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/Kconfig | 11 - drivers/pinctrl/intel/Kconfig.tng | 8 + drivers/pinctrl/intel/pinctrl-merrifield.c | 677 ++--------------------------- 3 files changed, 41 insertions(+), 655 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index f2bdb0726e31..4042d6cbafcb 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -36,17 +36,6 @@ config PINCTRL_LYNXPOINT provides an interface that allows configuring of PCH pins and using them as GPIOs. -config PINCTRL_MERRIFIELD - tristate "Intel Merrifield pinctrl driver" - depends on X86_INTEL_MID - select PINMUX - select PINCONF - select GENERIC_PINCONF - help - Merrifield Family-Level Interface Shim (FLIS) driver provides an - interface that allows configuring of SoC pins and using them as - GPIOs. - config PINCTRL_MOOREFIELD tristate "Intel Moorefield pinctrl driver" depends on X86_INTEL_MID diff --git a/drivers/pinctrl/intel/Kconfig.tng b/drivers/pinctrl/intel/Kconfig.tng index 8d7757913b21..8a6d315e34d7 100644 --- a/drivers/pinctrl/intel/Kconfig.tng +++ b/drivers/pinctrl/intel/Kconfig.tng @@ -14,4 +14,12 @@ config PINCTRL_TANGIER If built as a module its name will be pinctrl-tangier. +config PINCTRL_MERRIFIELD + tristate "Intel Merrifield pinctrl driver" + select PINCTRL_TANGIER + help + Intel Merrifield Family-Level Interface Shim (FLIS) driver provides + an interface that allows configuring of SoC pins and using them as + GPIOs. + endif diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index fb6de38b1c50..d809680a09c9 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -6,85 +6,17 @@ * Author: Andy Shevchenko */ -#include -#include -#include -#include +#include +#include #include +#include #include -#include +#include -#include -#include #include -#include #include "pinctrl-intel.h" - -#define MRFLD_FAMILY_NR 64 -#define MRFLD_FAMILY_LEN 0x400 - -#define SLEW_OFFSET 0x000 -#define BUFCFG_OFFSET 0x100 -#define MISC_OFFSET 0x300 - -#define BUFCFG_PINMODE_SHIFT 0 -#define BUFCFG_PINMODE_MASK GENMASK(2, 0) -#define BUFCFG_PINMODE_GPIO 0 -#define BUFCFG_PUPD_VAL_SHIFT 4 -#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4) -#define BUFCFG_PUPD_VAL_2K 0 -#define BUFCFG_PUPD_VAL_20K 1 -#define BUFCFG_PUPD_VAL_50K 2 -#define BUFCFG_PUPD_VAL_910 3 -#define BUFCFG_PU_EN BIT(8) -#define BUFCFG_PD_EN BIT(9) -#define BUFCFG_Px_EN_MASK GENMASK(9, 8) -#define BUFCFG_SLEWSEL BIT(10) -#define BUFCFG_OVINEN BIT(12) -#define BUFCFG_OVINEN_EN BIT(13) -#define BUFCFG_OVINEN_MASK GENMASK(13, 12) -#define BUFCFG_OVOUTEN BIT(14) -#define BUFCFG_OVOUTEN_EN BIT(15) -#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14) -#define BUFCFG_INDATAOV_VAL BIT(16) -#define BUFCFG_INDATAOV_EN BIT(17) -#define BUFCFG_INDATAOV_MASK GENMASK(17, 16) -#define BUFCFG_OUTDATAOV_VAL BIT(18) -#define BUFCFG_OUTDATAOV_EN BIT(19) -#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18) -#define BUFCFG_OD_EN BIT(21) - -/** - * struct mrfld_family - Intel pin family description - * @barno: MMIO BAR number where registers for this family reside - * @pin_base: Starting pin of pins in this family - * @npins: Number of pins in this family - * @protected: True if family is protected by access - * @regs: family specific common registers - */ -struct mrfld_family { - unsigned int barno; - unsigned int pin_base; - size_t npins; - bool protected; - void __iomem *regs; -}; - -#define MRFLD_FAMILY(b, s, e) \ - { \ - .barno = (b), \ - .pin_base = (s), \ - .npins = (e) - (s) + 1, \ - } - -#define MRFLD_FAMILY_PROTECTED(b, s, e) \ - { \ - .barno = (b), \ - .pin_base = (s), \ - .npins = (e) - (s) + 1, \ - .protected = true, \ - } +#include "pinctrl-tangier.h" static const struct pinctrl_pin_desc mrfld_pins[] = { /* Family 0: OCP2SSC (0 pins) */ @@ -389,587 +321,43 @@ static const struct intel_function mrfld_functions[] = { FUNCTION("pwm3", mrfld_pwm3_groups), }; -static const struct mrfld_family mrfld_families[] = { - MRFLD_FAMILY(1, 0, 12), - MRFLD_FAMILY(2, 13, 36), - MRFLD_FAMILY(3, 37, 56), - MRFLD_FAMILY(4, 57, 64), - MRFLD_FAMILY(5, 65, 78), - MRFLD_FAMILY(6, 79, 100), - MRFLD_FAMILY_PROTECTED(7, 101, 114), - MRFLD_FAMILY(8, 115, 126), - MRFLD_FAMILY(9, 127, 145), - MRFLD_FAMILY(10, 146, 157), - MRFLD_FAMILY(11, 158, 179), - MRFLD_FAMILY_PROTECTED(12, 180, 194), - MRFLD_FAMILY(13, 195, 214), - MRFLD_FAMILY(14, 215, 227), - MRFLD_FAMILY(15, 228, 232), +static const struct tng_family mrfld_families[] = { + TNG_FAMILY(1, 0, 12), + TNG_FAMILY(2, 13, 36), + TNG_FAMILY(3, 37, 56), + TNG_FAMILY(4, 57, 64), + TNG_FAMILY(5, 65, 78), + TNG_FAMILY(6, 79, 100), + TNG_FAMILY_PROTECTED(7, 101, 114), + TNG_FAMILY(8, 115, 126), + TNG_FAMILY(9, 127, 145), + TNG_FAMILY(10, 146, 157), + TNG_FAMILY(11, 158, 179), + TNG_FAMILY_PROTECTED(12, 180, 194), + TNG_FAMILY(13, 195, 214), + TNG_FAMILY(14, 215, 227), + TNG_FAMILY(15, 228, 232), }; -/** - * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure - * @dev: Pointer to the device structure - * @lock: Lock to serialize register access - * @pctldesc: Pin controller description - * @pctldev: Pointer to the pin controller device - * @families: Array of families this pinctrl handles - * @nfamilies: Number of families in the array - * @functions: Array of functions - * @nfunctions: Number of functions in the array - * @groups: Array of pin groups - * @ngroups: Number of groups in the array - * @pins: Array of pins this pinctrl controls - * @npins: Number of pins in the array - */ -struct mrfld_pinctrl { - struct device *dev; - raw_spinlock_t lock; - struct pinctrl_desc pctldesc; - struct pinctrl_dev *pctldev; - - /* Pin controller configuration */ - const struct mrfld_family *families; - size_t nfamilies; - const struct intel_function *functions; - size_t nfunctions; - const struct intel_pingroup *groups; - size_t ngroups; - const struct pinctrl_pin_desc *pins; - size_t npins; -}; - -#define pin_to_bufno(f, p) ((p) - (f)->pin_base) - -static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp, - unsigned int pin) -{ - const struct mrfld_family *family; - unsigned int i; - - for (i = 0; i < mp->nfamilies; i++) { - family = &mp->families[i]; - if (pin >= family->pin_base && - pin < family->pin_base + family->npins) - return family; - } - - dev_warn(mp->dev, "failed to find family for pin %u\n", pin); - return NULL; -} - -static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin) -{ - const struct mrfld_family *family; - - family = mrfld_get_family(mp, pin); - if (!family) - return false; - - return !family->protected; -} - -static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin) -{ - const struct mrfld_family *family; - unsigned int bufno; - - family = mrfld_get_family(mp, pin); - if (!family) - return NULL; - - bufno = pin_to_bufno(family, pin); - return family->regs + BUFCFG_OFFSET + bufno * 4; -} - -static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value) -{ - void __iomem *bufcfg; - - if (!mrfld_buf_available(mp, pin)) - return -EBUSY; - - bufcfg = mrfld_get_bufcfg(mp, pin); - *value = readl(bufcfg); - - return 0; -} - -static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, - u32 bits, u32 mask) -{ - void __iomem *bufcfg; - u32 value; - - bufcfg = mrfld_get_bufcfg(mp, pin); - value = readl(bufcfg); - - value &= ~mask; - value |= bits & mask; - - writel(value, bufcfg); -} - -static int mrfld_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->ngroups; -} - -static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->groups[group].grp.name; -} - -static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, - const unsigned int **pins, unsigned int *npins) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - *pins = mp->groups[group].grp.pins; - *npins = mp->groups[group].grp.npins; - return 0; -} - -static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned int pin) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - u32 value, mode; - int ret; - - ret = mrfld_read_bufcfg(mp, pin, &value); - if (ret) { - seq_puts(s, "not available"); - return; - } - - mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; - if (mode == BUFCFG_PINMODE_GPIO) - seq_puts(s, "GPIO "); - else - seq_printf(s, "mode %d ", mode); - - seq_printf(s, "0x%08x", value); -} - -static const struct pinctrl_ops mrfld_pinctrl_ops = { - .get_groups_count = mrfld_get_groups_count, - .get_group_name = mrfld_get_group_name, - .get_group_pins = mrfld_get_group_pins, - .pin_dbg_show = mrfld_pin_dbg_show, +static const struct tng_pinctrl mrfld_soc_data = { + .pins = mrfld_pins, + .npins = ARRAY_SIZE(mrfld_pins), + .groups = mrfld_groups, + .ngroups = ARRAY_SIZE(mrfld_groups), + .families = mrfld_families, + .nfamilies = ARRAY_SIZE(mrfld_families), + .functions = mrfld_functions, + .nfunctions = ARRAY_SIZE(mrfld_functions), }; -static int mrfld_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->nfunctions; -} - -static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev, - unsigned int function) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->functions[function].func.name; -} - -static int mrfld_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char * const **groups, - unsigned int * const ngroups) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - *groups = mp->functions[function].func.groups; - *ngroups = mp->functions[function].func.ngroups; - return 0; -} - -static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev, - unsigned int function, - unsigned int group) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - const struct intel_pingroup *grp = &mp->groups[group]; - u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT; - u32 mask = BUFCFG_PINMODE_MASK; - unsigned long flags; - unsigned int i; - - /* - * All pins in the groups needs to be accessible and writable - * before we can enable the mux for this group. - */ - for (i = 0; i < grp->grp.npins; i++) { - if (!mrfld_buf_available(mp, grp->grp.pins[i])) - return -EBUSY; - } - - /* Now enable the mux setting for each pin in the group */ - raw_spin_lock_irqsave(&mp->lock, flags); - for (i = 0; i < grp->grp.npins; i++) - mrfld_update_bufcfg(mp, grp->grp.pins[i], bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT; - u32 mask = BUFCFG_PINMODE_MASK; - unsigned long flags; - - if (!mrfld_buf_available(mp, pin)) - return -EBUSY; - - raw_spin_lock_irqsave(&mp->lock, flags); - mrfld_update_bufcfg(mp, pin, bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static const struct pinmux_ops mrfld_pinmux_ops = { - .get_functions_count = mrfld_get_functions_count, - .get_function_name = mrfld_get_function_name, - .get_function_groups = mrfld_get_function_groups, - .set_mux = mrfld_pinmux_set_mux, - .gpio_request_enable = mrfld_gpio_request_enable, -}; - -static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *config) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - u32 value, term; - u16 arg = 0; - int ret; - - ret = mrfld_read_bufcfg(mp, pin, &value); - if (ret) - return -ENOTSUPP; - - term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - if (value & BUFCFG_Px_EN_MASK) - return -EINVAL; - break; - - case PIN_CONFIG_BIAS_PULL_UP: - if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN) - return -EINVAL; - - switch (term) { - case BUFCFG_PUPD_VAL_910: - arg = 910; - break; - case BUFCFG_PUPD_VAL_2K: - arg = 2000; - break; - case BUFCFG_PUPD_VAL_20K: - arg = 20000; - break; - case BUFCFG_PUPD_VAL_50K: - arg = 50000; - break; - } - - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN) - return -EINVAL; - - switch (term) { - case BUFCFG_PUPD_VAL_910: - arg = 910; - break; - case BUFCFG_PUPD_VAL_2K: - arg = 2000; - break; - case BUFCFG_PUPD_VAL_20K: - arg = 20000; - break; - case BUFCFG_PUPD_VAL_50K: - arg = 50000; - break; - } - - break; - - case PIN_CONFIG_DRIVE_PUSH_PULL: - if (value & BUFCFG_OD_EN) - return -EINVAL; - break; - - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - if (!(value & BUFCFG_OD_EN)) - return -EINVAL; - break; - - case PIN_CONFIG_SLEW_RATE: - if (!(value & BUFCFG_SLEWSEL)) - arg = 0; - else - arg = 1; - break; - - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - return 0; -} - -static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin, - unsigned long config) -{ - unsigned int param = pinconf_to_config_param(config); - unsigned int arg = pinconf_to_config_argument(config); - u32 bits = 0, mask = 0; - unsigned long flags; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - break; - - case PIN_CONFIG_BIAS_PULL_UP: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - bits |= BUFCFG_PU_EN; - - /* Set default strength value in case none is given */ - if (arg == 1) - arg = 20000; - - switch (arg) { - case 50000: - bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 20000: - bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 2000: - bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; - break; - default: - return -EINVAL; - } - - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - bits |= BUFCFG_PD_EN; - - /* Set default strength value in case none is given */ - if (arg == 1) - arg = 20000; - - switch (arg) { - case 50000: - bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 20000: - bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 2000: - bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; - break; - default: - return -EINVAL; - } - - break; - - case PIN_CONFIG_DRIVE_PUSH_PULL: - mask |= BUFCFG_OD_EN; - bits &= ~BUFCFG_OD_EN; - break; - - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - mask |= BUFCFG_OD_EN; - bits |= BUFCFG_OD_EN; - break; - - case PIN_CONFIG_SLEW_RATE: - mask |= BUFCFG_SLEWSEL; - if (arg) - bits |= BUFCFG_SLEWSEL; - break; - } - - raw_spin_lock_irqsave(&mp->lock, flags); - mrfld_update_bufcfg(mp, pin, bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned int nconfigs) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - unsigned int i; - int ret; - - if (!mrfld_buf_available(mp, pin)) - return -ENOTSUPP; - - for (i = 0; i < nconfigs; i++) { - switch (pinconf_to_config_param(configs[i])) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_DRIVE_PUSH_PULL: - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - case PIN_CONFIG_SLEW_RATE: - ret = mrfld_config_set_pin(mp, pin, configs[i]); - if (ret) - return ret; - break; - - default: - return -ENOTSUPP; - } - } - - return 0; -} - -static int mrfld_config_group_get(struct pinctrl_dev *pctldev, - unsigned int group, unsigned long *config) -{ - const unsigned int *pins; - unsigned int npins; - int ret; - - ret = mrfld_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - - ret = mrfld_config_get(pctldev, pins[0], config); - if (ret) - return ret; - - return 0; -} - -static int mrfld_config_group_set(struct pinctrl_dev *pctldev, - unsigned int group, unsigned long *configs, - unsigned int num_configs) -{ - const unsigned int *pins; - unsigned int npins; - int i, ret; - - ret = mrfld_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - - for (i = 0; i < npins; i++) { - ret = mrfld_config_set(pctldev, pins[i], configs, num_configs); - if (ret) - return ret; - } - - return 0; -} - -static const struct pinconf_ops mrfld_pinconf_ops = { - .is_generic = true, - .pin_config_get = mrfld_config_get, - .pin_config_set = mrfld_config_set, - .pin_config_group_get = mrfld_config_group_get, - .pin_config_group_set = mrfld_config_group_set, -}; - -static const struct pinctrl_desc mrfld_pinctrl_desc = { - .pctlops = &mrfld_pinctrl_ops, - .pmxops = &mrfld_pinmux_ops, - .confops = &mrfld_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int mrfld_pinctrl_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct mrfld_family *families; - struct mrfld_pinctrl *mp; - void __iomem *regs; - size_t nfamilies; - unsigned int i; - - mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL); - if (!mp) - return -ENOMEM; - - mp->dev = dev; - raw_spin_lock_init(&mp->lock); - - regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); - - /* - * Make a copy of the families which we can use to hold pointers - * to the registers. - */ - nfamilies = ARRAY_SIZE(mrfld_families), - families = devm_kmemdup(dev, mrfld_families, sizeof(mrfld_families), GFP_KERNEL); - if (!families) - return -ENOMEM; - - /* Splice memory resource by chunk per family */ - for (i = 0; i < nfamilies; i++) { - struct mrfld_family *family = &families[i]; - - family->regs = regs + family->barno * MRFLD_FAMILY_LEN; - } - - mp->families = families; - mp->nfamilies = nfamilies; - mp->functions = mrfld_functions; - mp->nfunctions = ARRAY_SIZE(mrfld_functions); - mp->groups = mrfld_groups; - mp->ngroups = ARRAY_SIZE(mrfld_groups); - mp->pctldesc = mrfld_pinctrl_desc; - mp->pctldesc.name = dev_name(dev); - mp->pctldesc.pins = mrfld_pins; - mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins); - - mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp); - if (IS_ERR(mp->pctldev)) { - dev_err(dev, "failed to register pinctrl driver\n"); - return PTR_ERR(mp->pctldev); - } - - platform_set_drvdata(pdev, mp); - return 0; -} - static const struct acpi_device_id mrfld_acpi_table[] = { - { "INTC1002" }, + { "INTC1002", (kernel_ulong_t)&mrfld_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table); static struct platform_driver mrfld_pinctrl_driver = { - .probe = mrfld_pinctrl_probe, + .probe = devm_tng_pinctrl_probe, .driver = { .name = "pinctrl-merrifield", .acpi_match_table = mrfld_acpi_table, @@ -992,3 +380,4 @@ MODULE_AUTHOR("Andy Shevchenko "); MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:pinctrl-merrifield"); +MODULE_IMPORT_NS(PINCTRL_TANGIER); -- cgit From 8574e4d9942b9e3c2f469e20a89cf836a1d9577a Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Mon, 14 Aug 2023 11:10:33 +0530 Subject: pinctrl: moorefield: Adapt to Intel Tangier driver Make use of Intel Tangier as a library driver for Moorefield. Signed-off-by: Raag Jadav Link: https://lore.kernel.org/r/20230814054033.12004-4-raag.jadav@intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/Kconfig | 11 - drivers/pinctrl/intel/Kconfig.tng | 8 + drivers/pinctrl/intel/pinctrl-moorefield.c | 640 ++--------------------------- 3 files changed, 37 insertions(+), 622 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 4042d6cbafcb..eaa45ebfd1c1 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -36,17 +36,6 @@ config PINCTRL_LYNXPOINT provides an interface that allows configuring of PCH pins and using them as GPIOs. -config PINCTRL_MOOREFIELD - tristate "Intel Moorefield pinctrl driver" - depends on X86_INTEL_MID - select PINMUX - select PINCONF - select GENERIC_PINCONF - help - Moorefield Family-Level Interface Shim (FLIS) driver provides an - interface that allows configuring of SoC pins and using them as - GPIOs. - config PINCTRL_INTEL tristate select PINMUX diff --git a/drivers/pinctrl/intel/Kconfig.tng b/drivers/pinctrl/intel/Kconfig.tng index 8a6d315e34d7..6f88a64d260c 100644 --- a/drivers/pinctrl/intel/Kconfig.tng +++ b/drivers/pinctrl/intel/Kconfig.tng @@ -22,4 +22,12 @@ config PINCTRL_MERRIFIELD an interface that allows configuring of SoC pins and using them as GPIOs. +config PINCTRL_MOOREFIELD + tristate "Intel Moorefield pinctrl driver" + select PINCTRL_TANGIER + help + Intel Moorefield Family-Level Interface Shim (FLIS) driver provides + an interface that allows configuring of SoC pins and using them as + GPIOs. + endif diff --git a/drivers/pinctrl/intel/pinctrl-moorefield.c b/drivers/pinctrl/intel/pinctrl-moorefield.c index 2d38d953f360..807a694b818b 100644 --- a/drivers/pinctrl/intel/pinctrl-moorefield.c +++ b/drivers/pinctrl/intel/pinctrl-moorefield.c @@ -6,77 +6,16 @@ * Author: Andy Shevchenko */ -#include -#include -#include -#include +#include +#include #include +#include #include -#include +#include -#include -#include #include -#include - -#include "pinctrl-intel.h" - -#define MOFLD_FAMILY_NR 64 -#define MOFLD_FAMILY_LEN 0x400 - -#define SLEW_OFFSET 0x000 -#define BUFCFG_OFFSET 0x100 -#define MISC_OFFSET 0x300 -#define BUFCFG_PINMODE_SHIFT 0 -#define BUFCFG_PINMODE_MASK GENMASK(2, 0) -#define BUFCFG_PINMODE_GPIO 0 -#define BUFCFG_PUPD_VAL_SHIFT 4 -#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4) -#define BUFCFG_PUPD_VAL_2K 0 -#define BUFCFG_PUPD_VAL_20K 1 -#define BUFCFG_PUPD_VAL_50K 2 -#define BUFCFG_PUPD_VAL_910 3 -#define BUFCFG_PU_EN BIT(8) -#define BUFCFG_PD_EN BIT(9) -#define BUFCFG_Px_EN_MASK GENMASK(9, 8) -#define BUFCFG_SLEWSEL BIT(10) -#define BUFCFG_OVINEN BIT(12) -#define BUFCFG_OVINEN_EN BIT(13) -#define BUFCFG_OVINEN_MASK GENMASK(13, 12) -#define BUFCFG_OVOUTEN BIT(14) -#define BUFCFG_OVOUTEN_EN BIT(15) -#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14) -#define BUFCFG_INDATAOV_VAL BIT(16) -#define BUFCFG_INDATAOV_EN BIT(17) -#define BUFCFG_INDATAOV_MASK GENMASK(17, 16) -#define BUFCFG_OUTDATAOV_VAL BIT(18) -#define BUFCFG_OUTDATAOV_EN BIT(19) -#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18) -#define BUFCFG_OD_EN BIT(21) - -/** - * struct mofld_family - Intel pin family description - * @barno: MMIO BAR number where registers for this family reside - * @pin_base: Starting pin of pins in this family - * @npins: Number of pins in this family - * @protected: True if family is protected by access - * @regs: family specific common registers - */ -struct mofld_family { - unsigned int barno; - unsigned int pin_base; - size_t npins; - bool protected; - void __iomem *regs; -}; - -#define MOFLD_FAMILY(b, s, e) \ - { \ - .barno = (b), \ - .pin_base = (s), \ - .npins = (e) - (s) + 1, \ - } +#include "pinctrl-tangier.h" static const struct pinctrl_pin_desc mofld_pins[] = { /* ULPI (13 pins) */ @@ -347,561 +286,39 @@ static const struct pinctrl_pin_desc mofld_pins[] = { PINCTRL_PIN(250, "JTAG_TRST"), }; -static const struct mofld_family mofld_families[] = { - MOFLD_FAMILY(0, 0, 12), - MOFLD_FAMILY(1, 13, 24), - MOFLD_FAMILY(2, 25, 44), - MOFLD_FAMILY(3, 45, 52), - MOFLD_FAMILY(4, 53, 66), - MOFLD_FAMILY(5, 67, 88), - MOFLD_FAMILY(6, 89, 108), - MOFLD_FAMILY(7, 109, 131), - MOFLD_FAMILY(8, 132, 151), - MOFLD_FAMILY(9, 152, 166), - MOFLD_FAMILY(10, 167, 180), - MOFLD_FAMILY(11, 181, 195), - MOFLD_FAMILY(12, 196, 215), - MOFLD_FAMILY(13, 216, 228), - MOFLD_FAMILY(14, 229, 250), -}; - -/** - * struct mofld_pinctrl - Intel Merrifield pinctrl private structure - * @dev: Pointer to the device structure - * @lock: Lock to serialize register access - * @pctldesc: Pin controller description - * @pctldev: Pointer to the pin controller device - * @families: Array of families this pinctrl handles - * @nfamilies: Number of families in the array - * @functions: Array of functions - * @nfunctions: Number of functions in the array - * @groups: Array of pin groups - * @ngroups: Number of groups in the array - * @pins: Array of pins this pinctrl controls - * @npins: Number of pins in the array - */ -struct mofld_pinctrl { - struct device *dev; - raw_spinlock_t lock; - struct pinctrl_desc pctldesc; - struct pinctrl_dev *pctldev; - - /* Pin controller configuration */ - const struct mofld_family *families; - size_t nfamilies; - const struct intel_function *functions; - size_t nfunctions; - const struct intel_pingroup *groups; - size_t ngroups; - const struct pinctrl_pin_desc *pins; - size_t npins; -}; - -#define pin_to_bufno(f, p) ((p) - (f)->pin_base) - -static const struct mofld_family *mofld_get_family(struct mofld_pinctrl *mp, unsigned int pin) -{ - const struct mofld_family *family; - unsigned int i; - - for (i = 0; i < mp->nfamilies; i++) { - family = &mp->families[i]; - if (pin >= family->pin_base && - pin < family->pin_base + family->npins) - return family; - } - - dev_warn(mp->dev, "failed to find family for pin %u\n", pin); - return NULL; -} - -static bool mofld_buf_available(struct mofld_pinctrl *mp, unsigned int pin) -{ - const struct mofld_family *family; - - family = mofld_get_family(mp, pin); - if (!family) - return false; - - return !family->protected; -} - -static void __iomem *mofld_get_bufcfg(struct mofld_pinctrl *mp, unsigned int pin) -{ - const struct mofld_family *family; - unsigned int bufno; - - family = mofld_get_family(mp, pin); - if (!family) - return NULL; - - bufno = pin_to_bufno(family, pin); - return family->regs + BUFCFG_OFFSET + bufno * 4; -} - -static int mofld_read_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 *value) -{ - void __iomem *bufcfg; - - if (!mofld_buf_available(mp, pin)) - return -EBUSY; - - bufcfg = mofld_get_bufcfg(mp, pin); - *value = readl(bufcfg); - - return 0; -} - -static void mofld_update_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 bits, u32 mask) -{ - void __iomem *bufcfg; - u32 value; - - bufcfg = mofld_get_bufcfg(mp, pin); - value = readl(bufcfg); - - value &= ~mask; - value |= bits & mask; - - writel(value, bufcfg); -} - -static int mofld_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->ngroups; -} - -static const char *mofld_get_group_name(struct pinctrl_dev *pctldev, unsigned int group) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->groups[group].grp.name; -} - -static int mofld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, - const unsigned int **pins, unsigned int *npins) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - *pins = mp->groups[group].grp.pins; - *npins = mp->groups[group].grp.npins; - return 0; -} - -static void mofld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned int pin) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - u32 value, mode; - int ret; - - ret = mofld_read_bufcfg(mp, pin, &value); - if (ret) { - seq_puts(s, "not available"); - return; - } - - mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; - if (mode == BUFCFG_PINMODE_GPIO) - seq_puts(s, "GPIO "); - else - seq_printf(s, "mode %d ", mode); - - seq_printf(s, "0x%08x", value); -} - -static const struct pinctrl_ops mofld_pinctrl_ops = { - .get_groups_count = mofld_get_groups_count, - .get_group_name = mofld_get_group_name, - .get_group_pins = mofld_get_group_pins, - .pin_dbg_show = mofld_pin_dbg_show, -}; - -static int mofld_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->nfunctions; -} - -static const char *mofld_get_function_name(struct pinctrl_dev *pctldev, unsigned int function) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->functions[function].func.name; -} - -static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, - const char * const **groups, unsigned int * const ngroups) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - *groups = mp->functions[function].func.groups; - *ngroups = mp->functions[function].func.ngroups; - return 0; -} - -static int mofld_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, - unsigned int group) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - const struct intel_pingroup *grp = &mp->groups[group]; - u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT; - u32 mask = BUFCFG_PINMODE_MASK; - unsigned long flags; - unsigned int i; - - /* - * All pins in the groups needs to be accessible and writable - * before we can enable the mux for this group. - */ - for (i = 0; i < grp->grp.npins; i++) { - if (!mofld_buf_available(mp, grp->grp.pins[i])) - return -EBUSY; - } - - /* Now enable the mux setting for each pin in the group */ - raw_spin_lock_irqsave(&mp->lock, flags); - for (i = 0; i < grp->grp.npins; i++) - mofld_update_bufcfg(mp, grp->grp.pins[i], bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static int mofld_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT; - u32 mask = BUFCFG_PINMODE_MASK; - unsigned long flags; - - if (!mofld_buf_available(mp, pin)) - return -EBUSY; - - raw_spin_lock_irqsave(&mp->lock, flags); - mofld_update_bufcfg(mp, pin, bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static const struct pinmux_ops mofld_pinmux_ops = { - .get_functions_count = mofld_get_functions_count, - .get_function_name = mofld_get_function_name, - .get_function_groups = mofld_get_function_groups, - .set_mux = mofld_pinmux_set_mux, - .gpio_request_enable = mofld_gpio_request_enable, -}; - -static int mofld_config_get(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *config) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - u32 value, term; - u16 arg = 0; - int ret; - - ret = mofld_read_bufcfg(mp, pin, &value); - if (ret) - return -ENOTSUPP; - - term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - if (value & BUFCFG_Px_EN_MASK) - return -EINVAL; - break; - - case PIN_CONFIG_BIAS_PULL_UP: - if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN) - return -EINVAL; - - switch (term) { - case BUFCFG_PUPD_VAL_910: - arg = 910; - break; - case BUFCFG_PUPD_VAL_2K: - arg = 2000; - break; - case BUFCFG_PUPD_VAL_20K: - arg = 20000; - break; - case BUFCFG_PUPD_VAL_50K: - arg = 50000; - break; - } - - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN) - return -EINVAL; - - switch (term) { - case BUFCFG_PUPD_VAL_910: - arg = 910; - break; - case BUFCFG_PUPD_VAL_2K: - arg = 2000; - break; - case BUFCFG_PUPD_VAL_20K: - arg = 20000; - break; - case BUFCFG_PUPD_VAL_50K: - arg = 50000; - break; - } - - break; - - case PIN_CONFIG_DRIVE_PUSH_PULL: - if (value & BUFCFG_OD_EN) - return -EINVAL; - break; - - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - if (!(value & BUFCFG_OD_EN)) - return -EINVAL; - break; - - case PIN_CONFIG_SLEW_RATE: - if (!(value & BUFCFG_SLEWSEL)) - arg = 0; - else - arg = 1; - break; - - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - return 0; -} - -static int mofld_config_set_pin(struct mofld_pinctrl *mp, unsigned int pin, - unsigned long config) -{ - unsigned int param = pinconf_to_config_param(config); - unsigned int arg = pinconf_to_config_argument(config); - u32 bits = 0, mask = 0; - unsigned long flags; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - break; - - case PIN_CONFIG_BIAS_PULL_UP: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - bits |= BUFCFG_PU_EN; - - switch (arg) { - case 50000: - bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 20000: - bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 2000: - bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; - break; - default: - return -EINVAL; - } - - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - bits |= BUFCFG_PD_EN; - - switch (arg) { - case 50000: - bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 20000: - bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 2000: - bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; - break; - default: - return -EINVAL; - } - - break; - - case PIN_CONFIG_DRIVE_PUSH_PULL: - mask |= BUFCFG_OD_EN; - bits &= ~BUFCFG_OD_EN; - break; - - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - mask |= BUFCFG_OD_EN; - bits |= BUFCFG_OD_EN; - break; - - case PIN_CONFIG_SLEW_RATE: - mask |= BUFCFG_SLEWSEL; - if (arg) - bits |= BUFCFG_SLEWSEL; - break; - } - - raw_spin_lock_irqsave(&mp->lock, flags); - mofld_update_bufcfg(mp, pin, bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static int mofld_config_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned int nconfigs) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - unsigned int i; - int ret; - - if (!mofld_buf_available(mp, pin)) - return -ENOTSUPP; - - for (i = 0; i < nconfigs; i++) { - switch (pinconf_to_config_param(configs[i])) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_DRIVE_PUSH_PULL: - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - case PIN_CONFIG_SLEW_RATE: - ret = mofld_config_set_pin(mp, pin, configs[i]); - if (ret) - return ret; - break; - - default: - return -ENOTSUPP; - } - } - - return 0; -} - -static int mofld_config_group_get(struct pinctrl_dev *pctldev, unsigned int group, - unsigned long *config) -{ - const unsigned int *pins; - unsigned int npins; - int ret; - - ret = mofld_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - - ret = mofld_config_get(pctldev, pins[0], config); - if (ret) - return ret; - - return 0; -} - -static int mofld_config_group_set(struct pinctrl_dev *pctldev, unsigned int group, - unsigned long *configs, unsigned int num_configs) -{ - const unsigned int *pins; - unsigned int npins; - int i, ret; - - ret = mofld_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - - for (i = 0; i < npins; i++) { - ret = mofld_config_set(pctldev, pins[i], configs, num_configs); - if (ret) - return ret; - } - - return 0; -} - -static const struct pinconf_ops mofld_pinconf_ops = { - .is_generic = true, - .pin_config_get = mofld_config_get, - .pin_config_set = mofld_config_set, - .pin_config_group_get = mofld_config_group_get, - .pin_config_group_set = mofld_config_group_set, +static const struct tng_family mofld_families[] = { + TNG_FAMILY(0, 0, 12), + TNG_FAMILY(1, 13, 24), + TNG_FAMILY(2, 25, 44), + TNG_FAMILY(3, 45, 52), + TNG_FAMILY(4, 53, 66), + TNG_FAMILY(5, 67, 88), + TNG_FAMILY(6, 89, 108), + TNG_FAMILY(7, 109, 131), + TNG_FAMILY(8, 132, 151), + TNG_FAMILY(9, 152, 166), + TNG_FAMILY(10, 167, 180), + TNG_FAMILY(11, 181, 195), + TNG_FAMILY(12, 196, 215), + TNG_FAMILY(13, 216, 228), + TNG_FAMILY(14, 229, 250), }; -static const struct pinctrl_desc mofld_pinctrl_desc = { - .pctlops = &mofld_pinctrl_ops, - .pmxops = &mofld_pinmux_ops, - .confops = &mofld_pinconf_ops, - .owner = THIS_MODULE, +static const struct tng_pinctrl mofld_soc_data = { + .pins = mofld_pins, + .npins = ARRAY_SIZE(mofld_pins), + .families = mofld_families, + .nfamilies = ARRAY_SIZE(mofld_families), }; -static int mofld_pinctrl_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct mofld_family *families; - struct mofld_pinctrl *mp; - void __iomem *regs; - size_t nfamilies; - unsigned int i; - - mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL); - if (!mp) - return -ENOMEM; - - mp->dev = dev; - raw_spin_lock_init(&mp->lock); - - regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); - - nfamilies = ARRAY_SIZE(mofld_families), - families = devm_kmemdup(dev, mofld_families, sizeof(mofld_families), GFP_KERNEL); - if (!families) - return -ENOMEM; - - /* Splice memory resource by chunk per family */ - for (i = 0; i < nfamilies; i++) { - struct mofld_family *family = &families[i]; - - family->regs = regs + family->barno * MOFLD_FAMILY_LEN; - } - - mp->families = families; - mp->nfamilies = nfamilies; - mp->pctldesc = mofld_pinctrl_desc; - mp->pctldesc.name = dev_name(dev); - mp->pctldesc.pins = mofld_pins; - mp->pctldesc.npins = ARRAY_SIZE(mofld_pins); - - mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp); - if (IS_ERR(mp->pctldev)) - return PTR_ERR(mp->pctldev); - - platform_set_drvdata(pdev, mp); - return 0; -} - static const struct acpi_device_id mofld_acpi_table[] = { - { "INTC1003" }, + { "INTC1003", (kernel_ulong_t)&mofld_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, mofld_acpi_table); static struct platform_driver mofld_pinctrl_driver = { - .probe = mofld_pinctrl_probe, + .probe = devm_tng_pinctrl_probe, .driver = { .name = "pinctrl-moorefield", .acpi_match_table = mofld_acpi_table, @@ -924,3 +341,4 @@ MODULE_AUTHOR("Andy Shevchenko "); MODULE_DESCRIPTION("Intel Moorefield SoC pinctrl driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:pinctrl-moorefield"); +MODULE_IMPORT_NS(PINCTRL_TANGIER); -- cgit From 25018ace79ed822eb984a3a91a09de37acf80a63 Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Mon, 14 Aug 2023 11:33:08 +0530 Subject: pinctrl: intel: export common pinctrl functions Export common pinctrl functions that are used across Intel specific platform drivers, so that they can be reused. Signed-off-by: Raag Jadav Acked-by: Mika Westerberg Link: https://lore.kernel.org/r/20230814060311.15945-2-raag.jadav@intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 30 ++++++++++++++++-------------- drivers/pinctrl/intel/pinctrl-intel.h | 12 ++++++++++++ 2 files changed, 28 insertions(+), 14 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 64c3e62b4348..4e019c2cb27a 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -107,8 +107,7 @@ struct intel_community_context { #define pin_to_padno(c, p) ((p) - (c)->pin_base) #define padgroup_offset(g, p) ((p) - (g)->base) -static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, - unsigned int pin) +struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin) { struct intel_community *community; int i; @@ -123,6 +122,7 @@ static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); return NULL; } +EXPORT_SYMBOL_NS_GPL(intel_get_community, PINCTRL_INTEL); static const struct intel_padgroup * intel_community_get_padgroup(const struct intel_community *community, @@ -276,23 +276,24 @@ static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); } -static int intel_get_groups_count(struct pinctrl_dev *pctldev) +int intel_get_groups_count(struct pinctrl_dev *pctldev) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->ngroups; } +EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, PINCTRL_INTEL); -static const char *intel_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) +const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->groups[group].grp.name; } +EXPORT_SYMBOL_NS_GPL(intel_get_group_name, PINCTRL_INTEL); -static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, - const unsigned int **pins, unsigned int *npins) +int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, + const unsigned int **pins, unsigned int *npins) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -300,6 +301,7 @@ static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, *npins = pctrl->soc->groups[group].grp.npins; return 0; } +EXPORT_SYMBOL_NS_GPL(intel_get_group_pins, PINCTRL_INTEL); static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) @@ -359,25 +361,24 @@ static const struct pinctrl_ops intel_pinctrl_ops = { .pin_dbg_show = intel_pin_dbg_show, }; -static int intel_get_functions_count(struct pinctrl_dev *pctldev) +int intel_get_functions_count(struct pinctrl_dev *pctldev) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->nfunctions; } +EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, PINCTRL_INTEL); -static const char *intel_get_function_name(struct pinctrl_dev *pctldev, - unsigned int function) +const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->functions[function].func.name; } +EXPORT_SYMBOL_NS_GPL(intel_get_function_name, PINCTRL_INTEL); -static int intel_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char * const **groups, - unsigned int * const ngroups) +int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, + const char * const **groups, unsigned int * const ngroups) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -385,6 +386,7 @@ static int intel_get_function_groups(struct pinctrl_dev *pctldev, *ngroups = pctrl->soc->functions[function].func.ngroups; return 0; } +EXPORT_SYMBOL_NS_GPL(intel_get_function_groups, PINCTRL_INTEL); static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 1faf2ada480a..cee512f97b56 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -266,4 +266,16 @@ const struct dev_pm_ops _name = { \ intel_pinctrl_resume_noirq) \ } +struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin); + +int intel_get_groups_count(struct pinctrl_dev *pctldev); +const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group); +int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, + const unsigned int **pins, unsigned int *npins); + +int intel_get_functions_count(struct pinctrl_dev *pctldev); +const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function); +int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, + const char * const **groups, unsigned int * const ngroups); + #endif /* PINCTRL_INTEL_H */ -- cgit From 4d01688fdff822b0be6684acb266e59e0956daf8 Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Mon, 14 Aug 2023 11:33:09 +0530 Subject: pinctrl: baytrail: reuse common functions from pinctrl-intel Reuse common functions from pinctrl-intel driver. Signed-off-by: Raag Jadav Acked-by: Mika Westerberg Link: https://lore.kernel.org/r/20230814060311.15945-3-raag.jadav@intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 90 ++++---------------------------- 1 file changed, 11 insertions(+), 79 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 27aef62fc7c0..7ce10e11f5fc 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -551,25 +552,10 @@ static const struct intel_pinctrl_soc_data *byt_soc_data[] = { static DEFINE_RAW_SPINLOCK(byt_lock); -static struct intel_community *byt_get_community(struct intel_pinctrl *vg, - unsigned int pin) -{ - struct intel_community *comm; - int i; - - for (i = 0; i < vg->ncommunities; i++) { - comm = vg->communities + i; - if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) - return comm; - } - - return NULL; -} - static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, int reg) { - struct intel_community *comm = byt_get_community(vg, offset); + struct intel_community *comm = intel_get_community(vg, offset); u32 reg_offset; if (!comm) @@ -591,68 +577,12 @@ static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, return comm->pad_regs + reg_offset + reg; } -static int byt_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - return vg->soc->ngroups; -} - -static const char *byt_get_group_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - return vg->soc->groups[selector].grp.name; -} - -static int byt_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int selector, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - *pins = vg->soc->groups[selector].grp.pins; - *num_pins = vg->soc->groups[selector].grp.npins; - - return 0; -} - static const struct pinctrl_ops byt_pinctrl_ops = { - .get_groups_count = byt_get_groups_count, - .get_group_name = byt_get_group_name, - .get_group_pins = byt_get_group_pins, + .get_groups_count = intel_get_groups_count, + .get_group_name = intel_get_group_name, + .get_group_pins = intel_get_group_pins, }; -static int byt_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - return vg->soc->nfunctions; -} - -static const char *byt_get_function_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - return vg->soc->functions[selector].func.name; -} - -static int byt_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int selector, - const char * const **groups, - unsigned int *ngroups) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - *groups = vg->soc->functions[selector].func.groups; - *ngroups = vg->soc->functions[selector].func.ngroups; - - return 0; -} - static void byt_set_group_simple_mux(struct intel_pinctrl *vg, const struct intel_pingroup group, unsigned int func) @@ -851,9 +781,9 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, } static const struct pinmux_ops byt_pinmux_ops = { - .get_functions_count = byt_get_functions_count, - .get_function_name = byt_get_function_name, - .get_function_groups = byt_get_function_groups, + .get_functions_count = intel_get_functions_count, + .get_function_name = intel_get_function_name, + .get_function_groups = intel_get_function_groups, .set_mux = byt_set_mux, .gpio_request_enable = byt_gpio_request_enable, .gpio_disable_free = byt_gpio_disable_free, @@ -1265,7 +1195,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) val = readl(val_reg); raw_spin_unlock_irqrestore(&byt_lock, flags); - comm = byt_get_community(vg, pin); + comm = intel_get_community(vg, pin); if (!comm) { seq_printf(s, "Pin %i: can't retrieve community\n", pin); continue; @@ -1852,3 +1782,5 @@ static int __init byt_gpio_init(void) return platform_driver_register(&byt_gpio_driver); } subsys_initcall(byt_gpio_init); + +MODULE_IMPORT_NS(PINCTRL_INTEL); -- cgit From a2118cebc62cd76a86a3b42ac90cb9613297510c Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Mon, 14 Aug 2023 11:33:10 +0530 Subject: pinctrl: cherryview: reuse common functions from pinctrl-intel Reuse common functions from pinctrl-intel driver. Signed-off-by: Raag Jadav Acked-by: Mika Westerberg Link: https://lore.kernel.org/r/20230814060311.15945-4-raag.jadav@intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 69 ++++-------------------------- 1 file changed, 9 insertions(+), 60 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index eee0f9bc3d32..7bde3316addf 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -617,31 +617,6 @@ static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset) return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK; } -static int chv_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->ngroups; -} - -static const char *chv_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->groups[group].grp.name; -} - -static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, - const unsigned int **pins, unsigned int *npins) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - *pins = pctrl->soc->groups[group].grp.pins; - *npins = pctrl->soc->groups[group].grp.npins; - return 0; -} - static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int offset) { @@ -676,39 +651,12 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, } static const struct pinctrl_ops chv_pinctrl_ops = { - .get_groups_count = chv_get_groups_count, - .get_group_name = chv_get_group_name, - .get_group_pins = chv_get_group_pins, + .get_groups_count = intel_get_groups_count, + .get_group_name = intel_get_group_name, + .get_group_pins = intel_get_group_pins, .pin_dbg_show = chv_pin_dbg_show, }; -static int chv_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->nfunctions; -} - -static const char *chv_get_function_name(struct pinctrl_dev *pctldev, - unsigned int function) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->functions[function].func.name; -} - -static int chv_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char * const **groups, - unsigned int * const ngroups) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pctrl->soc->functions[function].func.groups; - *ngroups = pctrl->soc->functions[function].func.ngroups; - return 0; -} - static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { @@ -884,9 +832,9 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, } static const struct pinmux_ops chv_pinmux_ops = { - .get_functions_count = chv_get_functions_count, - .get_function_name = chv_get_function_name, - .get_function_groups = chv_get_function_groups, + .get_functions_count = intel_get_functions_count, + .get_function_name = intel_get_function_name, + .get_function_groups = intel_get_function_groups, .set_mux = chv_pinmux_set_mux, .gpio_request_enable = chv_gpio_request_enable, .gpio_disable_free = chv_gpio_disable_free, @@ -1118,7 +1066,7 @@ static int chv_config_group_get(struct pinctrl_dev *pctldev, unsigned int npins; int ret; - ret = chv_get_group_pins(pctldev, group, &pins, &npins); + ret = intel_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; @@ -1137,7 +1085,7 @@ static int chv_config_group_set(struct pinctrl_dev *pctldev, unsigned int npins; int i, ret; - ret = chv_get_group_pins(pctldev, group, &pins, &npins); + ret = intel_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; @@ -1915,3 +1863,4 @@ module_exit(chv_pinctrl_exit); MODULE_AUTHOR("Mika Westerberg "); MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); -- cgit From 976cf4a6ee8b5ba1dccd64ab388823ef1e4a9456 Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Mon, 14 Aug 2023 11:33:11 +0530 Subject: pinctrl: lynxpoint: reuse common functions from pinctrl-intel Reuse common functions from pinctrl-intel driver. While at it, select pinctrl-intel for Intel Lynxpoint driver. Signed-off-by: Raag Jadav Acked-by: Mika Westerberg Link: https://lore.kernel.org/r/20230814060311.15945-5-raag.jadav@intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/Kconfig | 6 +-- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 86 +++---------------------------- 2 files changed, 9 insertions(+), 83 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index b3ec00624416..b42148c828ef 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -26,11 +26,7 @@ config PINCTRL_CHERRYVIEW config PINCTRL_LYNXPOINT tristate "Intel Lynxpoint pinctrl and GPIO driver" depends on ACPI - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GPIOLIB - select GPIOLIB_IRQCHIP + select PINCTRL_INTEL help Lynxpoint is the PCH of Intel Haswell. This pinctrl driver provides an interface that allows configuring of PCH pins and diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index cdace55aaeac..780c9ab79d85 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -206,21 +206,6 @@ static const struct intel_pinctrl_soc_data lptlp_soc_data = { * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. */ -static struct intel_community *lp_get_community(struct intel_pinctrl *lg, - unsigned int pin) -{ - struct intel_community *comm; - int i; - - for (i = 0; i < lg->ncommunities; i++) { - comm = &lg->communities[i]; - if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) - return comm; - } - - return NULL; -} - static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, int reg) { @@ -228,7 +213,7 @@ static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, struct intel_community *comm; int reg_offset; - comm = lp_get_community(lg, offset); + comm = intel_get_community(lg, offset); if (!comm) return NULL; @@ -272,34 +257,6 @@ static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) return false; } -static int lp_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - return lg->soc->ngroups; -} - -static const char *lp_get_group_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - return lg->soc->groups[selector].grp.name; -} - -static int lp_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int selector, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - *pins = lg->soc->groups[selector].grp.pins; - *num_pins = lg->soc->groups[selector].grp.npins; - - return 0; -} - static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) { @@ -323,40 +280,12 @@ static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, } static const struct pinctrl_ops lptlp_pinctrl_ops = { - .get_groups_count = lp_get_groups_count, - .get_group_name = lp_get_group_name, - .get_group_pins = lp_get_group_pins, + .get_groups_count = intel_get_groups_count, + .get_group_name = intel_get_group_name, + .get_group_pins = intel_get_group_pins, .pin_dbg_show = lp_pin_dbg_show, }; -static int lp_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - return lg->soc->nfunctions; -} - -static const char *lp_get_function_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - return lg->soc->functions[selector].func.name; -} - -static int lp_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int selector, - const char * const **groups, - unsigned int *ngroups) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - *groups = lg->soc->functions[selector].func.groups; - *ngroups = lg->soc->functions[selector].func.ngroups; - - return 0; -} - static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { @@ -481,9 +410,9 @@ static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, } static const struct pinmux_ops lptlp_pinmux_ops = { - .get_functions_count = lp_get_functions_count, - .get_function_name = lp_get_function_name, - .get_function_groups = lp_get_function_groups, + .get_functions_count = intel_get_functions_count, + .get_function_name = intel_get_function_name, + .get_function_groups = intel_get_function_groups, .set_mux = lp_pinmux_set_mux, .gpio_request_enable = lp_gpio_request_enable, .gpio_disable_free = lp_gpio_disable_free, @@ -987,3 +916,4 @@ MODULE_AUTHOR("Andy Shevchenko (Intel)"); MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:lp_gpio"); +MODULE_IMPORT_NS(PINCTRL_INTEL); -- cgit From 34393c367872a6ef5aaf36172d7238668db23ae4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 15 Aug 2023 19:18:58 +0300 Subject: pinctrl: intel: Switch to use exported namespace We already have a few symbols exported in the namespace. Let's do the same for others (except PM for now). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-alderlake.c | 1 + drivers/pinctrl/intel/pinctrl-broxton.c | 1 + drivers/pinctrl/intel/pinctrl-cannonlake.c | 2 +- drivers/pinctrl/intel/pinctrl-cedarfork.c | 1 + drivers/pinctrl/intel/pinctrl-denverton.c | 1 + drivers/pinctrl/intel/pinctrl-elkhartlake.c | 2 +- drivers/pinctrl/intel/pinctrl-emmitsburg.c | 2 +- drivers/pinctrl/intel/pinctrl-geminilake.c | 1 + drivers/pinctrl/intel/pinctrl-icelake.c | 2 +- drivers/pinctrl/intel/pinctrl-intel.c | 6 +++--- drivers/pinctrl/intel/pinctrl-jasperlake.c | 1 + drivers/pinctrl/intel/pinctrl-lakefield.c | 1 + drivers/pinctrl/intel/pinctrl-lewisburg.c | 2 +- drivers/pinctrl/intel/pinctrl-meteorlake.c | 1 + drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 1 + drivers/pinctrl/intel/pinctrl-tigerlake.c | 2 +- 16 files changed, 18 insertions(+), 9 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c index 55bbfd647ba4..4a37dc273d63 100644 --- a/drivers/pinctrl/intel/pinctrl-alderlake.c +++ b/drivers/pinctrl/intel/pinctrl-alderlake.c @@ -748,3 +748,4 @@ module_platform_driver(adl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko "); MODULE_DESCRIPTION("Intel Alder Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c index 77e921b2178d..4d5ddb297909 100644 --- a/drivers/pinctrl/intel/pinctrl-broxton.c +++ b/drivers/pinctrl/intel/pinctrl-broxton.c @@ -1028,3 +1028,4 @@ MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:apollolake-pinctrl"); MODULE_ALIAS("platform:broxton-pinctrl"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index 88142ec57b25..95976abfb785 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -834,9 +834,9 @@ static struct platform_driver cnl_pinctrl_driver = { .pm = &cnl_pinctrl_pm_ops, }, }; - module_platform_driver(cnl_pinctrl_driver); MODULE_AUTHOR("Mika Westerberg "); MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-cedarfork.c b/drivers/pinctrl/intel/pinctrl-cedarfork.c index 2ab52b1fbc59..a20465eb2dc6 100644 --- a/drivers/pinctrl/intel/pinctrl-cedarfork.c +++ b/drivers/pinctrl/intel/pinctrl-cedarfork.c @@ -351,3 +351,4 @@ module_exit(cdf_pinctrl_exit); MODULE_AUTHOR("Mika Westerberg "); MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-denverton.c b/drivers/pinctrl/intel/pinctrl-denverton.c index c1a9db091c6e..0c4694cfa594 100644 --- a/drivers/pinctrl/intel/pinctrl-denverton.c +++ b/drivers/pinctrl/intel/pinctrl-denverton.c @@ -281,3 +281,4 @@ module_exit(dnv_pinctrl_exit); MODULE_AUTHOR("Mika Westerberg "); MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-elkhartlake.c b/drivers/pinctrl/intel/pinctrl-elkhartlake.c index 64b1997df0be..81581ab85316 100644 --- a/drivers/pinctrl/intel/pinctrl-elkhartlake.c +++ b/drivers/pinctrl/intel/pinctrl-elkhartlake.c @@ -495,9 +495,9 @@ static struct platform_driver ehl_pinctrl_driver = { .pm = &ehl_pinctrl_pm_ops, }, }; - module_platform_driver(ehl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko "); MODULE_DESCRIPTION("Intel Elkhart Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-emmitsburg.c b/drivers/pinctrl/intel/pinctrl-emmitsburg.c index cc8f0baabc91..099ec8351d5f 100644 --- a/drivers/pinctrl/intel/pinctrl-emmitsburg.c +++ b/drivers/pinctrl/intel/pinctrl-emmitsburg.c @@ -368,9 +368,9 @@ static struct platform_driver ebg_pinctrl_driver = { .pm = &ebg_pinctrl_pm_ops, }, }; - module_platform_driver(ebg_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko "); MODULE_DESCRIPTION("Intel Emmitsburg PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-geminilake.c b/drivers/pinctrl/intel/pinctrl-geminilake.c index 918cc9f261cf..9effa06b61e9 100644 --- a/drivers/pinctrl/intel/pinctrl-geminilake.c +++ b/drivers/pinctrl/intel/pinctrl-geminilake.c @@ -473,3 +473,4 @@ module_exit(glk_pinctrl_exit); MODULE_AUTHOR("Mika Westerberg "); MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 1c64b4a1c491..300e1538c8d0 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -685,10 +685,10 @@ static struct platform_driver icl_pinctrl_driver = { .pm = &icl_pinctrl_pm_ops, }, }; - module_platform_driver(icl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko "); MODULE_AUTHOR("Mika Westerberg "); MODULE_DESCRIPTION("Intel Ice Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 4e019c2cb27a..3be04ab760d3 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1668,7 +1668,7 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev) return intel_pinctrl_probe(pdev, data); } -EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); +EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, PINCTRL_INTEL); int intel_pinctrl_probe_by_uid(struct platform_device *pdev) { @@ -1680,7 +1680,7 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev) return intel_pinctrl_probe(pdev, data); } -EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); +EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, PINCTRL_INTEL); const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) { @@ -1712,7 +1712,7 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_ return data ?: ERR_PTR(-ENODATA); } -EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); +EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL); #ifdef CONFIG_PM_SLEEP static bool __intel_gpio_is_direct_irq(u32 value) diff --git a/drivers/pinctrl/intel/pinctrl-jasperlake.c b/drivers/pinctrl/intel/pinctrl-jasperlake.c index 086ab7fe08dd..50f137deed9c 100644 --- a/drivers/pinctrl/intel/pinctrl-jasperlake.c +++ b/drivers/pinctrl/intel/pinctrl-jasperlake.c @@ -341,3 +341,4 @@ module_platform_driver(jsl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko "); MODULE_DESCRIPTION("Intel Jasper Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-lakefield.c b/drivers/pinctrl/intel/pinctrl-lakefield.c index 8dac2d6012b1..0b94e11b78ac 100644 --- a/drivers/pinctrl/intel/pinctrl-lakefield.c +++ b/drivers/pinctrl/intel/pinctrl-lakefield.c @@ -362,3 +362,4 @@ module_platform_driver(lkf_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko "); MODULE_DESCRIPTION("Intel Lakefield PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-lewisburg.c b/drivers/pinctrl/intel/pinctrl-lewisburg.c index 7aac1bbde2e9..aa725a5d62b9 100644 --- a/drivers/pinctrl/intel/pinctrl-lewisburg.c +++ b/drivers/pinctrl/intel/pinctrl-lewisburg.c @@ -317,9 +317,9 @@ static struct platform_driver lbg_pinctrl_driver = { .pm = &lbg_pinctrl_pm_ops, }, }; - module_platform_driver(lbg_pinctrl_driver); MODULE_AUTHOR("Mika Westerberg "); MODULE_DESCRIPTION("Intel Lewisburg pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-meteorlake.c b/drivers/pinctrl/intel/pinctrl-meteorlake.c index 9a11f729bec8..7ced2b402dce 100644 --- a/drivers/pinctrl/intel/pinctrl-meteorlake.c +++ b/drivers/pinctrl/intel/pinctrl-meteorlake.c @@ -604,3 +604,4 @@ module_platform_driver(mtl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko "); MODULE_DESCRIPTION("Intel Meteor Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index f91e27feb7c3..b7a40ab0bca8 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -606,3 +606,4 @@ MODULE_AUTHOR("Mathias Nyman "); MODULE_AUTHOR("Mika Westerberg "); MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 6e3a651d1241..4768a69a9258 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -753,10 +753,10 @@ static struct platform_driver tgl_pinctrl_driver = { .pm = &tgl_pinctrl_pm_ops, }, }; - module_platform_driver(tgl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko "); MODULE_AUTHOR("Mika Westerberg "); MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); -- cgit From df660f66ba5350c4cb8c6aa04e6eed909c929a46 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 17 Jul 2023 20:28:13 +0300 Subject: pinctrl: baytrail: Make use of pm_ptr() Cleaning up the driver to use pm_ptr() and *_PM_OPS() macros that make it simpler and allows the compiler to remove those functions if built without CONFIG_PM and CONFIG_PM_SLEEP support. Reviewed-by: Jonathan Cameron Reviewed-by: Paul Cercueil Link: https://lore.kernel.org/r/20230717172821.62827-3-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 85f1aea2ca89..faa8b7ff5bcf 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1659,7 +1659,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM_SLEEP static int byt_gpio_suspend(struct device *dev) { struct intel_pinctrl *vg = dev_get_drvdata(dev); @@ -1743,9 +1742,7 @@ static int byt_gpio_resume(struct device *dev) raw_spin_unlock_irqrestore(&byt_lock, flags); return 0; } -#endif -#ifdef CONFIG_PM static int byt_gpio_runtime_suspend(struct device *dev) { return 0; @@ -1755,19 +1752,17 @@ static int byt_gpio_runtime_resume(struct device *dev) { return 0; } -#endif static const struct dev_pm_ops byt_gpio_pm_ops = { - SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) - SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, - NULL) + LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) + RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, NULL) }; static struct platform_driver byt_gpio_driver = { .probe = byt_pinctrl_probe, .driver = { .name = "byt_gpio", - .pm = &byt_gpio_pm_ops, + .pm = pm_ptr(&byt_gpio_pm_ops), .acpi_match_table = byt_gpio_acpi_match, .suppress_bind_attrs = true, }, -- cgit From 1956149dec0e8e8f533380337bc2d4f4ceb16b9a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 17 Jul 2023 20:28:16 +0300 Subject: pinctrl: lynxpoint: Make use of pm_ptr() Cleaning up the driver to use pm_ptr() and *_PM_OPS() macros that make it simpler and allows the compiler to remove those functions if built without CONFIG_PM and CONFIG_PM_SLEEP support. The lp_gpio_resume() is also assigned to .thaw and .restore members. This is not a problem as the function it enables input pins that had been disabled by firmware and repetion of that doesn't change the pin configuration, i.e. it is idempotent. Reviewed-by: Paul Cercueil Link: https://lore.kernel.org/r/20230717172821.62827-6-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 780c9ab79d85..c3732a9f0658 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -877,9 +877,8 @@ static int lp_gpio_resume(struct device *dev) } static const struct dev_pm_ops lp_gpio_pm_ops = { - .runtime_suspend = lp_gpio_runtime_suspend, - .runtime_resume = lp_gpio_runtime_resume, - .resume = lp_gpio_resume, + SYSTEM_SLEEP_PM_OPS(NULL, lp_gpio_resume) + RUNTIME_PM_OPS(lp_gpio_runtime_suspend, lp_gpio_runtime_resume, NULL) }; static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { @@ -894,7 +893,7 @@ static struct platform_driver lp_gpio_driver = { .remove = lp_gpio_remove, .driver = { .name = "lp_gpio", - .pm = &lp_gpio_pm_ops, + .pm = pm_ptr(&lp_gpio_pm_ops), .acpi_match_table = lynxpoint_gpio_acpi_match, }, }; -- cgit From 8f6f16fe1553ce63edfb98a39ef9d4754a0c39bf Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 18 Aug 2023 04:02:35 +0100 Subject: pinctrl: mediatek: fix pull_type data for MT7981 MediaTek has released pull_type data for MT7981 in their SDK. Use it and set functions to configure pin bias. Fixes: 6c83b2d94fcc ("pinctrl: add mt7981 pinctrl driver") Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/7bcc8ead25dbfabc7f5a85d066224a926fbb4941.1692327317.git.daniel@makrotopia.org Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 44 +++++++++---------------------- 1 file changed, 13 insertions(+), 31 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 18abc5780011..0fd2c0c451f9 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -457,37 +457,15 @@ static const unsigned int mt7981_pull_type[] = { MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ - MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ - MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ - MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ - MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ - MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ - MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ - MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ - MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ - MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ - MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ - MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ - MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ - MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ - MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ - MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ - MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ - MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ - MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ - MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ - MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ - MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ - MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ - MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ - MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ - MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ - MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ - MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ - MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ - MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ - MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ - MTK_PULL_PU_PD_TYPE,/*100*/ + MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ + MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ + MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ + MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/ + MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/ + MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/ + MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/ + MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ + MTK_PULL_PU_PD_TYPE,/*56*/ }; static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { @@ -1014,6 +992,10 @@ static struct mtk_pin_soc mt7981_data = { .ies_present = false, .base_names = mt7981_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, .pull_type = mt7981_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, -- cgit From 0d8387fba9f151220e48dc3dcdc2335539708f13 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 18 Aug 2023 04:03:26 +0100 Subject: pinctrl: mediatek: assign functions to configure pin bias on MT7986 Assign bias_disable_get/set and bias_get/set functions to allow configuring pin bias on MT7986. Fixes: 2c58d8dc9cd0 ("pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC") Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/47f72372354312a839b9337e09476aadcc206e8b.1692327317.git.daniel@makrotopia.org Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index aa0ccd67f4f4..acaac9b38aa8 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -922,6 +922,10 @@ static struct mtk_pin_soc mt7986a_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, @@ -944,6 +948,10 @@ static struct mtk_pin_soc mt7986b_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, -- cgit From e5f32bf0974f817790717839e4a53b16eedcb5a9 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 17 Jul 2023 20:28:14 +0300 Subject: pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/20230717172821.62827-4-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 7bde3316addf..55a42dbf97b6 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1741,7 +1741,6 @@ static int chv_pinctrl_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM_SLEEP static int chv_pinctrl_suspend_noirq(struct device *dev) { struct intel_pinctrl *pctrl = dev_get_drvdata(dev); @@ -1825,12 +1824,9 @@ static int chv_pinctrl_resume_noirq(struct device *dev) return 0; } -#endif -static const struct dev_pm_ops chv_pinctrl_pm_ops = { - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, - chv_pinctrl_resume_noirq) -}; +static DEFINE_NOIRQ_DEV_PM_OPS(chv_pinctrl_pm_ops, + chv_pinctrl_suspend_noirq, chv_pinctrl_resume_noirq); static const struct acpi_device_id chv_pinctrl_acpi_match[] = { { "INT33FF", (kernel_ulong_t)chv_soc_data }, @@ -1843,7 +1839,7 @@ static struct platform_driver chv_pinctrl_driver = { .remove = chv_pinctrl_remove, .driver = { .name = "cherryview-pinctrl", - .pm = &chv_pinctrl_pm_ops, + .pm = pm_sleep_ptr(&chv_pinctrl_pm_ops), .acpi_match_table = chv_pinctrl_acpi_match, }, }; -- cgit From f0d8d0eea5ed9854b4e4a8973ddced1a8e660a77 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 17 Jul 2023 20:28:17 +0300 Subject: pinctrl: at91: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. With that switch pm_ptr() to pm_sleep_ptr() as the above mentioned callbacks are only used for system sleep. The use of the pm_sleep_ptr() macro allows the compiler to always see the dev_pm_ops structure and related functions, while still allowing the unused code to be removed, without the need for the __maybe_unused markings. Reviewed-by: Claudiu Beznea Reviewed-by: Paul Cercueil Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/20230717172821.62827-7-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-at91.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 39956d821ad7..608f55c5ba5f 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1657,7 +1657,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state) return 0; } -static int __maybe_unused at91_gpio_suspend(struct device *dev) +static int at91_gpio_suspend(struct device *dev) { struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev); void __iomem *pio = at91_chip->regbase; @@ -1675,7 +1675,7 @@ static int __maybe_unused at91_gpio_suspend(struct device *dev) return 0; } -static int __maybe_unused at91_gpio_resume(struct device *dev) +static int at91_gpio_resume(struct device *dev) { struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev); void __iomem *pio = at91_chip->regbase; @@ -1903,15 +1903,13 @@ static int at91_gpio_probe(struct platform_device *pdev) return 0; } -static const struct dev_pm_ops at91_gpio_pm_ops = { - NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume) -}; +static DEFINE_NOIRQ_DEV_PM_OPS(at91_gpio_pm_ops, at91_gpio_suspend, at91_gpio_resume); static struct platform_driver at91_gpio_driver = { .driver = { .name = "gpio-at91", .of_match_table = at91_gpio_of_match, - .pm = pm_ptr(&at91_gpio_pm_ops), + .pm = pm_sleep_ptr(&at91_gpio_pm_ops), }, .probe = at91_gpio_probe, }; -- cgit From c9008b71bed6a86079e0d5f9b0eca27f9eb1bbcd Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 17 Jul 2023 20:28:19 +0300 Subject: pinctrl: mvebu: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. Reviewed-by: Jonathan Cameron Reviewed-by: Paul Cercueil Link: https://lore.kernel.org/r/20230717172821.62827-9-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 67c6751a6f06..46351c00ee73 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -1013,7 +1013,6 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, return 0; } -#if defined(CONFIG_PM) static int armada_3700_pinctrl_suspend(struct device *dev) { struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); @@ -1107,15 +1106,8 @@ static int armada_3700_pinctrl_resume(struct device *dev) * Since pinctrl is an infrastructure module, its resume should be issued prior * to other IO drivers. */ -static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = { - .suspend_noirq = armada_3700_pinctrl_suspend, - .resume_noirq = armada_3700_pinctrl_resume, -}; - -#define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops) -#else -#define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL -#endif /* CONFIG_PM */ +static DEFINE_NOIRQ_DEV_PM_OPS(armada_3700_pinctrl_pm_ops, + armada_3700_pinctrl_suspend, armada_3700_pinctrl_resume); static const struct of_device_id armada_37xx_pinctrl_of_match[] = { { @@ -1182,7 +1174,7 @@ static struct platform_driver armada_37xx_pinctrl_driver = { .driver = { .name = "armada-37xx-pinctrl", .of_match_table = armada_37xx_pinctrl_of_match, - .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS, + .pm = pm_sleep_ptr(&armada_3700_pinctrl_pm_ops), }, }; -- cgit From 727eb02eb753375e6e8b829a19839ddd1006bfad Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 17 Jul 2023 20:28:20 +0300 Subject: pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. Reviewed-by: Jonathan Cameron Reviewed-by: Geert Uytterhoeven Acked-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230717172821.62827-10-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/renesas/core.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 0c8d081da6a8..34232b016960 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -649,7 +649,7 @@ static const struct of_device_id sh_pfc_of_table[] = { }; #endif -#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) +#if defined(CONFIG_ARM_PSCI_FW) static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) { } @@ -732,15 +732,13 @@ static int sh_pfc_resume_noirq(struct device *dev) sh_pfc_walk_regs(pfc, sh_pfc_restore_reg); return 0; } - -static const struct dev_pm_ops sh_pfc_pm = { - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq) -}; -#define DEV_PM_OPS &sh_pfc_pm #else static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } -#define DEV_PM_OPS NULL -#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ +static int sh_pfc_suspend_noirq(struct device *dev) { return 0; } +static int sh_pfc_resume_noirq(struct device *dev) { return 0; } +#endif /* CONFIG_ARM_PSCI_FW */ + +static DEFINE_NOIRQ_DEV_PM_OPS(sh_pfc_pm, sh_pfc_suspend_noirq, sh_pfc_resume_noirq); #ifdef DEBUG #define SH_PFC_MAX_REGS 300 @@ -1418,7 +1416,7 @@ static struct platform_driver sh_pfc_driver = { .driver = { .name = DRV_NAME, .of_match_table = of_match_ptr(sh_pfc_of_table), - .pm = DEV_PM_OPS, + .pm = pm_sleep_ptr(&sh_pfc_pm), }, }; -- cgit From 83f7586f3b365330765a24eb40f99a1c1a43d38e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 17 Jul 2023 20:28:21 +0300 Subject: pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. With that, make sure the PM ops are used only in CONFIG_PM_SLEEP=y case by wrapping them in pm_sleep_ptr() macro. Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230717172821.62827-11-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko --- drivers/pinctrl/tegra/pinctrl-tegra.c | 5 +---- drivers/pinctrl/tegra/pinctrl-tegra210.c | 2 +- 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 4547cf66d03b..734c71ef005b 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -747,10 +747,7 @@ static int tegra_pinctrl_resume(struct device *dev) return 0; } -const struct dev_pm_ops tegra_pinctrl_pm = { - .suspend_noirq = &tegra_pinctrl_suspend, - .resume_noirq = &tegra_pinctrl_resume -}; +DEFINE_NOIRQ_DEV_PM_OPS(tegra_pinctrl_pm, tegra_pinctrl_suspend, tegra_pinctrl_resume); static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx) { diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c index 9bb29146dfff..bc668b9c2ae0 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c @@ -1570,7 +1570,7 @@ static struct platform_driver tegra210_pinctrl_driver = { .driver = { .name = "tegra210-pinctrl", .of_match_table = tegra210_pinctrl_of_match, - .pm = &tegra_pinctrl_pm, + .pm = pm_sleep_ptr(&tegra_pinctrl_pm), }, .probe = tegra210_pinctrl_probe, }; -- cgit From da41309b618e4dff92bbc109b776f800faa7a60a Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Tue, 22 Aug 2023 13:00:56 +0530 Subject: pinctrl: intel: consolidate ACPI dependency Since all the Intel specific platform drivers depend on ACPI, we can consolidate their config dependency. Signed-off-by: Raag Jadav Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/Kconfig | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index f42a83e29b8b..d66f4f6932d8 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -1,11 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 # Intel pin control drivers menu "Intel pinctrl drivers" - depends on X86 || COMPILE_TEST + depends on ACPI && (X86 || COMPILE_TEST) config PINCTRL_BAYTRAIL bool "Intel Baytrail GPIO pin control" - depends on ACPI select PINCTRL_INTEL help driver for memory mapped GPIO functionality on Intel Baytrail @@ -17,7 +16,6 @@ config PINCTRL_BAYTRAIL config PINCTRL_CHERRYVIEW tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help Cherryview/Braswell pinctrl driver provides an interface that @@ -25,7 +23,6 @@ config PINCTRL_CHERRYVIEW config PINCTRL_LYNXPOINT tristate "Intel Lynxpoint pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help Lynxpoint is the PCH of Intel Haswell. This pinctrl driver @@ -42,7 +39,6 @@ config PINCTRL_INTEL config PINCTRL_ALDERLAKE tristate "Intel Alder Lake pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -50,7 +46,6 @@ config PINCTRL_ALDERLAKE config PINCTRL_BROXTON tristate "Intel Broxton pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help Broxton pinctrl driver provides an interface that allows @@ -58,7 +53,6 @@ config PINCTRL_BROXTON config PINCTRL_CANNONLAKE tristate "Intel Cannon Lake PCH pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -66,7 +60,6 @@ config PINCTRL_CANNONLAKE config PINCTRL_CEDARFORK tristate "Intel Cedar Fork pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -74,7 +67,6 @@ config PINCTRL_CEDARFORK config PINCTRL_DENVERTON tristate "Intel Denverton pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -82,7 +74,6 @@ config PINCTRL_DENVERTON config PINCTRL_ELKHARTLAKE tristate "Intel Elkhart Lake SoC pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -90,7 +81,6 @@ config PINCTRL_ELKHARTLAKE config PINCTRL_EMMITSBURG tristate "Intel Emmitsburg pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -98,7 +88,6 @@ config PINCTRL_EMMITSBURG config PINCTRL_GEMINILAKE tristate "Intel Gemini Lake SoC pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -106,7 +95,6 @@ config PINCTRL_GEMINILAKE config PINCTRL_ICELAKE tristate "Intel Ice Lake PCH pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -114,7 +102,6 @@ config PINCTRL_ICELAKE config PINCTRL_JASPERLAKE tristate "Intel Jasper Lake PCH pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -122,7 +109,6 @@ config PINCTRL_JASPERLAKE config PINCTRL_LAKEFIELD tristate "Intel Lakefield SoC pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -130,7 +116,6 @@ config PINCTRL_LAKEFIELD config PINCTRL_LEWISBURG tristate "Intel Lewisburg pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -138,7 +123,6 @@ config PINCTRL_LEWISBURG config PINCTRL_METEORLAKE tristate "Intel Meteor Lake pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -146,7 +130,6 @@ config PINCTRL_METEORLAKE config PINCTRL_SUNRISEPOINT tristate "Intel Sunrisepoint pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver @@ -155,7 +138,6 @@ config PINCTRL_SUNRISEPOINT config PINCTRL_TIGERLAKE tristate "Intel Tiger Lake pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring -- cgit From d5301c90716a8e20bc961a348182daca00c8e8f0 Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Tue, 22 Aug 2023 12:53:40 +0530 Subject: pinctrl: cherryview: fix address_space_handler() argument First argument of acpi_*_address_space_handler() APIs is acpi_handle of the device, which is incorrectly passed in driver ->remove() path here. Fix it by passing the appropriate argument and while at it, make both API calls consistent using ACPI_HANDLE(). Fixes: a0b028597d59 ("pinctrl: cherryview: Add support for GMMR GPIO opregion") Cc: stable@vger.kernel.org Signed-off-by: Raag Jadav Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 55a42dbf97b6..81ee949b946d 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1649,7 +1649,6 @@ static int chv_pinctrl_probe(struct platform_device *pdev) struct intel_community_context *cctx; struct intel_community *community; struct device *dev = &pdev->dev; - struct acpi_device *adev = ACPI_COMPANION(dev); struct intel_pinctrl *pctrl; acpi_status status; unsigned int i; @@ -1717,7 +1716,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev) if (ret) return ret; - status = acpi_install_address_space_handler(adev->handle, + status = acpi_install_address_space_handler(ACPI_HANDLE(dev), community->acpi_space_id, chv_pinctrl_mmio_access_handler, NULL, pctrl); @@ -1734,7 +1733,7 @@ static int chv_pinctrl_remove(struct platform_device *pdev) struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); const struct intel_community *community = &pctrl->communities[0]; - acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), + acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev), community->acpi_space_id, chv_pinctrl_mmio_access_handler); -- cgit From c0f84760b01e8d8b59e9e186a4f7fa8f081a4488 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 23 Aug 2023 10:55:46 +0200 Subject: pinctrl: use capital "OR" for multiple licenses in SPDX Documentation/process/license-rules.rst and checkpatch expect the SPDX identifier syntax for multiple licenses to use capital "OR". Correct it to keep consistent format and avoid copy-paste issues. Correct also the placement of SPDX identifier in pinctrl-meson-axg files: WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230823085546.116494-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 3 +-- drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | 2 +- drivers/pinctrl/meson/pinctrl-meson-axg.c | 3 +-- drivers/pinctrl/meson/pinctrl-meson-g12a.c | 2 +- drivers/pinctrl/pinctrl-mlxbf3.c | 2 +- 5 files changed, 5 insertions(+), 7 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c index 80c43683c789..ae3f8d0da05f 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Second generation of pinmux driver for Amlogic Meson-AXG SoC. * @@ -6,8 +7,6 @@ * * Copyright (c) 2017 Amlogic, Inc. All rights reserved. * Author: Xingyu Chen - * - * SPDX-License-Identifier: (GPL-2.0+ or MIT) */ /* diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h index aa79d7ecee00..67147ebaef1b 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2017 Baylibre SAS. * Author: Jerome Brunet diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c index d249a035c2b9..6667c9d0238f 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -1,10 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Pin controller and GPIO driver for Amlogic Meson AXG SoC. * * Copyright (c) 2017 Amlogic, Inc. All rights reserved. * Author: Xingyu Chen - * - * SPDX-License-Identifier: (GPL-2.0+ or MIT) */ #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index 3cd86d6a0a60..2c17891ba6a9 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Pin controller and GPIO driver for Amlogic Meson G12A SoC. * diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlxbf3.c index d9944e6a0af9..903606b64d2f 100644 --- a/drivers/pinctrl/pinctrl-mlxbf3.c +++ b/drivers/pinctrl/pinctrl-mlxbf3.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause +// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause /* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */ #include -- cgit From 69657e60b8a7faf83b583c658ec7ce1f5ece9eb3 Mon Sep 17 00:00:00 2001 From: Asmaa Mnebhi Date: Fri, 18 Aug 2023 12:43:13 -0400 Subject: pinctrl: mlxbf3: Remove gpio_disable_free() Remove support for gpio_disable_free() because it is called when the libgpiod command "gpioset" is invoked. This gives the GPIO control back to hardware which cancels out the effort to set the GPIO value. Reminder of the code flow to change a GPIO value from software: 1) All GPIOs are controlled by hardware by default 2) To change the GPIO value, enable software control via a mux. 3) Once software has control over the GPIO pin, the gpio-mlxbf3 driver will be able to change the direction and value of the GPIO. When the user runs "gpioset gpiochip0 0=0" for example, the gpio pin value should change from 1 to 0. In this case, mlxbf3_gpio_request_enable() is called via gpiochip_generic_request(). The latter switches GPIO control from hardware to software. Then the GPIO value is changed from 1 to 0. However, gpio_disable_free() is also called which changes control back to hardware which changes the GPIO value back to 1. Fixes: d11f932808dc ("pinctrl: mlxbf3: Add pinctrl driver support") Signed-off-by: Asmaa Mnebhi Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20230818164314.8505-2-asmaa@nvidia.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mlxbf3.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlxbf3.c index 903606b64d2f..7d1713824a89 100644 --- a/drivers/pinctrl/pinctrl-mlxbf3.c +++ b/drivers/pinctrl/pinctrl-mlxbf3.c @@ -223,26 +223,12 @@ static int mlxbf3_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } -static void mlxbf3_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); - - /* disable GPIO functionality by giving control back to hardware */ - if (offset < MLXBF3_NGPIOS_GPIO0) - writel(BIT(offset), priv->fw_ctrl_clr0); - else - writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1); -} - static const struct pinmux_ops mlxbf3_pmx_ops = { .get_functions_count = mlxbf3_pmx_get_funcs_count, .get_function_name = mlxbf3_pmx_get_func_name, .get_function_groups = mlxbf3_pmx_get_groups, .set_mux = mlxbf3_pmx_set, .gpio_request_enable = mlxbf3_gpio_request_enable, - .gpio_disable_free = mlxbf3_gpio_disable_free, }; static struct pinctrl_desc mlxbf3_pin_desc = { -- cgit