From 12d614a0dcaee9668c641fcaa9f524da861a765e Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Thu, 11 Jan 2018 16:40:31 +0530 Subject: platform/x86: intel_pmc_core: Remove unused EXPORTED API Though ChromeOs uses the exported API as part of their S0ix failsafe mechanism, there is no active consumer of this API in upstream kernel. We can revisit this when ChromeOs kernel team is able to get their S0ix failsafe framework in mainline. Cc: Derek Basehore Cc: Rajat Jain Link: https://patchwork.kernel.org/patch/9831229/ Suggested-by: Andriy Shevchenko Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 32 -------------------------------- 1 file changed, 32 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 17e08b42b0a9..00748472a55e 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -146,37 +146,6 @@ static inline u32 pmc_core_adjust_slp_s0_step(u32 value) return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP; } -/** - * intel_pmc_slp_s0_counter_read() - Read SLP_S0 residency. - * @data: Out param that contains current SLP_S0 count. - * - * This API currently supports Intel Skylake SoC and Sunrise - * Point Platform Controller Hub. Future platform support - * should be added for platforms that support low power modes - * beyond Package C10 state. - * - * SLP_S0_RESIDENCY counter counts in 100 us granularity per - * step hence function populates the multiplied value in out - * parameter @data. - * - * Return: an error code or 0 on success. - */ -int intel_pmc_slp_s0_counter_read(u32 *data) -{ - struct pmc_dev *pmcdev = &pmc; - const struct pmc_reg_map *map = pmcdev->map; - u32 value; - - if (!pmcdev->has_slp_s0_res) - return -EACCES; - - value = pmc_core_reg_read(pmcdev, map->slp_s0_offset); - *data = pmc_core_adjust_slp_s0_step(value); - - return 0; -} -EXPORT_SYMBOL_GPL(intel_pmc_slp_s0_counter_read); - static int pmc_core_dev_state_get(void *data, u64 *val) { struct pmc_dev *pmcdev = data; @@ -548,7 +517,6 @@ static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id) if (err < 0) dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n"); - pmc.has_slp_s0_res = true; return 0; } -- cgit From 2854a0aa822c11ea8538ebfe94a62e20ab570e2b Mon Sep 17 00:00:00 2001 From: Srinivas Pandruvada Date: Thu, 11 Jan 2018 16:40:34 +0530 Subject: platform/x86: intel_pmc_core: Change driver to a module Allow the driver to be a module since builtin_pci_driver funtionality is no longer needed. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 00748472a55e..44353034718a 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -21,8 +21,8 @@ #include #include #include -#include #include +#include #include #include @@ -124,6 +124,7 @@ static const struct pci_device_id pmc_pci_ids[] = { (kernel_ulong_t)&spt_reg_map }, { 0, }, }; +MODULE_DEVICE_TABLE(pci, pmc_pci_ids); static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset) { @@ -520,10 +521,20 @@ static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id) return 0; } +static void pmc_core_remove(struct pci_dev *dev) +{ + pmc_core_dbgfs_unregister(&pmc); + mutex_destroy(&pmc.lock); +} + static struct pci_driver intel_pmc_core_driver = { .name = "intel_pmc_core", .id_table = pmc_pci_ids, .probe = pmc_core_probe, + .remove = pmc_core_remove, }; -builtin_pci_driver(intel_pmc_core_driver); +module_pci_driver(intel_pmc_core_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Intel PMC Core Driver"); -- cgit From 1f644da7e920cb83403818efa88ebfb6d1528264 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Thu, 11 Jan 2018 16:40:35 +0530 Subject: platform/x86: intel_pmc_core: Fix file permission warnings Symbolic permissions 'S_IRUGO' are not preferred. This patch changes the debugfs files to use octal permissions '0644' or '0444' as needed by the attribute. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 44353034718a..cf8b3b34a979 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -414,31 +414,27 @@ static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev) return -ENOMEM; pmcdev->dbgfs_dir = dir; - file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO, + file = debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev, &pmc_core_dev_state); if (!file) goto err; - file = debugfs_create_file("pch_ip_power_gating_status", - S_IFREG | S_IRUGO, dir, pmcdev, - &pmc_core_ppfear_ops); + file = debugfs_create_file("pch_ip_power_gating_status", 0444, + dir, pmcdev, &pmc_core_ppfear_ops); if (!file) goto err; - file = debugfs_create_file("mphy_core_lanes_power_gating_status", - S_IFREG | S_IRUGO, dir, pmcdev, - &pmc_core_mphy_pg_ops); + file = debugfs_create_file("mphy_core_lanes_power_gating_status", 0444, + dir, pmcdev, &pmc_core_mphy_pg_ops); if (!file) goto err; - file = debugfs_create_file("pll_status", - S_IFREG | S_IRUGO, dir, pmcdev, + file = debugfs_create_file("pll_status", 0444, dir, pmcdev, &pmc_core_pll_ops); if (!file) goto err; - file = debugfs_create_file("ltr_ignore", - S_IFREG | S_IRUGO, dir, pmcdev, + file = debugfs_create_file("ltr_ignore", 0644, dir, pmcdev, &pmc_core_ltr_ignore_ops); if (!file) -- cgit From 750e0f570b7145870d40f07337f3356c18e0abd4 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Fri, 19 Jan 2018 14:28:20 +0530 Subject: platform/x86: intel_pmc_core: Refactor debugfs entries When on a platform if we can't show MPHY and PLL status, don't even bother to create a debugfs entry as it will fail anyway. In fact unless OEM builds a special BIOS for test, it will fail on every production system. This will help to add future platform support where we can't support these entries. Suggested-by: Andy Shevchenko Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 38 +++++++++++++---------------------- 1 file changed, 14 insertions(+), 24 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index cf8b3b34a979..da924d3bb3e5 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -407,43 +407,33 @@ static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev) static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev) { - struct dentry *dir, *file; + struct dentry *dir; dir = debugfs_create_dir("pmc_core", NULL); if (!dir) return -ENOMEM; pmcdev->dbgfs_dir = dir; - file = debugfs_create_file("slp_s0_residency_usec", 0444, - dir, pmcdev, &pmc_core_dev_state); - if (!file) - goto err; - file = debugfs_create_file("pch_ip_power_gating_status", 0444, - dir, pmcdev, &pmc_core_ppfear_ops); - if (!file) - goto err; + debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev, + &pmc_core_dev_state); - file = debugfs_create_file("mphy_core_lanes_power_gating_status", 0444, - dir, pmcdev, &pmc_core_mphy_pg_ops); - if (!file) - goto err; + debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev, + &pmc_core_ppfear_ops); - file = debugfs_create_file("pll_status", 0444, dir, pmcdev, - &pmc_core_pll_ops); - if (!file) - goto err; + debugfs_create_file("ltr_ignore", 0644, dir, pmcdev, + &pmc_core_ltr_ignore_ops); - file = debugfs_create_file("ltr_ignore", 0644, dir, pmcdev, - &pmc_core_ltr_ignore_ops); + if (pmcdev->map->pll_sts) + debugfs_create_file("pll_status", 0444, dir, pmcdev, + &pmc_core_pll_ops); - if (!file) - goto err; + if (pmcdev->map->mphy_sts) + debugfs_create_file("mphy_core_lanes_power_gating_status", + 0444, dir, pmcdev, + &pmc_core_mphy_pg_ops); return 0; -err: - pmc_core_dbgfs_unregister(pmcdev); - return -ENODEV; } #else static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev) -- cgit From 21ae43570940f8393a80369f62a3880bd64daad8 Mon Sep 17 00:00:00 2001 From: Srinivas Pandruvada Date: Fri, 19 Jan 2018 14:28:21 +0530 Subject: platform/x86: intel_pmc_core: Substitute PCI with CPUID enumeration The Only use of PCI device enumeration here is to get the PMC base address which is a fixed value i.e. 0xFE000000. On some platforms this can be read through a non standard PCI BAR. But after Kabylake, PMC is not exposed as a PCI device anymore. There are other non standard methods like ACPI LPIT which can also be used for obtaining this value. For simplicity, this value can be hardcoded as it won't change. Since we don't have a PMC PCI device on any platform after Kabylake, this creates a foundation for future SoC support. Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Srinivas Pandruvada Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 89 ++++++++++++----------------------- 1 file changed, 31 insertions(+), 58 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index da924d3bb3e5..e3b98fcceb57 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -18,12 +18,12 @@ * */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include #include -#include #include #include -#include #include #include @@ -119,13 +119,6 @@ static const struct pmc_reg_map spt_reg_map = { .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT, }; -static const struct pci_device_id pmc_pci_ids[] = { - { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), - (kernel_ulong_t)&spt_reg_map }, - { 0, }, -}; -MODULE_DEVICE_TABLE(pci, pmc_pci_ids); - static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset) { return readb(pmcdev->regbase + offset); @@ -448,79 +441,59 @@ static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev) static const struct x86_cpu_id intel_pmc_core_ids[] = { { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT, - (kernel_ulong_t)NULL}, + (kernel_ulong_t)&spt_reg_map}, { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT, - (kernel_ulong_t)NULL}, + (kernel_ulong_t)&spt_reg_map}, { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_MOBILE, X86_FEATURE_MWAIT, - (kernel_ulong_t)NULL}, + (kernel_ulong_t)&spt_reg_map}, { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_DESKTOP, X86_FEATURE_MWAIT, - (kernel_ulong_t)NULL}, + (kernel_ulong_t)&spt_reg_map}, {} }; -static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id) +MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids); + +static int __init pmc_core_probe(void) { - struct device *ptr_dev = &dev->dev; struct pmc_dev *pmcdev = &pmc; const struct x86_cpu_id *cpu_id; - const struct pmc_reg_map *map = (struct pmc_reg_map *)id->driver_data; int err; cpu_id = x86_match_cpu(intel_pmc_core_ids); - if (!cpu_id) { - dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n"); - return -EINVAL; - } - - err = pcim_enable_device(dev); - if (err < 0) { - dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n"); - return err; - } - - err = pci_read_config_dword(dev, - SPT_PMC_BASE_ADDR_OFFSET, - &pmcdev->base_addr); - if (err < 0) { - dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n"); - return err; - } - pmcdev->base_addr &= PMC_BASE_ADDR_MASK; - dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr); - - pmcdev->regbase = devm_ioremap_nocache(ptr_dev, - pmcdev->base_addr, - SPT_PMC_MMIO_REG_LEN); - if (!pmcdev->regbase) { - dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n"); + if (!cpu_id) + return -ENODEV; + + pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data; + pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT; + pmcdev->regbase = ioremap(pmcdev->base_addr, + pmcdev->map->regmap_length); + if (!pmcdev->regbase) return -ENOMEM; - } mutex_init(&pmcdev->lock); - pmcdev->map = map; pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit(); err = pmc_core_dbgfs_register(pmcdev); - if (err < 0) - dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n"); + if (err < 0) { + pr_warn(" debugfs register failed.\n"); + iounmap(pmcdev->regbase); + return err; + } + pr_info(" initialized\n"); return 0; } +module_init(pmc_core_probe) -static void pmc_core_remove(struct pci_dev *dev) +static void __exit pmc_core_remove(void) { - pmc_core_dbgfs_unregister(&pmc); - mutex_destroy(&pmc.lock); -} - -static struct pci_driver intel_pmc_core_driver = { - .name = "intel_pmc_core", - .id_table = pmc_pci_ids, - .probe = pmc_core_probe, - .remove = pmc_core_remove, -}; + struct pmc_dev *pmcdev = &pmc; -module_pci_driver(intel_pmc_core_driver); + pmc_core_dbgfs_unregister(pmcdev); + mutex_destroy(&pmcdev->lock); + iounmap(pmcdev->regbase); +} +module_exit(pmc_core_remove) MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("Intel PMC Core Driver"); -- cgit From 00f8b2fce4da2296bafc1de6a46510a13ef60938 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Fri, 19 Jan 2018 14:28:24 +0530 Subject: platform/x86: intel_pmc_core: Convert to ICPU macro Use ICPU macro to refactor code related to x86_cpu_id for better readability. Suggested-by: Andy Shevchenko Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index e3b98fcceb57..f971ca1a6ed2 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -32,6 +32,9 @@ #include "intel_pmc_core.h" +#define ICPU(model, data) \ + { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (kernel_ulong_t)data } + static struct pmc_dev pmc; static const struct pmc_bit_map spt_pll_map[] = { @@ -440,14 +443,10 @@ static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev) #endif /* CONFIG_DEBUG_FS */ static const struct x86_cpu_id intel_pmc_core_ids[] = { - { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT, - (kernel_ulong_t)&spt_reg_map}, - { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT, - (kernel_ulong_t)&spt_reg_map}, - { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_MOBILE, X86_FEATURE_MWAIT, - (kernel_ulong_t)&spt_reg_map}, - { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_DESKTOP, X86_FEATURE_MWAIT, - (kernel_ulong_t)&spt_reg_map}, + ICPU(INTEL_FAM6_SKYLAKE_MOBILE, &spt_reg_map), + ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map), + ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map), + ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map), {} }; -- cgit From 941691ef2197944a202d7870dcd7da3fb0391c65 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Wed, 31 Jan 2018 11:50:22 +0530 Subject: platform/x86: intel_pmc_core: Remove unused header file Recently sent patch 'platform/x86: intel_pmc_core: Remove unused EXPORTED API' missed to remove the header file 'arch/x86/include/asm/pmc_core.h' which was solely used to declare the EXPORTED API 'intel_pmc_slp_s0_counter_read'. This patch provides the errata fix for the same. Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index f971ca1a6ed2..5c401e17cfb6 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -28,7 +28,6 @@ #include #include -#include #include "intel_pmc_core.h" -- cgit From 745698c37c08f48fb5ad3c0cb7ee955bd5701d4a Mon Sep 17 00:00:00 2001 From: Srinivas Pandruvada Date: Fri, 2 Feb 2018 19:13:34 +0530 Subject: platform/x86: intel_pmc_core: Read base address from LPIT Read SLP_S0 address from ACPI LPIT table when present and use PMC specific SLP_S0 offset to get the base address of PMC MMIO. Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Srinivas Pandruvada Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 5c401e17cfb6..bb80aed4c3c1 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -20,6 +20,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -455,6 +456,7 @@ static int __init pmc_core_probe(void) { struct pmc_dev *pmcdev = &pmc; const struct x86_cpu_id *cpu_id; + u64 slp_s0_addr; int err; cpu_id = x86_match_cpu(intel_pmc_core_ids); @@ -462,7 +464,12 @@ static int __init pmc_core_probe(void) return -ENODEV; pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data; - pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT; + + if (lpit_read_residency_count_address(&slp_s0_addr)) + pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT; + else + pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset; + pmcdev->regbase = ioremap(pmcdev->base_addr, pmcdev->map->regmap_length); if (!pmcdev->regbase) -- cgit From 291101f6a73566f5d1ab597784288c5bc85906fd Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Fri, 2 Feb 2018 19:13:36 +0530 Subject: platform/x86: intel_pmc_core: Add CannonLake PCH support This adds support for Cannonlake PCH which is used by Cannonlake and Coffeelake SoCs. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 85 +++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index bb80aed4c3c1..a255c4b0f7a8 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -122,6 +122,90 @@ static const struct pmc_reg_map spt_reg_map = { .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT, }; +/* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */ +static const struct pmc_bit_map cnp_pfear_map[] = { + {"PMC", BIT(0)}, + {"OPI-DMI", BIT(1)}, + {"SPI/eSPI", BIT(2)}, + {"XHCI", BIT(3)}, + {"SPA", BIT(4)}, + {"SPB", BIT(5)}, + {"SPC", BIT(6)}, + {"GBE", BIT(7)}, + + {"SATA", BIT(0)}, + {"HDA_PGD0", BIT(1)}, + {"HDA_PGD1", BIT(2)}, + {"HDA_PGD2", BIT(3)}, + {"HDA_PGD3", BIT(4)}, + {"SPD", BIT(5)}, + {"LPSS", BIT(6)}, + {"LPC", BIT(7)}, + + {"SMB", BIT(0)}, + {"ISH", BIT(1)}, + {"P2SB", BIT(2)}, + {"NPK_VNN", BIT(3)}, + {"SDX", BIT(4)}, + {"SPE", BIT(5)}, + {"Fuse", BIT(6)}, + {"Res_23", BIT(7)}, + + {"CSME_FSC", BIT(0)}, + {"USB3_OTG", BIT(1)}, + {"EXI", BIT(2)}, + {"CSE", BIT(3)}, + {"csme_kvm", BIT(4)}, + {"csme_pmt", BIT(5)}, + {"csme_clink", BIT(6)}, + {"csme_ptio", BIT(7)}, + + {"csme_usbr", BIT(0)}, + {"csme_susram", BIT(1)}, + {"csme_smt1", BIT(2)}, + {"CSME_SMT4", BIT(3)}, + {"csme_sms2", BIT(4)}, + {"csme_sms1", BIT(5)}, + {"csme_rtc", BIT(6)}, + {"csme_psf", BIT(7)}, + + {"SBR0", BIT(0)}, + {"SBR1", BIT(1)}, + {"SBR2", BIT(2)}, + {"SBR3", BIT(3)}, + {"SBR4", BIT(4)}, + {"SBR5", BIT(5)}, + {"CSME_PECI", BIT(6)}, + {"PSF1", BIT(7)}, + + {"PSF2", BIT(0)}, + {"PSF3", BIT(1)}, + {"PSF4", BIT(2)}, + {"CNVI", BIT(3)}, + {"UFS0", BIT(4)}, + {"EMMC", BIT(5)}, + {"Res_6", BIT(6)}, + {"SBR6", BIT(7)}, + + {"SBR7", BIT(0)}, + {"NPK_AON", BIT(1)}, + {"HDA_PGD4", BIT(2)}, + {"HDA_PGD5", BIT(3)}, + {"HDA_PGD6", BIT(4)}, + {} +}; + +static const struct pmc_reg_map cnp_reg_map = { + .pfear_sts = cnp_pfear_map, + .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, + .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, + .regmap_length = CNP_PMC_MMIO_REG_LEN, + .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, + .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES, + .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, + .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, +}; + static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset) { return readb(pmcdev->regbase + offset); @@ -447,6 +531,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = { ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map), ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map), ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map), + ICPU(INTEL_FAM6_CANNONLAKE_MOBILE, &cnp_reg_map), {} }; -- cgit From 661405bd817b209ac9bd4812c63d90873a7f2993 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Fri, 2 Feb 2018 19:13:37 +0530 Subject: platform/x86: intel_pmc_core: Special case for Coffeelake Intel CoffeeLake SoC uses CPU ID of KabyLake but has Cannonlake PCH, so in this case PMC register details from Cannonlake PCH must be used. In order to identify whether the given platform is Coffeelake, scan for the Sunrisepoint PMC PCI Id. KBL CPUID SPT PCIID ------------------------------------ KBL | Y | Y | ------------------------------------ CFL | Y | N | ------------------------------------ Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index a255c4b0f7a8..43bbe74743d9 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -537,6 +538,11 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = { MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids); +static const struct pci_device_id pmc_pci_ids[] = { + { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0}, + { 0, }, +}; + static int __init pmc_core_probe(void) { struct pmc_dev *pmcdev = &pmc; @@ -550,6 +556,14 @@ static int __init pmc_core_probe(void) pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data; + /* + * Coffeelake has CPU ID of Kabylake and Cannonlake PCH. So here + * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap + * in this case. + */ + if (!pci_dev_present(pmc_pci_ids)) + pmcdev->map = &cnp_reg_map; + if (lpit_read_residency_count_address(&slp_s0_addr)) pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT; else -- cgit