From 971f128bb2d9314203d365b7f163a5c35167bb6b Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 12 Oct 2023 10:22:09 +0100 Subject: soc: sifive: shunt ccache driver to drivers/cache Move the ccache driver over to drivers/cache, out of the drivers/soc dumping ground, to this new collection point for cache controller drivers. Reviewed-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Conor Dooley --- drivers/soc/Kconfig | 1 - drivers/soc/Makefile | 1 - drivers/soc/sifive/Kconfig | 10 -- drivers/soc/sifive/Makefile | 3 - drivers/soc/sifive/sifive_ccache.c | 272 ------------------------------------- 5 files changed, 287 deletions(-) delete mode 100644 drivers/soc/sifive/Kconfig delete mode 100644 drivers/soc/sifive/Makefile delete mode 100644 drivers/soc/sifive/sifive_ccache.c (limited to 'drivers/soc') diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 10a9ff84ff41..5d924e946507 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -22,7 +22,6 @@ source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" -source "drivers/soc/sifive/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 0706a27d13be..ba8f5b5460e1 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -28,7 +28,6 @@ obj-y += qcom/ obj-y += renesas/ obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ -obj-y += sifive/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig deleted file mode 100644 index 139884addc41..000000000000 --- a/drivers/soc/sifive/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -if ARCH_SIFIVE || ARCH_STARFIVE - -config SIFIVE_CCACHE - bool "Sifive Composable Cache controller" - help - Support for the composable cache controller on SiFive platforms. - -endif diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile deleted file mode 100644 index 1f5dc339bf82..000000000000 --- a/drivers/soc/sifive/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c deleted file mode 100644 index 3684f5b40a80..000000000000 --- a/drivers/soc/sifive/sifive_ccache.c +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SiFive composable cache controller Driver - * - * Copyright (C) 2018-2022 SiFive, Inc. - * - */ - -#define pr_fmt(fmt) "CCACHE: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include - -#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 -#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104 -#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108 - -#define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120 -#define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124 -#define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128 - -#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140 -#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144 -#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148 - -#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160 -#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164 -#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 - -#define SIFIVE_CCACHE_CONFIG 0x00 -#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0) -#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8) -#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) -#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) - -#define SIFIVE_CCACHE_WAYENABLE 0x08 -#define SIFIVE_CCACHE_ECCINJECTERR 0x40 - -#define SIFIVE_CCACHE_MAX_ECCINTR 4 - -static void __iomem *ccache_base; -static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; -static struct riscv_cacheinfo_ops ccache_cache_ops; -static int level; - -enum { - DIR_CORR = 0, - DATA_CORR, - DATA_UNCORR, - DIR_UNCORR, -}; - -#ifdef CONFIG_DEBUG_FS -static struct dentry *sifive_test; - -static ssize_t ccache_write(struct file *file, const char __user *data, - size_t count, loff_t *ppos) -{ - unsigned int val; - - if (kstrtouint_from_user(data, count, 0, &val)) - return -EINVAL; - if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) - writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR); - else - return -EINVAL; - return count; -} - -static const struct file_operations ccache_fops = { - .owner = THIS_MODULE, - .open = simple_open, - .write = ccache_write -}; - -static void setup_sifive_debug(void) -{ - sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL); - - debugfs_create_file("sifive_debug_inject_error", 0200, - sifive_test, NULL, &ccache_fops); -} -#endif - -static void ccache_config_read(void) -{ - u32 cfg; - - cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n", - FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg), - FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg), - BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)), - BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg))); - - cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("Index of the largest way enabled: %u\n", cfg); -} - -static const struct of_device_id sifive_ccache_ids[] = { - { .compatible = "sifive,fu540-c000-ccache" }, - { .compatible = "sifive,fu740-c000-ccache" }, - { .compatible = "sifive,ccache0" }, - { /* end of table */ } -}; - -static ATOMIC_NOTIFIER_HEAD(ccache_err_chain); - -int register_sifive_ccache_error_notifier(struct notifier_block *nb) -{ - return atomic_notifier_chain_register(&ccache_err_chain, nb); -} -EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier); - -int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) -{ - return atomic_notifier_chain_unregister(&ccache_err_chain, nb); -} -EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); - -static int ccache_largest_wayenabled(void) -{ - return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; -} - -static ssize_t number_of_ways_enabled_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - return sprintf(buf, "%u\n", ccache_largest_wayenabled()); -} - -static DEVICE_ATTR_RO(number_of_ways_enabled); - -static struct attribute *priv_attrs[] = { - &dev_attr_number_of_ways_enabled.attr, - NULL, -}; - -static const struct attribute_group priv_attr_group = { - .attrs = priv_attrs, -}; - -static const struct attribute_group *ccache_get_priv_group(struct cacheinfo - *this_leaf) -{ - /* We want to use private group for composable cache only */ - if (this_leaf->level == level) - return &priv_attr_group; - else - return NULL; -} - -static irqreturn_t ccache_int_handler(int irq, void *device) -{ - unsigned int add_h, add_l; - - if (irq == g_irq[DIR_CORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); - pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l); - /* Reading this register clears the DirError interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); - atomic_notifier_call_chain(&ccache_err_chain, - SIFIVE_CCACHE_ERR_TYPE_CE, - "DirECCFix"); - } - if (irq == g_irq[DIR_UNCORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); - /* Reading this register clears the DirFail interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); - atomic_notifier_call_chain(&ccache_err_chain, - SIFIVE_CCACHE_ERR_TYPE_UE, - "DirECCFail"); - panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); - } - if (irq == g_irq[DATA_CORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); - pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l); - /* Reading this register clears the DataError interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); - atomic_notifier_call_chain(&ccache_err_chain, - SIFIVE_CCACHE_ERR_TYPE_CE, - "DatECCFix"); - } - if (irq == g_irq[DATA_UNCORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); - pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l); - /* Reading this register clears the DataFail interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); - atomic_notifier_call_chain(&ccache_err_chain, - SIFIVE_CCACHE_ERR_TYPE_UE, - "DatECCFail"); - } - - return IRQ_HANDLED; -} - -static int __init sifive_ccache_init(void) -{ - struct device_node *np; - struct resource res; - int i, rc, intr_num; - - np = of_find_matching_node(NULL, sifive_ccache_ids); - if (!np) - return -ENODEV; - - if (of_address_to_resource(np, 0, &res)) { - rc = -ENODEV; - goto err_node_put; - } - - ccache_base = ioremap(res.start, resource_size(&res)); - if (!ccache_base) { - rc = -ENOMEM; - goto err_node_put; - } - - if (of_property_read_u32(np, "cache-level", &level)) { - rc = -ENOENT; - goto err_unmap; - } - - intr_num = of_property_count_u32_elems(np, "interrupts"); - if (!intr_num) { - pr_err("No interrupts property\n"); - rc = -ENODEV; - goto err_unmap; - } - - for (i = 0; i < intr_num; i++) { - g_irq[i] = irq_of_parse_and_map(np, i); - rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", - NULL); - if (rc) { - pr_err("Could not request IRQ %d\n", g_irq[i]); - goto err_free_irq; - } - } - of_node_put(np); - - ccache_config_read(); - - ccache_cache_ops.get_priv_group = ccache_get_priv_group; - riscv_set_cacheinfo_ops(&ccache_cache_ops); - -#ifdef CONFIG_DEBUG_FS - setup_sifive_debug(); -#endif - return 0; - -err_free_irq: - while (--i >= 0) - free_irq(g_irq[i], NULL); -err_unmap: - iounmap(ccache_base); -err_node_put: - of_node_put(np); - return rc; -} - -device_initcall(sifive_ccache_init); -- cgit