From c9deb9a4f574b49bfd00be88aba470659d2db671 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Fri, 26 Apr 2024 13:20:02 +0100 Subject: scsi: ufs: exynos: Allow max frequencies up to 267Mhz Platforms such as Tensor gs101 the pclk frequency is 267Mhz. Increase PCLK_AVAIL_MAX so we don't fail the frequency check. Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20240426122004.2249178-5-peter.griffin@linaro.org Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker Signed-off-by: Martin K. Petersen --- drivers/ufs/host/ufs-exynos.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/ufs') diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index acf07cc54684..7acc13914100 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -116,7 +116,7 @@ struct exynos_ufs; #define PA_HIBERN8TIME_VAL 0x20 #define PCLK_AVAIL_MIN 70000000 -#define PCLK_AVAIL_MAX 167000000 +#define PCLK_AVAIL_MAX 267000000 struct exynos_ufs_uic_attr { /* TX Attributes */ -- cgit