From aec2927b5944df70bca4bdeea6c4e7c3195dc37a Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Mon, 8 Jan 2018 07:30:53 -0500 Subject: usb: renesas_usbhs: Add support for RZ/A1 This patch adds the capability to support RZ/A1 SoCs. Signed-off-by: Chris Brandt Signed-off-by: Greg Kroah-Hartman --- drivers/usb/renesas_usbhs/common.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/usb/renesas_usbhs/common.h') diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h index c9747f064601..f619afeae2b8 100644 --- a/drivers/usb/renesas_usbhs/common.h +++ b/drivers/usb/renesas_usbhs/common.h @@ -98,6 +98,7 @@ struct usbhs_priv; #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */ #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */ #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */ +#define SUSPMODE 0x0102 /* for RZ/A */ /* SYSCFG */ #define SCKE (1 << 10) /* USB Module Clock Enable */ @@ -106,6 +107,8 @@ struct usbhs_priv; #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */ #define DPRPU (1 << 4) /* D+ Line Resistance Control */ #define USBE (1 << 0) /* USB Module Operation Enable */ +#define UCKSEL (1 << 2) /* Clock Select for RZ/A1 */ +#define UPLLE (1 << 1) /* USB PLL Enable for RZ/A1 */ /* DVSTCTR */ #define EXTLP (1 << 10) /* Controls the EXTLP pin output state */ @@ -233,6 +236,9 @@ struct usbhs_priv; #define USBSPD_SPEED_FULL 0x2 #define USBSPD_SPEED_HIGH 0x3 +/* SUSPMODE */ +#define SUSPM (1 << 14) /* SuspendM Control */ + /* * struct */ -- cgit