From dd08ebf6c3525a7ea2186e636df064ea47281987 Mon Sep 17 00:00:00 2001 From: Matthew Brost Date: Thu, 30 Mar 2023 17:31:57 -0400 Subject: drm/xe: Introduce a new DRM driver for Intel GPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Xe, is a new driver for Intel GPUs that supports both integrated and discrete platforms starting with Tiger Lake (first Intel Xe Architecture). The code is at a stage where it is already functional and has experimental support for multiple platforms starting from Tiger Lake, with initial support implemented in Mesa (for Iris and Anv, our OpenGL and Vulkan drivers), as well as in NEO (for OpenCL and Level0). The new Xe driver leverages a lot from i915. As for display, the intent is to share the display code with the i915 driver so that there is maximum reuse there. But it is not added in this patch. This initial work is a collaboration of many people and unfortunately the big squashed patch won't fully honor the proper credits. But let's get some git quick stats so we can at least try to preserve some of the credits: Co-developed-by: Matthew Brost Co-developed-by: Matthew Auld Co-developed-by: Matt Roper Co-developed-by: Thomas Hellström Co-developed-by: Francois Dugast Co-developed-by: Lucas De Marchi Co-developed-by: Maarten Lankhorst Co-developed-by: Philippe Lecluse Co-developed-by: Nirmoy Das Co-developed-by: Jani Nikula Co-developed-by: José Roberto de Souza Co-developed-by: Rodrigo Vivi Co-developed-by: Dave Airlie Co-developed-by: Faith Ekstrand Co-developed-by: Daniel Vetter Co-developed-by: Mauro Carvalho Chehab Signed-off-by: Rodrigo Vivi Signed-off-by: Matthew Brost --- include/drm/xe_pciids.h | 195 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 include/drm/xe_pciids.h (limited to 'include/drm') diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h new file mode 100644 index 000000000000..e539594ed939 --- /dev/null +++ b/include/drm/xe_pciids.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef _XE_PCIIDS_H_ +#define _XE_PCIIDS_H_ + +/* + * Lists below can be turned into initializers for a struct pci_device_id + * by defining INTEL_VGA_DEVICE: + * + * #define INTEL_VGA_DEVICE(id, info) { \ + * 0x8086, id, \ + * ~0, ~0, \ + * 0x030000, 0xff0000, \ + * (unsigned long) info } + * + * And then calling like: + * + * XE_TGL_12_GT1_IDS(INTEL_VGA_DEVICE, ## __VA_ARGS__) + * + * To turn them into something else, just provide a different macro passed as + * first argument. + */ + +/* TGL */ +#define XE_TGL_GT1_IDS(MACRO__, ...) \ + MACRO__(0x9A60, ## __VA_ARGS__), \ + MACRO__(0x9A68, ## __VA_ARGS__), \ + MACRO__(0x9A70, ## __VA_ARGS__) + +#define XE_TGL_GT2_IDS(MACRO__, ...) \ + MACRO__(0x9A40, ## __VA_ARGS__), \ + MACRO__(0x9A49, ## __VA_ARGS__), \ + MACRO__(0x9A59, ## __VA_ARGS__), \ + MACRO__(0x9A78, ## __VA_ARGS__), \ + MACRO__(0x9AC0, ## __VA_ARGS__), \ + MACRO__(0x9AC9, ## __VA_ARGS__), \ + MACRO__(0x9AD9, ## __VA_ARGS__), \ + MACRO__(0x9AF8, ## __VA_ARGS__) + +#define XE_TGL_IDS(MACRO__, ...) \ + XE_TGL_GT1_IDS(MACRO__, ...), \ + XE_TGL_GT2_IDS(MACRO__, ...) + +/* RKL */ +#define XE_RKL_IDS(MACRO__, ...) \ + MACRO__(0x4C80, ## __VA_ARGS__), \ + MACRO__(0x4C8A, ## __VA_ARGS__), \ + MACRO__(0x4C8B, ## __VA_ARGS__), \ + MACRO__(0x4C8C, ## __VA_ARGS__), \ + MACRO__(0x4C90, ## __VA_ARGS__), \ + MACRO__(0x4C9A, ## __VA_ARGS__) + +/* DG1 */ +#define XE_DG1_IDS(MACRO__, ...) \ + MACRO__(0x4905, ## __VA_ARGS__), \ + MACRO__(0x4906, ## __VA_ARGS__), \ + MACRO__(0x4907, ## __VA_ARGS__), \ + MACRO__(0x4908, ## __VA_ARGS__), \ + MACRO__(0x4909, ## __VA_ARGS__) + +/* ADL-S */ +#define XE_ADLS_IDS(MACRO__, ...) \ + MACRO__(0x4680, ## __VA_ARGS__), \ + MACRO__(0x4682, ## __VA_ARGS__), \ + MACRO__(0x4688, ## __VA_ARGS__), \ + MACRO__(0x468A, ## __VA_ARGS__), \ + MACRO__(0x4690, ## __VA_ARGS__), \ + MACRO__(0x4692, ## __VA_ARGS__), \ + MACRO__(0x4693, ## __VA_ARGS__) + +/* ADL-P */ +#define XE_ADLP_IDS(MACRO__, ...) \ + MACRO__(0x46A0, ## __VA_ARGS__), \ + MACRO__(0x46A1, ## __VA_ARGS__), \ + MACRO__(0x46A2, ## __VA_ARGS__), \ + MACRO__(0x46A3, ## __VA_ARGS__), \ + MACRO__(0x46A6, ## __VA_ARGS__), \ + MACRO__(0x46A8, ## __VA_ARGS__), \ + MACRO__(0x46AA, ## __VA_ARGS__), \ + MACRO__(0x462A, ## __VA_ARGS__), \ + MACRO__(0x4626, ## __VA_ARGS__), \ + MACRO__(0x4628, ## __VA_ARGS__), \ + MACRO__(0x46B0, ## __VA_ARGS__), \ + MACRO__(0x46B1, ## __VA_ARGS__), \ + MACRO__(0x46B2, ## __VA_ARGS__), \ + MACRO__(0x46B3, ## __VA_ARGS__), \ + MACRO__(0x46C0, ## __VA_ARGS__), \ + MACRO__(0x46C1, ## __VA_ARGS__), \ + MACRO__(0x46C2, ## __VA_ARGS__), \ + MACRO__(0x46C3, ## __VA_ARGS__) + +/* ADL-N */ +#define XE_ADLN_IDS(MACRO__, ...) \ + MACRO__(0x46D0, ## __VA_ARGS__), \ + MACRO__(0x46D1, ## __VA_ARGS__), \ + MACRO__(0x46D2, ## __VA_ARGS__) + +/* RPL-S */ +#define XE_RPLS_IDS(MACRO__, ...) \ + MACRO__(0xA780, ## __VA_ARGS__), \ + MACRO__(0xA781, ## __VA_ARGS__), \ + MACRO__(0xA782, ## __VA_ARGS__), \ + MACRO__(0xA783, ## __VA_ARGS__), \ + MACRO__(0xA788, ## __VA_ARGS__), \ + MACRO__(0xA789, ## __VA_ARGS__), \ + MACRO__(0xA78A, ## __VA_ARGS__), \ + MACRO__(0xA78B, ## __VA_ARGS__) + +/* RPL-U */ +#define XE_RPLU_IDS(MACRO__, ...) \ + MACRO__(0xA721, ## __VA_ARGS__), \ + MACRO__(0xA7A1, ## __VA_ARGS__), \ + MACRO__(0xA7A9, ## __VA_ARGS__) + +/* RPL-P */ +#define XE_RPLP_IDS(MACRO__, ...) \ + MACRO__(0xA720, ## __VA_ARGS__), \ + MACRO__(0xA7A0, ## __VA_ARGS__), \ + MACRO__(0xA7A8, ## __VA_ARGS__) + +/* DG2 */ +#define XE_DG2_G10_IDS(MACRO__, ...) \ + MACRO__(0x5690, ## __VA_ARGS__), \ + MACRO__(0x5691, ## __VA_ARGS__), \ + MACRO__(0x5692, ## __VA_ARGS__), \ + MACRO__(0x56A0, ## __VA_ARGS__), \ + MACRO__(0x56A1, ## __VA_ARGS__), \ + MACRO__(0x56A2, ## __VA_ARGS__) + +#define XE_DG2_G11_IDS(MACRO__, ...) \ + MACRO__(0x5693, ## __VA_ARGS__), \ + MACRO__(0x5694, ## __VA_ARGS__), \ + MACRO__(0x5695, ## __VA_ARGS__), \ + MACRO__(0x5698, ## __VA_ARGS__), \ + MACRO__(0x56A5, ## __VA_ARGS__), \ + MACRO__(0x56A6, ## __VA_ARGS__), \ + MACRO__(0x56B0, ## __VA_ARGS__), \ + MACRO__(0x56B1, ## __VA_ARGS__) + +#define XE_DG2_G12_IDS(MACRO__, ...) \ + MACRO__(0x5696, ## __VA_ARGS__), \ + MACRO__(0x5697, ## __VA_ARGS__), \ + MACRO__(0x56A3, ## __VA_ARGS__), \ + MACRO__(0x56A4, ## __VA_ARGS__), \ + MACRO__(0x56B2, ## __VA_ARGS__), \ + MACRO__(0x56B3, ## __VA_ARGS__) + +#define XE_DG2_IDS(MACRO__, ...) \ + XE_DG2_G10_IDS(MACRO__, ## __VA_ARGS__),\ + XE_DG2_G11_IDS(MACRO__, ## __VA_ARGS__),\ + XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__) + +#define XE_ATS_M150_IDS(MACRO__, ...) \ + MACRO__(0x56C0, ## __VA_ARGS__) + +#define XE_ATS_M75_IDS(MACRO__, ...) \ + MACRO__(0x56C1, ## __VA_ARGS__) + +#define XE_ATS_M_IDS(MACRO__, ...) \ + XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\ + XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) + +/* MTL */ +#define XE_MTL_M_IDS(MACRO__, ...) \ + MACRO__(0x7D40, ## __VA_ARGS__), \ + MACRO__(0x7D43, ## __VA_ARGS__), \ + MACRO__(0x7DC0, ## __VA_ARGS__) + +#define XE_MTL_P_IDS(MACRO__, ...) \ + MACRO__(0x7D45, ## __VA_ARGS__), \ + MACRO__(0x7D47, ## __VA_ARGS__), \ + MACRO__(0x7D50, ## __VA_ARGS__), \ + MACRO__(0x7D55, ## __VA_ARGS__), \ + MACRO__(0x7DC5, ## __VA_ARGS__), \ + MACRO__(0x7DD0, ## __VA_ARGS__), \ + MACRO__(0x7DD5, ## __VA_ARGS__) + +#define XE_MTL_S_IDS(MACRO__, ...) \ + MACRO__(0x7D60, ## __VA_ARGS__), \ + MACRO__(0x7DE0, ## __VA_ARGS__) + +#define XE_ARL_IDS(MACRO__, ...) \ + MACRO__(0x7D66, ## __VA_ARGS__), \ + MACRO__(0x7D76, ## __VA_ARGS__) + +#define XE_MTL_IDS(MACRO__, ...) \ + XE_MTL_M_IDS(MACRO__, ## __VA_ARGS__), \ + XE_MTL_P_IDS(MACRO__, ## __VA_ARGS__), \ + XE_MTL_S_IDS(MACRO__, ## __VA_ARGS__), \ + XE_ARL_IDS(MACRO__, ## __VA_ARGS__) + +#endif -- cgit From 780637e28783af505864151da78e713f62ed64ae Mon Sep 17 00:00:00 2001 From: Carlos Santa Date: Wed, 15 Feb 2023 12:34:25 -0800 Subject: drm/xe: Update the list of devices to add even more TGL devices The list of GTs got splitted a while back between GT1 and GT2 on TGL. References: https://patchwork.freedesktop.org/patch/388414/ CC: Rodrigo Vivi Signed-off-by: Carlos Santa Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi --- include/drm/xe_pciids.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/drm') diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index e539594ed939..b9e9f5b2b0ac 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -41,8 +41,8 @@ MACRO__(0x9AF8, ## __VA_ARGS__) #define XE_TGL_IDS(MACRO__, ...) \ - XE_TGL_GT1_IDS(MACRO__, ...), \ - XE_TGL_GT2_IDS(MACRO__, ...) + XE_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__),\ + XE_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__) /* RKL */ #define XE_RKL_IDS(MACRO__, ...) \ -- cgit From de4651d6dd04d173b50fa8631a9a3cdd897434c4 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Fri, 4 Aug 2023 16:17:09 -0700 Subject: drm/xe: Update ARL-S DevIDs to the latest BSpec BSpec changed with regard the DevIDs for ARL-S. Update the define accordingly. Bspec: 55420 Reviewed-by: Niranjana Vishwanathapura Link: https://lore.kernel.org/r/20230804231709.1065087-3-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Rodrigo Vivi --- include/drm/xe_pciids.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include/drm') diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index b9e9f5b2b0ac..0d0cf80eb0ba 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -183,8 +183,7 @@ MACRO__(0x7DE0, ## __VA_ARGS__) #define XE_ARL_IDS(MACRO__, ...) \ - MACRO__(0x7D66, ## __VA_ARGS__), \ - MACRO__(0x7D76, ## __VA_ARGS__) + MACRO__(0x7D67, ## __VA_ARGS__) #define XE_MTL_IDS(MACRO__, ...) \ XE_MTL_M_IDS(MACRO__, ## __VA_ARGS__), \ -- cgit From 3330361543fca2a60b71ebf02cd5e56bb417b159 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Fri, 11 Aug 2023 09:06:16 -0700 Subject: drm/xe/lnl: Add LNL platform definition LNL is an integrated GPU based on the Xe2 architecture. Bspec: 70821 Signed-off-by: Matt Roper Signed-off-by: Lucas De Marchi Reviewed-by: Balasubramani Vivekanandan Signed-off-by: Rodrigo Vivi --- include/drm/xe_pciids.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/drm') diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index 0d0cf80eb0ba..f6ac6d9772ee 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -191,4 +191,9 @@ XE_MTL_S_IDS(MACRO__, ## __VA_ARGS__), \ XE_ARL_IDS(MACRO__, ## __VA_ARGS__) +#define XE_LNL_IDS(MACRO__, ...) \ + MACRO__(0x6420, ## __VA_ARGS__), \ + MACRO__(0x64A0, ## __VA_ARGS__), \ + MACRO__(0x64B0, ## __VA_ARGS__) + #endif -- cgit From bbd52b6153731908e52f68d7c797bef7c42af4f7 Mon Sep 17 00:00:00 2001 From: Matthew Brost Date: Thu, 31 Aug 2023 07:58:44 -0700 Subject: drm/gpuva: Add drm_gpuva_for_each_op_reverse Add a helper to walk op list in reverse. Xe will make use of this when unwinding GPUVA operations. v2: (Rodrigo) reword commit message Reviewed-by: Rodrigo Vivi Signed-off-by: Matthew Brost Signed-off-by: Rodrigo Vivi --- include/drm/drm_gpuvm.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/drm') diff --git a/include/drm/drm_gpuvm.h b/include/drm/drm_gpuvm.h index 6258849382e1..48311e6d664c 100644 --- a/include/drm/drm_gpuvm.h +++ b/include/drm/drm_gpuvm.h @@ -1007,6 +1007,16 @@ struct drm_gpuva_ops { #define drm_gpuva_for_each_op_from_reverse(op, ops) \ list_for_each_entry_from_reverse(op, &(ops)->list, entry) +/** + * drm_gpuva_for_each_op_reverse - iterator to walk over &drm_gpuva_ops in reverse + * @op: &drm_gpuva_op to assign in each iteration step + * @ops: &drm_gpuva_ops to walk + * + * This iterator walks over all ops within a given list of operations in reverse + */ +#define drm_gpuva_for_each_op_reverse(op, ops) \ + list_for_each_entry_reverse(op, &(ops)->list, entry) + /** * drm_gpuva_first_op() - returns the first &drm_gpuva_op from &drm_gpuva_ops * @ops: the &drm_gpuva_ops to get the fist &drm_gpuva_op from -- cgit From 3445166655cdcdcf18f10ffa124e6ae0ee3018c6 Mon Sep 17 00:00:00 2001 From: Shekhar Chauhan Date: Wed, 11 Oct 2023 10:44:18 +0530 Subject: drm/xe: Add new DG2 PCI IDs Add recently added PCI IDs for DG2 BSpec: 44477 Signed-off-by: Shekhar Chauhan Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20231011051418.2767145-1-shekhar.chauhan@intel.com Signed-off-by: Matt Roper Signed-off-by: Rodrigo Vivi --- include/drm/xe_pciids.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include/drm') diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index f6ac6d9772ee..d105527df0c4 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -138,7 +138,11 @@ MACRO__(0x56A5, ## __VA_ARGS__), \ MACRO__(0x56A6, ## __VA_ARGS__), \ MACRO__(0x56B0, ## __VA_ARGS__), \ - MACRO__(0x56B1, ## __VA_ARGS__) + MACRO__(0x56B1, ## __VA_ARGS__), \ + MACRO__(0x56BA, ## __VA_ARGS__), \ + MACRO__(0x56BB, ## __VA_ARGS__), \ + MACRO__(0x56BC, ## __VA_ARGS__), \ + MACRO__(0x56BD, ## __VA_ARGS__) #define XE_DG2_G12_IDS(MACRO__, ...) \ MACRO__(0x5696, ## __VA_ARGS__), \ -- cgit From cd0adf746527dc2d1410adf5bf09ee6f4cd22a79 Mon Sep 17 00:00:00 2001 From: Shekhar Chauhan Date: Wed, 11 Oct 2023 21:15:26 +0530 Subject: drm/xe/dg2: Remove one PCI ID The bspec was recently updated to remove PCI ID 0x5698; this ID is actually reserved for future use and should not be treated as DG2-G11. BSpec: 44477 Signed-off-by: Shekhar Chauhan Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20231011154526.2819754-1-shekhar.chauhan@intel.com Signed-off-by: Matt Roper Signed-off-by: Rodrigo Vivi --- include/drm/xe_pciids.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/drm') diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index d105527df0c4..11deefceffd0 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -134,7 +134,6 @@ MACRO__(0x5693, ## __VA_ARGS__), \ MACRO__(0x5694, ## __VA_ARGS__), \ MACRO__(0x5695, ## __VA_ARGS__), \ - MACRO__(0x5698, ## __VA_ARGS__), \ MACRO__(0x56A5, ## __VA_ARGS__), \ MACRO__(0x56A6, ## __VA_ARGS__), \ MACRO__(0x56B0, ## __VA_ARGS__), \ -- cgit From baf9089c800c46f224f14e2a681ba3a7c1b09374 Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Fri, 17 Nov 2023 09:29:28 -0800 Subject: drm/xe: Include RPL-U to pciidlist MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RPL-U is defined as a subplatform but those PCI ids were not included in pciidlist so Xe KMD would never probe device with those ids. This is following what i915 does to include RPL-U to PCI ids probe list. v2: - change order to match i915 Cc: Lucas De Marchi Reviewed-by: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Rodrigo Vivi --- include/drm/xe_pciids.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/drm') diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index 11deefceffd0..47ff7472c8bd 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -117,6 +117,7 @@ /* RPL-P */ #define XE_RPLP_IDS(MACRO__, ...) \ + XE_RPLU_IDS(MACRO__, ## __VA_ARGS__), \ MACRO__(0xA720, ## __VA_ARGS__), \ MACRO__(0xA7A0, ## __VA_ARGS__), \ MACRO__(0xA7A8, ## __VA_ARGS__) -- cgit From 1bec833316fffa110259093671d27be137be454d Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Mon, 20 Nov 2023 10:00:35 -0800 Subject: drm/xe: Add missing RPL and ADL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Those are ids present in i915 but missing in Xe. Cc: Lucas De Marchi Reviewed-by: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Rodrigo Vivi --- include/drm/xe_pciids.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'include/drm') diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index 47ff7472c8bd..84fb596ab8f5 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -67,6 +67,7 @@ MACRO__(0x4682, ## __VA_ARGS__), \ MACRO__(0x4688, ## __VA_ARGS__), \ MACRO__(0x468A, ## __VA_ARGS__), \ + MACRO__(0x468B, ## __VA_ARGS__), \ MACRO__(0x4690, ## __VA_ARGS__), \ MACRO__(0x4692, ## __VA_ARGS__), \ MACRO__(0x4693, ## __VA_ARGS__) @@ -113,14 +114,18 @@ #define XE_RPLU_IDS(MACRO__, ...) \ MACRO__(0xA721, ## __VA_ARGS__), \ MACRO__(0xA7A1, ## __VA_ARGS__), \ - MACRO__(0xA7A9, ## __VA_ARGS__) + MACRO__(0xA7A9, ## __VA_ARGS__), \ + MACRO__(0xA7AC, ## __VA_ARGS__), \ + MACRO__(0xA7AD, ## __VA_ARGS__) /* RPL-P */ #define XE_RPLP_IDS(MACRO__, ...) \ XE_RPLU_IDS(MACRO__, ## __VA_ARGS__), \ MACRO__(0xA720, ## __VA_ARGS__), \ MACRO__(0xA7A0, ## __VA_ARGS__), \ - MACRO__(0xA7A8, ## __VA_ARGS__) + MACRO__(0xA7A8, ## __VA_ARGS__), \ + MACRO__(0xA7AA, ## __VA_ARGS__), \ + MACRO__(0xA7AB, ## __VA_ARGS__) /* DG2 */ #define XE_DG2_G10_IDS(MACRO__, ...) \ -- cgit From 1a3d4d76bacee545c620f5935a5bf4677ad88d4c Mon Sep 17 00:00:00 2001 From: Haridhar Kalvala Date: Mon, 20 Nov 2023 12:25:07 +0530 Subject: drm/xe: ATS-M device ID update ATS-M device ID update. BSpec: 44477 Signed-off-by: Haridhar Kalvala Reviewed-by: Matt Roper Reviewed-by: Lucas De Marchi Link: https://lore.kernel.org/r/20231120065507.1543676-1-haridhar.kalvala@intel.com Signed-off-by: Rodrigo Vivi --- include/drm/xe_pciids.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/drm') diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index 84fb596ab8f5..6c3ac3b5ec94 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -163,7 +163,8 @@ XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__) #define XE_ATS_M150_IDS(MACRO__, ...) \ - MACRO__(0x56C0, ## __VA_ARGS__) + MACRO__(0x56C0, ## __VA_ARGS__), \ + MACRO__(0x56C2, ## __VA_ARGS__) #define XE_ATS_M75_IDS(MACRO__, ...) \ MACRO__(0x56C1, ## __VA_ARGS__) -- cgit From 812ec747a354e00f5e789f3cdcfbc80f98f1d71d Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Tue, 21 Nov 2023 11:52:09 -0800 Subject: drm/xe: Sync MTL PCI IDs with i915 For Xe1 platforms, it's better to follow the way i915 adds the PCI IDs to the header, so it's easier to catch up when there is an update. This brings the same logic applied in commit 2e3c369f23a7 ("drm/i915/mtl: Eliminate subplatforms") to the equivalent xe header. The end result of this header for Xe1 platforms is now in sync with i915 as of commit 5032c607e886 ("drm/i915: ATS-M device ID update"). This can be seen by $ git show 5032c607e886:include/drm/i915_pciids.h > a.h $ git diff --color-words --no-index a.h include/drm/xe_pciids.h Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20231121195209.802235-2-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Rodrigo Vivi --- include/drm/xe_pciids.h | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) (limited to 'include/drm') diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index 6c3ac3b5ec94..de1a344737bc 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -173,33 +173,14 @@ XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\ XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) -/* MTL */ -#define XE_MTL_M_IDS(MACRO__, ...) \ +/* MTL / ARL */ +#define XE_MTL_IDS(MACRO__, ...) \ MACRO__(0x7D40, ## __VA_ARGS__), \ - MACRO__(0x7D43, ## __VA_ARGS__), \ - MACRO__(0x7DC0, ## __VA_ARGS__) - -#define XE_MTL_P_IDS(MACRO__, ...) \ MACRO__(0x7D45, ## __VA_ARGS__), \ - MACRO__(0x7D47, ## __VA_ARGS__), \ - MACRO__(0x7D50, ## __VA_ARGS__), \ MACRO__(0x7D55, ## __VA_ARGS__), \ - MACRO__(0x7DC5, ## __VA_ARGS__), \ - MACRO__(0x7DD0, ## __VA_ARGS__), \ - MACRO__(0x7DD5, ## __VA_ARGS__) - -#define XE_MTL_S_IDS(MACRO__, ...) \ MACRO__(0x7D60, ## __VA_ARGS__), \ - MACRO__(0x7DE0, ## __VA_ARGS__) - -#define XE_ARL_IDS(MACRO__, ...) \ - MACRO__(0x7D67, ## __VA_ARGS__) - -#define XE_MTL_IDS(MACRO__, ...) \ - XE_MTL_M_IDS(MACRO__, ## __VA_ARGS__), \ - XE_MTL_P_IDS(MACRO__, ## __VA_ARGS__), \ - XE_MTL_S_IDS(MACRO__, ## __VA_ARGS__), \ - XE_ARL_IDS(MACRO__, ## __VA_ARGS__) + MACRO__(0x7D67, ## __VA_ARGS__), \ + MACRO__(0x7DD5, ## __VA_ARGS__) #define XE_LNL_IDS(MACRO__, ...) \ MACRO__(0x6420, ## __VA_ARGS__), \ -- cgit