From e654df7a1a4843429b5d1d6ee40cac9ecef75304 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Thu, 12 Feb 2015 14:01:30 +0800 Subject: ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the ipg clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk - the APB clock signal . In order to gate/ungate the ipg clock, this patch adds a new shared clock gate named as "mipi_ipg". Signed-off-by: Liu Ying Signed-off-by: Shawn Guo --- include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings/clock') diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index dbc828c23a17..8780868458a0 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -250,6 +250,7 @@ #define IMX6QDL_CLK_GPT_3M 237 #define IMX6QDL_CLK_VIDEO_27M 238 #define IMX6QDL_CLK_MIPI_CORE_CFG 239 -#define IMX6QDL_CLK_END 240 +#define IMX6QDL_CLK_MIPI_IPG 240 +#define IMX6QDL_CLK_END 241 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ -- cgit