From 4c5773f9f5462dcb372857813918bbfe8c0cdcdd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 28 May 2016 11:54:12 +0200 Subject: dt-bindings: clock: Add license and reformat Exynos5410 clock IDs Add license and copyrights (file introduced in 2014) to header with Exynos5410 clock IDs. Additionally reformat it to improve readability. Signed-off-by: Krzysztof Kozlowski Acked-by: Stephen Boyd Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5410.h | 54 ++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 22 deletions(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 9b180f032e2d..213f19e02870 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -1,33 +1,43 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Exynos5421 clock controller. +*/ + #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H /* core clocks */ -#define CLK_FIN_PLL 1 -#define CLK_FOUT_APLL 2 -#define CLK_FOUT_CPLL 3 -#define CLK_FOUT_MPLL 4 -#define CLK_FOUT_BPLL 5 -#define CLK_FOUT_KPLL 6 +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_CPLL 3 +#define CLK_FOUT_MPLL 4 +#define CLK_FOUT_BPLL 5 +#define CLK_FOUT_KPLL 6 /* gate for special clocks (sclk) */ -#define CLK_SCLK_UART0 128 -#define CLK_SCLK_UART1 129 -#define CLK_SCLK_UART2 130 -#define CLK_SCLK_UART3 131 -#define CLK_SCLK_MMC0 132 -#define CLK_SCLK_MMC1 133 -#define CLK_SCLK_MMC2 134 +#define CLK_SCLK_UART0 128 +#define CLK_SCLK_UART1 129 +#define CLK_SCLK_UART2 130 +#define CLK_SCLK_UART3 131 +#define CLK_SCLK_MMC0 132 +#define CLK_SCLK_MMC1 133 +#define CLK_SCLK_MMC2 134 /* gate clocks */ -#define CLK_UART0 257 -#define CLK_UART1 258 -#define CLK_UART2 259 -#define CLK_UART3 260 -#define CLK_MCT 315 -#define CLK_MMC0 351 -#define CLK_MMC1 352 -#define CLK_MMC2 353 +#define CLK_UART0 257 +#define CLK_UART1 258 +#define CLK_UART2 259 +#define CLK_UART3 260 +#define CLK_MCT 315 +#define CLK_MMC0 351 +#define CLK_MMC1 352 +#define CLK_MMC2 353 -#define CLK_NR_CLKS 512 +#define CLK_NR_CLKS 512 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ -- cgit From 5cd3535a27a7cf8fc4070b499d66e419e7e72b61 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 28 May 2016 11:54:13 +0200 Subject: dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410 Add IDs for PWM and USB clocks to Exynos5410. Use the same number as for Exynos5420 just in case in future these drivers were merged. Signed-off-by: Krzysztof Kozlowski Acked-by: Stephen Boyd Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5410.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 213f19e02870..34c8e96987a1 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Copyright (c) 2016 Krzysztof Kozlowski * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -27,16 +28,25 @@ #define CLK_SCLK_MMC0 132 #define CLK_SCLK_MMC1 133 #define CLK_SCLK_MMC2 134 +#define CLK_SCLK_USBD300 150 +#define CLK_SCLK_USBD301 151 +#define CLK_SCLK_USBPHY300 152 +#define CLK_SCLK_USBPHY301 153 +#define CLK_SCLK_PWM 155 /* gate clocks */ #define CLK_UART0 257 #define CLK_UART1 258 #define CLK_UART2 259 #define CLK_UART3 260 +#define CLK_PWM 279 #define CLK_MCT 315 #define CLK_MMC0 351 #define CLK_MMC1 352 #define CLK_MMC2 353 +#define CLK_USBH20 365 +#define CLK_USBD300 366 +#define CLK_USBD301 367 #define CLK_NR_CLKS 512 -- cgit From ed1e1505db0c116affdfab01e650c44a9c459c65 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 28 May 2016 11:54:29 +0200 Subject: dt-bindings: clock: Add I2C, HSI2C and RTC clock IDs to Exynos5410 Add IDs for I2C, USI (HSI2C) and RTC clocks to Exynos5410. Use the same number as for Exynos5420 just in case in future these drivers are merged. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5410.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 34c8e96987a1..e94b7bbfd6af 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -38,9 +38,18 @@ #define CLK_UART0 257 #define CLK_UART1 258 #define CLK_UART2 259 +#define CLK_I2C0 261 +#define CLK_I2C1 262 +#define CLK_I2C2 263 +#define CLK_I2C3 264 +#define CLK_USI0 265 +#define CLK_USI1 266 +#define CLK_USI2 267 +#define CLK_USI3 268 #define CLK_UART3 260 #define CLK_PWM 279 #define CLK_MCT 315 +#define CLK_RTC 317 #define CLK_MMC0 351 #define CLK_MMC1 352 #define CLK_MMC2 353 -- cgit From 109869f522852094393b829918b56327c0feb360 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 May 2016 20:39:00 +0200 Subject: dt-bindings: clock: Add TMU clock ID to Exynos5410 Add ID for TMU clock to Exynos5410. Use the same number as for Exynos5420 just in case in future these drivers were merged. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5410.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index e94b7bbfd6af..705b2aa84317 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -50,6 +50,7 @@ #define CLK_PWM 279 #define CLK_MCT 315 #define CLK_RTC 317 +#define CLK_TMU 318 #define CLK_MMC0 351 #define CLK_MMC1 352 #define CLK_MMC2 353 -- cgit From 4528dd8ed477bf202bd33ee48d38d656672d37f8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Jun 2016 11:45:49 +0200 Subject: dt-bindings: clock: Add watchdog and SSS clock IDs to Exynos5410 Add IDs for watchdog and Security SubSystem to Exynos5410. Use the same number as for Exynos5420 just in case in future these drivers were merged. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5410.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 705b2aa84317..85b467b3a207 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -49,6 +49,7 @@ #define CLK_UART3 260 #define CLK_PWM 279 #define CLK_MCT 315 +#define CLK_WDT 316 #define CLK_RTC 317 #define CLK_TMU 318 #define CLK_MMC0 351 @@ -57,6 +58,7 @@ #define CLK_USBH20 365 #define CLK_USBD300 366 #define CLK_USBD301 367 +#define CLK_SSS 471 #define CLK_NR_CLKS 512 -- cgit From 972610fb23b08dd54879102a9d5be695d53b728b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 May 2016 14:36:32 +0200 Subject: clk: renesas: Add r8a7796 CPG Core Clock Definitions Add all R-Car M3-W Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2b ("List of Clocks [R-Car M3-W]") of the R-Car Gen3 datasheet (rev. 0.51 + Errata for Rev051 Mar 31 2016). Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, and SSPSRC) are not included, as they are used as internal clock sources only, and never referenced from DT. Signed-off-by: Geert Uytterhoeven Tested-by: Simon Horman --- include/dt-bindings/clock/r8a7796-cpg-mssr.h | 69 ++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 include/dt-bindings/clock/r8a7796-cpg-mssr.h (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h new file mode 100644 index 000000000000..1e5942695f0d --- /dev/null +++ b/include/dt-bindings/clock/r8a7796-cpg-mssr.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ + +#include + +/* r8a7796 CPG Core Clocks */ +#define R8A7796_CLK_Z 0 +#define R8A7796_CLK_Z2 1 +#define R8A7796_CLK_ZR 2 +#define R8A7796_CLK_ZG 3 +#define R8A7796_CLK_ZTR 4 +#define R8A7796_CLK_ZTRD2 5 +#define R8A7796_CLK_ZT 6 +#define R8A7796_CLK_ZX 7 +#define R8A7796_CLK_S0D1 8 +#define R8A7796_CLK_S0D2 9 +#define R8A7796_CLK_S0D3 10 +#define R8A7796_CLK_S0D4 11 +#define R8A7796_CLK_S0D6 12 +#define R8A7796_CLK_S0D8 13 +#define R8A7796_CLK_S0D12 14 +#define R8A7796_CLK_S1D1 15 +#define R8A7796_CLK_S1D2 16 +#define R8A7796_CLK_S1D4 17 +#define R8A7796_CLK_S2D1 18 +#define R8A7796_CLK_S2D2 19 +#define R8A7796_CLK_S2D4 20 +#define R8A7796_CLK_S3D1 21 +#define R8A7796_CLK_S3D2 22 +#define R8A7796_CLK_S3D4 23 +#define R8A7796_CLK_LB 24 +#define R8A7796_CLK_CL 25 +#define R8A7796_CLK_ZB3 26 +#define R8A7796_CLK_ZB3D2 27 +#define R8A7796_CLK_ZB3D4 28 +#define R8A7796_CLK_CR 29 +#define R8A7796_CLK_CRD2 30 +#define R8A7796_CLK_SD0H 31 +#define R8A7796_CLK_SD0 32 +#define R8A7796_CLK_SD1H 33 +#define R8A7796_CLK_SD1 34 +#define R8A7796_CLK_SD2H 35 +#define R8A7796_CLK_SD2 36 +#define R8A7796_CLK_SD3H 37 +#define R8A7796_CLK_SD3 38 +#define R8A7796_CLK_SSP2 39 +#define R8A7796_CLK_SSP1 40 +#define R8A7796_CLK_SSPRS 41 +#define R8A7796_CLK_RPC 42 +#define R8A7796_CLK_RPCD2 43 +#define R8A7796_CLK_MSO 44 +#define R8A7796_CLK_CANFD 45 +#define R8A7796_CLK_HDMI 46 +#define R8A7796_CLK_CSI0 47 +#define R8A7796_CLK_CSIREF 48 +#define R8A7796_CLK_CP 49 +#define R8A7796_CLK_CPEX 50 +#define R8A7796_CLK_R 51 +#define R8A7796_CLK_OSC 52 + +#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ -- cgit From 0e4504470667d355b53ca3c9802fdd2120c9f946 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 10 Jun 2016 13:56:32 +0900 Subject: clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device This patch adds the CLK_IGNORE_UNUSED flag for PCI Express's clocks which need to remain enabled. The 'pcie' gate clock definition is also added. Signed-off-by: Jaehoon Chung Signed-off-by: Chanwoo Choi [s.nawrocki@samsung.com: edited the patch's summary] Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5433.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 8e024fea26e7..4fa6bb2136e3 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -622,8 +622,9 @@ #define CLK_SCLK_UFSUNIPRO 112 #define CLK_SCLK_USBHOST30 113 #define CLK_SCLK_USBDRD30 114 +#define CLK_PCIE 115 -#define FSYS_NR_CLK 115 +#define FSYS_NR_CLK 116 /* CMU_G2D */ #define CLK_MUX_ACLK_G2D_266_USER 1 -- cgit From e452b818db48dc2c7edb5afd62de47ae0363aec2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 9 Jun 2016 17:47:17 +0200 Subject: clk: tegra: Enable sor1 and sor1_src on Tegra210 Make the sor1 and sor1_src clocks available on Tegra210. They will be used by the display driver to support HDMI and DP. Signed-off-by: Thierry Reding --- include/dt-bindings/clock/tegra210-car.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index bd3530e56d46..35288b20f2c9 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -308,7 +308,7 @@ #define TEGRA210_CLK_CLK_OUT_3 279 #define TEGRA210_CLK_BLINK 280 /* 281 */ -/* 282 */ +#define TEGRA210_CLK_SOR1_SRC 282 /* 283 */ #define TEGRA210_CLK_XUSB_HOST_SRC 284 #define TEGRA210_CLK_XUSB_FALCON_SRC 285 -- cgit From 5f6d71044f4d766c3636b9fd2c43e7c9d71d31af Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Tue, 21 Jun 2016 12:53:29 +0800 Subject: clk: rockchip: add clock-ids for rk3228 audio clocks This patch exports related i2s/spdif clocks for dts reference. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3228-cru.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 5d43ed9b05ad..c992f3e50e25 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -84,6 +84,10 @@ #define PCLK_HDMI_PHY 365 /* hclk gates */ +#define HCLK_I2S0_8CH 442 +#define HCLK_I2S1_8CH 443 +#define HCLK_I2S2_2CH 444 +#define HCLK_SPDIF_8CH 445 #define HCLK_VOP 452 #define HCLK_NANDC 453 #define HCLK_SDMMC 456 -- cgit From 9ff59360b863706b50cbcd7ffad9287d67254063 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Tue, 21 Jun 2016 12:59:47 +0800 Subject: clk: rockchip: add clock-ids for rk3228 MAC clocks This patch exports related MAC clocks for dts reference. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3228-cru.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index c992f3e50e25..b27e2b1a65e3 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -52,6 +52,15 @@ #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC_EXTCLK 125 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_MAC_PHY 131 +#define SCLK_MAC_OUT 132 /* dclk gates */ #define DCLK_VOP 190 @@ -61,6 +70,7 @@ #define ACLK_DMAC 194 #define ACLK_PERI 210 #define ACLK_VOP 211 +#define ACLK_GMAC 212 /* pclk gates */ #define PCLK_GPIO0 320 @@ -82,6 +92,7 @@ #define PCLK_PERI 363 #define PCLK_HDMI_CTRL 364 #define PCLK_HDMI_PHY 365 +#define PCLK_GMAC 367 /* hclk gates */ #define HCLK_I2S0_8CH 442 -- cgit From c0daa3e6f5b0b707f5c4b408bc8ef541c9a7742a Mon Sep 17 00:00:00 2001 From: Michael Turquette Date: Thu, 28 Apr 2016 12:01:51 -0700 Subject: clk: meson8b: clean up composite clocks Remove the composite clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. To preserve git bisect this patch also flips the switch and starts using of_clk_add_hw_provider instead of the deprecated meson_clk_register_clks method. As a byproduct clk.c can be deleted. Tested-by: Kevin Hilman Signed-off-by: Michael Turquette --- include/dt-bindings/clock/meson8b-clkc.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index bd2720d58e0c..595a58d0969a 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -19,7 +19,9 @@ #define CLKID_MALI 11 #define CLKID_CPUCLK 12 #define CLKID_ZERO 13 +#define CLKID_MPEG_SEL 14 +#define CLKID_MPEG_DIV 15 -#define CLK_NR_CLKS (CLKID_ZERO + 1) +#define CLK_NR_CLKS (CLKID_MPEG_DIV + 1) #endif /* __MESON8B_CLKC_H */ -- cgit From 738f66d3211d7ae0cd0012ba6457dac9a03bfd6b Mon Sep 17 00:00:00 2001 From: Michael Turquette Date: Mon, 23 May 2016 15:44:26 -0700 Subject: clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman Signed-off-by: Michael Turquette --- include/dt-bindings/clock/gxbb-clkc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/clock/gxbb-clkc.h (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h new file mode 100644 index 000000000000..f889d80246cb --- /dev/null +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -0,0 +1,12 @@ +/* + * GXBB clock tree IDs + */ + +#ifndef __GXBB_CLKC_H +#define __GXBB_CLKC_H + +#define CLKID_CPUCLK 1 +#define CLKID_CLK81 12 +#define CLKID_ETH 36 + +#endif /* __GXBB_CLKC_H */ -- cgit From 6fb924dc9c482557ebd41f6c6a5fde34210a2e08 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 29 Jun 2016 17:48:44 -0700 Subject: clk: hi6220: Add RTC clock for pl031 Adds clk support for the pl031 RTC on hi6220 Cc: Michael Turquette Cc: Stephen Boyd Cc: Rob Herring Cc: Pawel Moll Cc: Wei Xu Cc: Guodong Xu Signed-off-by: Zhangfei Gao [jstultz: Forward ported, tweaked commit description] Signed-off-by: John Stultz Signed-off-by: Stephen Boyd --- include/dt-bindings/clock/hi6220-clock.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h index 70ee3833a7a0..6b03c84f4278 100644 --- a/include/dt-bindings/clock/hi6220-clock.h +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -55,8 +55,9 @@ #define HI6220_TIMER7_PCLK 34 #define HI6220_TIMER8_PCLK 35 #define HI6220_UART0_PCLK 36 - -#define HI6220_AO_NR_CLKS 37 +#define HI6220_RTC0_PCLK 37 +#define HI6220_RTC1_PCLK 38 +#define HI6220_AO_NR_CLKS 39 /* clk in Hi6220 systrl */ /* gate clock */ -- cgit From 054e2730088a9c9340b5bc6927000f5c14a8b6d7 Mon Sep 17 00:00:00 2001 From: Sylvain Lemieux Date: Fri, 3 Jun 2016 15:34:35 -0400 Subject: clk: lpc32xx: allow peripheral clock selection in device tree This patch add the support to select the peripheral clock (PERIPH) as a parent clock source using the "assigned-clock-parents" parameter in the device tree. Signed-off-by: Sylvain Lemieux Acked-by: Vladimir Zapolskiy Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/1464982475-24738-1-git-send-email-slemieux.tyco@gmail.com --- include/dt-bindings/clock/lpc32xx-clock.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h index d41b6fea1450..e624d3a52798 100644 --- a/include/dt-bindings/clock/lpc32xx-clock.h +++ b/include/dt-bindings/clock/lpc32xx-clock.h @@ -48,6 +48,7 @@ #define LPC32XX_CLK_PWM2 33 #define LPC32XX_CLK_ADC 34 #define LPC32XX_CLK_HCLK_PLL 35 +#define LPC32XX_CLK_PERIPH 36 /* LPC32XX USB clocks */ #define LPC32XX_USB_CLK_I2C 1 -- cgit From e16fb2e6355c1c1b41623af9e01ada196e2af098 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 6 Jul 2016 20:38:37 -0700 Subject: clk: gxbb: expose CLKID_MMC_PCLK The MMC_PCLK is needed for the SD/eMMC driver, expose to DT (and comment out in clk driver) Signed-off-by: Kevin Hilman Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/20160707033837.20029-1-khilman@baylibre.com --- include/dt-bindings/clock/gxbb-clkc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index f889d80246cb..5eb69ec74f6b 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -8,5 +8,6 @@ #define CLKID_CPUCLK 1 #define CLKID_CLK81 12 #define CLKID_ETH 36 +#define CLKID_MMC_PCLK 66 #endif /* __GXBB_CLKC_H */ -- cgit From 0577e4853bfb4c65f620fa56d3157692df7f766e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 29 Jun 2016 21:05:34 +0200 Subject: clk: sunxi-ng: Add H3 clocks Add the list of clocks and resets found in the H3 CCU. Signed-off-by: Maxime Ripard Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/20160629190535.11855-14-maxime.ripard@free-electrons.com --- include/dt-bindings/clock/sun8i-h3-ccu.h | 145 +++++++++++++++++++++++++++++++ include/dt-bindings/reset/sun8i-h3-ccu.h | 103 ++++++++++++++++++++++ 2 files changed, 248 insertions(+) create mode 100644 include/dt-bindings/clock/sun8i-h3-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-h3-ccu.h (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h new file mode 100644 index 000000000000..efb7ba2bd515 --- /dev/null +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ +#define _DT_BINDINGS_CLK_SUN8I_H3_H_ + +#define CLK_CPUX 14 + +#define CLK_BUS_CE 20 +#define CLK_BUS_DMA 21 +#define CLK_BUS_MMC0 22 +#define CLK_BUS_MMC1 23 +#define CLK_BUS_MMC2 24 +#define CLK_BUS_NAND 25 +#define CLK_BUS_DRAM 26 +#define CLK_BUS_EMAC 27 +#define CLK_BUS_TS 28 +#define CLK_BUS_HSTIMER 29 +#define CLK_BUS_SPI0 30 +#define CLK_BUS_SPI1 31 +#define CLK_BUS_OTG 32 +#define CLK_BUS_EHCI0 33 +#define CLK_BUS_EHCI1 34 +#define CLK_BUS_EHCI2 35 +#define CLK_BUS_EHCI3 36 +#define CLK_BUS_OHCI0 37 +#define CLK_BUS_OHCI1 38 +#define CLK_BUS_OHCI2 39 +#define CLK_BUS_OHCI3 40 +#define CLK_BUS_VE 41 +#define CLK_BUS_TCON0 42 +#define CLK_BUS_TCON1 43 +#define CLK_BUS_DEINTERLACE 44 +#define CLK_BUS_CSI 45 +#define CLK_BUS_TVE 46 +#define CLK_BUS_HDMI 47 +#define CLK_BUS_DE 48 +#define CLK_BUS_GPU 49 +#define CLK_BUS_MSGBOX 50 +#define CLK_BUS_SPINLOCK 51 +#define CLK_BUS_CODEC 52 +#define CLK_BUS_SPDIF 53 +#define CLK_BUS_PIO 54 +#define CLK_BUS_THS 55 +#define CLK_BUS_I2S0 56 +#define CLK_BUS_I2S1 57 +#define CLK_BUS_I2S2 58 +#define CLK_BUS_I2C0 59 +#define CLK_BUS_I2C1 60 +#define CLK_BUS_I2C2 61 +#define CLK_BUS_UART0 62 +#define CLK_BUS_UART1 63 +#define CLK_BUS_UART2 64 +#define CLK_BUS_UART3 65 +#define CLK_BUS_SCR 66 +#define CLK_BUS_EPHY 67 +#define CLK_BUS_DBG 68 + +#define CLK_THS 69 +#define CLK_NAND 70 +#define CLK_MMC0 71 +#define CLK_MMC0_SAMPLE 72 +#define CLK_MMC0_OUTPUT 73 +#define CLK_MMC1 74 +#define CLK_MMC1_SAMPLE 75 +#define CLK_MMC1_OUTPUT 76 +#define CLK_MMC2 77 +#define CLK_MMC2_SAMPLE 78 +#define CLK_MMC2_OUTPUT 79 +#define CLK_TS 80 +#define CLK_CE 81 +#define CLK_SPI0 82 +#define CLK_SPI1 83 +#define CLK_I2S0 84 +#define CLK_I2S1 85 +#define CLK_I2S2 86 +#define CLK_SPDIF 87 +#define CLK_USB_PHY0 88 +#define CLK_USB_PHY1 89 +#define CLK_USB_PHY2 90 +#define CLK_USB_PHY3 91 +#define CLK_USB_OHCI0 92 +#define CLK_USB_OHCI1 93 +#define CLK_USB_OHCI2 94 +#define CLK_USB_OHCI3 95 + +#define CLK_DRAM_VE 97 +#define CLK_DRAM_CSI 98 +#define CLK_DRAM_DEINTERLACE 99 +#define CLK_DRAM_TS 100 +#define CLK_DE 101 +#define CLK_TCON0 102 +#define CLK_TVE 103 +#define CLK_DEINTERLACE 104 +#define CLK_CSI_MISC 105 +#define CLK_CSI_SCLK 106 +#define CLK_CSI_MCLK 107 +#define CLK_VE 108 +#define CLK_AC_DIG 109 +#define CLK_AVS 110 +#define CLK_HDMI 111 +#define CLK_HDMI_DDC 112 + +#define CLK_GPU 114 + +#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h new file mode 100644 index 000000000000..6b7af80c26ec --- /dev/null +++ b/include/dt-bindings/reset/sun8i-h3-ccu.h @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_ +#define _DT_BINDINGS_RST_SUN8I_H3_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_PHY2 2 +#define RST_USB_PHY3 3 + +#define RST_MBUS 4 + +#define RST_BUS_CE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MMC0 7 +#define RST_BUS_MMC1 8 +#define RST_BUS_MMC2 9 +#define RST_BUS_NAND 10 +#define RST_BUS_DRAM 11 +#define RST_BUS_EMAC 12 +#define RST_BUS_TS 13 +#define RST_BUS_HSTIMER 14 +#define RST_BUS_SPI0 15 +#define RST_BUS_SPI1 16 +#define RST_BUS_OTG 17 +#define RST_BUS_EHCI0 18 +#define RST_BUS_EHCI1 19 +#define RST_BUS_EHCI2 20 +#define RST_BUS_EHCI3 21 +#define RST_BUS_OHCI0 22 +#define RST_BUS_OHCI1 23 +#define RST_BUS_OHCI2 24 +#define RST_BUS_OHCI3 25 +#define RST_BUS_VE 26 +#define RST_BUS_TCON0 27 +#define RST_BUS_TCON1 28 +#define RST_BUS_DEINTERLACE 29 +#define RST_BUS_CSI 30 +#define RST_BUS_TVE 31 +#define RST_BUS_HDMI0 32 +#define RST_BUS_HDMI1 33 +#define RST_BUS_DE 34 +#define RST_BUS_GPU 35 +#define RST_BUS_MSGBOX 36 +#define RST_BUS_SPINLOCK 37 +#define RST_BUS_DBG 38 +#define RST_BUS_EPHY 39 +#define RST_BUS_CODEC 40 +#define RST_BUS_SPDIF 41 +#define RST_BUS_THS 42 +#define RST_BUS_I2S0 43 +#define RST_BUS_I2S1 44 +#define RST_BUS_I2S2 45 +#define RST_BUS_I2C0 46 +#define RST_BUS_I2C1 47 +#define RST_BUS_I2C2 48 +#define RST_BUS_UART0 49 +#define RST_BUS_UART1 50 +#define RST_BUS_UART2 51 +#define RST_BUS_UART3 52 +#define RST_BUS_SCR 53 + +#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ -- cgit From ca1d2e269f593b318a75f3ffb9befc1ec8b6f2fd Mon Sep 17 00:00:00 2001 From: Michael Turquette Date: Fri, 15 Jul 2016 19:13:36 -0700 Subject: Revert "clk: gxbb: expose CLKID_MMC_PCLK" This reverts commit e16fb2e6355c1c1b41623af9e01ada196e2af098. Updated documentation from the chip vendor reveals that this clock is not required for correct operation of the MMC controller. As such, do not expose it to DT. Signed-off-by: Michael Turquette --- include/dt-bindings/clock/gxbb-clkc.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index 5eb69ec74f6b..f889d80246cb 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -8,6 +8,5 @@ #define CLKID_CPUCLK 1 #define CLKID_CLK81 12 #define CLKID_ETH 36 -#define CLKID_MMC_PCLK 66 #endif /* __GXBB_CLKC_H */ -- cgit