From 20ccb993f29bd6ad17699dd0b349db086e3ca719 Mon Sep 17 00:00:00 2001 From: "Bean Huo (beanhuo)" Date: Mon, 4 Dec 2017 12:34:47 +0000 Subject: mtd: spi-nor: check FSR error bits for Micron memories For Micron spi nor device, when erase/program operation fails, especially the failure results from intending to modify protected space, spi-nor upper layers still get the return which shows the operation succeeds. This is because current spi_nor_fsr_ready() only uses FSR bit.7 (flag status register) to check device whether ready. This patch fixes this issue by checking relevant error bits in FSR. The FSR is a powerful tool to investigate the status of device, checking information regarding what the memory is actually doing and detecting possible error conditions. Signed-off-by: beanhuo Signed-off-by: Cyrille Pitchen --- include/linux/mtd/spi-nor.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include/linux/mtd') diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d0c66a0975cf..c0836cca5280 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -61,6 +61,7 @@ #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ +#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ @@ -130,7 +131,10 @@ #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ /* Flag Status Register bits */ -#define FSR_READY BIT(7) +#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ +#define FSR_E_ERR BIT(5) /* Erase operation status */ +#define FSR_P_ERR BIT(4) /* Program operation status */ +#define FSR_PT_ERR BIT(1) /* Protection error bit */ /* Configuration Register bits. */ #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ -- cgit