From a8f9a36e46344ea5bdc301c2fde0389a463bf0a3 Mon Sep 17 00:00:00 2001 From: "Bao D. Nguyen" Date: Mon, 29 May 2023 15:12:20 -0700 Subject: scsi: ufs: core: Combine 32-bit command_desc_base_addr_lo/hi The UTP command descriptor base address is a 57-bit field in the UTP transfer request descriptor. Combine the two 32-bit command_desc_base_addr_lo/hi fields into a 64-bit for better handling of this field. Signed-off-by: Bao D. Nguyen Link: https://lore.kernel.org/r/4e6f7f5a15000cdae77c3014b477264f57bf572c.1685396241.git.quic_nguyenb@quicinc.com Reviewed-by: Bart Van Assche Reviewed-by: Stanley Chu Tested-by: Stanley Chu Reviewed-by: Can Guo Signed-off-by: Martin K. Petersen --- include/ufs/ufshci.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'include/ufs') diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h index 11424bb03814..7c5a76b2c70a 100644 --- a/include/ufs/ufshci.h +++ b/include/ufs/ufshci.h @@ -503,8 +503,7 @@ struct request_desc_header { /** * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD) * @header: UTRD header DW-0 to DW-3 - * @command_desc_base_addr_lo: UCD base address low DW-4 - * @command_desc_base_addr_hi: UCD base address high DW-5 + * @command_desc_base_addr: UCD base address DW 4-5 * @response_upiu_length: response UPIU length DW-6 * @response_upiu_offset: response UPIU offset DW-6 * @prd_table_length: Physical region descriptor length DW-7 @@ -516,8 +515,7 @@ struct utp_transfer_req_desc { struct request_desc_header header; /* DW 4-5*/ - __le32 command_desc_base_addr_lo; - __le32 command_desc_base_addr_hi; + __le64 command_desc_base_addr; /* DW 6 */ __le16 response_upiu_length; -- cgit From 8d7290348992f27242dd6a696fa2eede709f0b14 Mon Sep 17 00:00:00 2001 From: "Bao D. Nguyen" Date: Mon, 29 May 2023 15:12:22 -0700 Subject: scsi: ufs: mcq: Add supporting functions for MCQ abort Add supporting functions to handle UFS abort in MCQ mode. Signed-off-by: Bao D. Nguyen Link: https://lore.kernel.org/r/d452c5ad62dc863cc067ec82daa0885ec98bd508.1685396241.git.quic_nguyenb@quicinc.com Reviewed-by: Bart Van Assche Reviewed-by: Stanley Chu Tested-by: Stanley Chu Reviewed-by: Can Guo Signed-off-by: Martin K. Petersen --- include/ufs/ufshcd.h | 3 +++ include/ufs/ufshci.h | 17 +++++++++++++++++ 2 files changed, 20 insertions(+) (limited to 'include/ufs') diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index f7553293ba98..145710e9c2a5 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1087,6 +1087,7 @@ struct ufs_hba { * @cq_tail_slot: current slot to which CQ tail pointer is pointing * @cq_head_slot: current slot to which CQ head pointer is pointing * @cq_lock: Synchronize between multiple polling instances + * @sq_mutex: prevent submission queue concurrent access */ struct ufs_hw_queue { void __iomem *mcq_sq_head; @@ -1105,6 +1106,8 @@ struct ufs_hw_queue { u32 cq_tail_slot; u32 cq_head_slot; spinlock_t cq_lock; + /* prevent concurrent access to submission queue */ + struct mutex sq_mutex; }; static inline bool is_mcq_enabled(struct ufs_hba *hba) diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h index 7c5a76b2c70a..9d291ca7f31d 100644 --- a/include/ufs/ufshci.h +++ b/include/ufs/ufshci.h @@ -99,6 +99,9 @@ enum { enum { REG_SQHP = 0x0, REG_SQTP = 0x4, + REG_SQRTC = 0x8, + REG_SQCTI = 0xC, + REG_SQRTS = 0x10, }; enum { @@ -111,12 +114,26 @@ enum { REG_CQIE = 0x4, }; +enum { + SQ_START = 0x0, + SQ_STOP = 0x1, + SQ_ICU = 0x2, +}; + +enum { + SQ_STS = 0x1, + SQ_CUS = 0x2, +}; + +#define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4) +#define UPIU_COMMAND_TYPE_MASK GENMASK(31, 28) #define UFS_MASK(mask, offset) ((mask) << (offset)) /* UFS Version 08h */ #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) +#define UFSHCD_NUM_RESERVED 1 /* * Controller UFSHCI version * - 2.x and newer use the following scheme: -- cgit From 57d6ef4601c0b7975aab5144c7c3760846362e1c Mon Sep 17 00:00:00 2001 From: "Bao D. Nguyen" Date: Mon, 29 May 2023 15:12:25 -0700 Subject: scsi: ufs: mcq: Use ufshcd_mcq_poll_cqe_lock() in MCQ mode In preparation for adding MCQ error handler support, update the MCQ code to use the ufshcd_mcq_poll_cqe_lock() in interrupt context instead of using ufshcd_mcq_poll_cqe_nolock(). This is to keep synchronization between MCQ interrupt and error handler contexts because both need to access the MCQ hardware in separate contexts. Signed-off-by: Bao D. Nguyen Link: https://lore.kernel.org/r/6ae727ad2a4040469b8f0632b55e0577d80da11b.1685396241.git.quic_nguyenb@quicinc.com Reviewed-by: Bart Van Assche Reviewed-by: Stanley Chu Tested-by: Stanley Chu Reviewed-by: Can Guo Signed-off-by: Martin K. Petersen --- include/ufs/ufshcd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/ufs') diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 145710e9c2a5..12e3149617db 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1243,7 +1243,7 @@ void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); void ufshcd_hba_stop(struct ufs_hba *hba); void ufshcd_schedule_eh_work(struct ufs_hba *hba); void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); -unsigned long ufshcd_mcq_poll_cqe_nolock(struct ufs_hba *hba, +unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, struct ufs_hw_queue *hwq); void ufshcd_mcq_enable_esi(struct ufs_hba *hba); void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); -- cgit