From 9859cd3b1582cbe39f969a500d8b7fc87c4b87b8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 16 Nov 2015 17:57:11 +0900 Subject: ARM: shmobile: r8a7794: Add DU0 clock The DU0 clock is an MSTP clock, child of the CPG ZX clock. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- include/dt-bindings/clock/r8a7794-clock.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index 09da38a58776..a7a7e0370968 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -79,6 +79,7 @@ #define R8A7794_CLK_SCIF2 19 #define R8A7794_CLK_SCIF1 20 #define R8A7794_CLK_SCIF0 21 +#define R8A7794_CLK_DU0 24 /* MSTP8 */ #define R8A7794_CLK_VIN1 10 -- cgit From 94af7a3c310f5877dc6f756179b92f24f89a9b08 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 19 Oct 2015 14:00:32 +0900 Subject: clk: samsung: exynos4: Add SSS gate clock Add a gate clock for controlling all clocks of Security Sub System (SSS). Signed-off-by: Krzysztof Kozlowski Acked-by: Stephen Boyd --- include/dt-bindings/clock/exynos4.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index c4b1676ea674..c40111f36d5e 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -93,6 +93,7 @@ #define CLK_SCLK_FIMG2D 177 /* gate clocks */ +#define CLK_SSS 255 #define CLK_FIMC0 256 #define CLK_FIMC1 257 #define CLK_FIMC2 258 -- cgit From 967313e2ec9cb9184e1d6af393c766e87f8eb1fc Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 20 Nov 2015 12:42:44 +0100 Subject: ARM: mediatek: DT: Move reset controller constants into common location By popular vote, the DT binding includes for reset controllers are located in include/dt-bindings/reset/. Move the mediatek reset constants in there, too, to avoid confusion. Signed-off-by: Philipp Zabel Signed-off-by: Matthias Brugger --- .../dt-bindings/reset-controller/mt8135-resets.h | 64 ---------------------- .../dt-bindings/reset-controller/mt8173-resets.h | 63 --------------------- include/dt-bindings/reset/mt8135-resets.h | 64 ++++++++++++++++++++++ include/dt-bindings/reset/mt8173-resets.h | 63 +++++++++++++++++++++ 4 files changed, 127 insertions(+), 127 deletions(-) delete mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h delete mode 100644 include/dt-bindings/reset-controller/mt8173-resets.h create mode 100644 include/dt-bindings/reset/mt8135-resets.h create mode 100644 include/dt-bindings/reset/mt8173-resets.h (limited to 'include') diff --git a/include/dt-bindings/reset-controller/mt8135-resets.h b/include/dt-bindings/reset-controller/mt8135-resets.h deleted file mode 100644 index 1fb629508db2..000000000000 --- a/include/dt-bindings/reset-controller/mt8135-resets.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Flora Fu, MediaTek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8135 - -/* INFRACFG resets */ -#define MT8135_INFRA_EMI_REG_RST 0 -#define MT8135_INFRA_DRAMC0_A0_RST 1 -#define MT8135_INFRA_CCIF0_RST 2 -#define MT8135_INFRA_APCIRQ_EINT_RST 3 -#define MT8135_INFRA_APXGPT_RST 4 -#define MT8135_INFRA_SCPSYS_RST 5 -#define MT8135_INFRA_CCIF1_RST 6 -#define MT8135_INFRA_PMIC_WRAP_RST 7 -#define MT8135_INFRA_KP_RST 8 -#define MT8135_INFRA_EMI_RST 32 -#define MT8135_INFRA_DRAMC0_RST 34 -#define MT8135_INFRA_SMI_RST 35 -#define MT8135_INFRA_M4U_RST 36 - -/* PERICFG resets */ -#define MT8135_PERI_UART0_SW_RST 0 -#define MT8135_PERI_UART1_SW_RST 1 -#define MT8135_PERI_UART2_SW_RST 2 -#define MT8135_PERI_UART3_SW_RST 3 -#define MT8135_PERI_IRDA_SW_RST 4 -#define MT8135_PERI_PTP_SW_RST 5 -#define MT8135_PERI_AP_HIF_SW_RST 6 -#define MT8135_PERI_GPCU_SW_RST 7 -#define MT8135_PERI_MD_HIF_SW_RST 8 -#define MT8135_PERI_NLI_SW_RST 9 -#define MT8135_PERI_AUXADC_SW_RST 10 -#define MT8135_PERI_DMA_SW_RST 11 -#define MT8135_PERI_NFI_SW_RST 14 -#define MT8135_PERI_PWM_SW_RST 15 -#define MT8135_PERI_THERM_SW_RST 16 -#define MT8135_PERI_MSDC0_SW_RST 17 -#define MT8135_PERI_MSDC1_SW_RST 18 -#define MT8135_PERI_MSDC2_SW_RST 19 -#define MT8135_PERI_MSDC3_SW_RST 20 -#define MT8135_PERI_I2C0_SW_RST 22 -#define MT8135_PERI_I2C1_SW_RST 23 -#define MT8135_PERI_I2C2_SW_RST 24 -#define MT8135_PERI_I2C3_SW_RST 25 -#define MT8135_PERI_I2C4_SW_RST 26 -#define MT8135_PERI_I2C5_SW_RST 27 -#define MT8135_PERI_I2C6_SW_RST 28 -#define MT8135_PERI_USB_SW_RST 29 -#define MT8135_PERI_SPI1_SW_RST 33 -#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ diff --git a/include/dt-bindings/reset-controller/mt8173-resets.h b/include/dt-bindings/reset-controller/mt8173-resets.h deleted file mode 100644 index 9464b37cf68c..000000000000 --- a/include/dt-bindings/reset-controller/mt8173-resets.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Flora Fu, MediaTek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8173 - -/* INFRACFG resets */ -#define MT8173_INFRA_EMI_REG_RST 0 -#define MT8173_INFRA_DRAMC0_A0_RST 1 -#define MT8173_INFRA_APCIRQ_EINT_RST 3 -#define MT8173_INFRA_APXGPT_RST 4 -#define MT8173_INFRA_SCPSYS_RST 5 -#define MT8173_INFRA_KP_RST 6 -#define MT8173_INFRA_PMIC_WRAP_RST 7 -#define MT8173_INFRA_MPIP_RST 8 -#define MT8173_INFRA_CEC_RST 9 -#define MT8173_INFRA_EMI_RST 32 -#define MT8173_INFRA_DRAMC0_RST 34 -#define MT8173_INFRA_APMIXEDSYS_RST 35 -#define MT8173_INFRA_MIPI_DSI_RST 36 -#define MT8173_INFRA_TRNG_RST 37 -#define MT8173_INFRA_SYSIRQ_RST 38 -#define MT8173_INFRA_MIPI_CSI_RST 39 -#define MT8173_INFRA_GCE_FAXI_RST 40 -#define MT8173_INFRA_MMIOMMURST 47 - - -/* PERICFG resets */ -#define MT8173_PERI_UART0_SW_RST 0 -#define MT8173_PERI_UART1_SW_RST 1 -#define MT8173_PERI_UART2_SW_RST 2 -#define MT8173_PERI_UART3_SW_RST 3 -#define MT8173_PERI_IRRX_SW_RST 4 -#define MT8173_PERI_PWM_SW_RST 8 -#define MT8173_PERI_AUXADC_SW_RST 10 -#define MT8173_PERI_DMA_SW_RST 11 -#define MT8173_PERI_I2C6_SW_RST 13 -#define MT8173_PERI_NFI_SW_RST 14 -#define MT8173_PERI_THERM_SW_RST 16 -#define MT8173_PERI_MSDC2_SW_RST 17 -#define MT8173_PERI_MSDC3_SW_RST 18 -#define MT8173_PERI_MSDC0_SW_RST 19 -#define MT8173_PERI_MSDC1_SW_RST 20 -#define MT8173_PERI_I2C0_SW_RST 22 -#define MT8173_PERI_I2C1_SW_RST 23 -#define MT8173_PERI_I2C2_SW_RST 24 -#define MT8173_PERI_I2C3_SW_RST 25 -#define MT8173_PERI_I2C4_SW_RST 26 -#define MT8173_PERI_HDMI_SW_RST 29 -#define MT8173_PERI_SPI0_SW_RST 33 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ diff --git a/include/dt-bindings/reset/mt8135-resets.h b/include/dt-bindings/reset/mt8135-resets.h new file mode 100644 index 000000000000..1fb629508db2 --- /dev/null +++ b/include/dt-bindings/reset/mt8135-resets.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Flora Fu, MediaTek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8135 + +/* INFRACFG resets */ +#define MT8135_INFRA_EMI_REG_RST 0 +#define MT8135_INFRA_DRAMC0_A0_RST 1 +#define MT8135_INFRA_CCIF0_RST 2 +#define MT8135_INFRA_APCIRQ_EINT_RST 3 +#define MT8135_INFRA_APXGPT_RST 4 +#define MT8135_INFRA_SCPSYS_RST 5 +#define MT8135_INFRA_CCIF1_RST 6 +#define MT8135_INFRA_PMIC_WRAP_RST 7 +#define MT8135_INFRA_KP_RST 8 +#define MT8135_INFRA_EMI_RST 32 +#define MT8135_INFRA_DRAMC0_RST 34 +#define MT8135_INFRA_SMI_RST 35 +#define MT8135_INFRA_M4U_RST 36 + +/* PERICFG resets */ +#define MT8135_PERI_UART0_SW_RST 0 +#define MT8135_PERI_UART1_SW_RST 1 +#define MT8135_PERI_UART2_SW_RST 2 +#define MT8135_PERI_UART3_SW_RST 3 +#define MT8135_PERI_IRDA_SW_RST 4 +#define MT8135_PERI_PTP_SW_RST 5 +#define MT8135_PERI_AP_HIF_SW_RST 6 +#define MT8135_PERI_GPCU_SW_RST 7 +#define MT8135_PERI_MD_HIF_SW_RST 8 +#define MT8135_PERI_NLI_SW_RST 9 +#define MT8135_PERI_AUXADC_SW_RST 10 +#define MT8135_PERI_DMA_SW_RST 11 +#define MT8135_PERI_NFI_SW_RST 14 +#define MT8135_PERI_PWM_SW_RST 15 +#define MT8135_PERI_THERM_SW_RST 16 +#define MT8135_PERI_MSDC0_SW_RST 17 +#define MT8135_PERI_MSDC1_SW_RST 18 +#define MT8135_PERI_MSDC2_SW_RST 19 +#define MT8135_PERI_MSDC3_SW_RST 20 +#define MT8135_PERI_I2C0_SW_RST 22 +#define MT8135_PERI_I2C1_SW_RST 23 +#define MT8135_PERI_I2C2_SW_RST 24 +#define MT8135_PERI_I2C3_SW_RST 25 +#define MT8135_PERI_I2C4_SW_RST 26 +#define MT8135_PERI_I2C5_SW_RST 27 +#define MT8135_PERI_I2C6_SW_RST 28 +#define MT8135_PERI_USB_SW_RST 29 +#define MT8135_PERI_SPI1_SW_RST 33 +#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ diff --git a/include/dt-bindings/reset/mt8173-resets.h b/include/dt-bindings/reset/mt8173-resets.h new file mode 100644 index 000000000000..9464b37cf68c --- /dev/null +++ b/include/dt-bindings/reset/mt8173-resets.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Flora Fu, MediaTek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8173 + +/* INFRACFG resets */ +#define MT8173_INFRA_EMI_REG_RST 0 +#define MT8173_INFRA_DRAMC0_A0_RST 1 +#define MT8173_INFRA_APCIRQ_EINT_RST 3 +#define MT8173_INFRA_APXGPT_RST 4 +#define MT8173_INFRA_SCPSYS_RST 5 +#define MT8173_INFRA_KP_RST 6 +#define MT8173_INFRA_PMIC_WRAP_RST 7 +#define MT8173_INFRA_MPIP_RST 8 +#define MT8173_INFRA_CEC_RST 9 +#define MT8173_INFRA_EMI_RST 32 +#define MT8173_INFRA_DRAMC0_RST 34 +#define MT8173_INFRA_APMIXEDSYS_RST 35 +#define MT8173_INFRA_MIPI_DSI_RST 36 +#define MT8173_INFRA_TRNG_RST 37 +#define MT8173_INFRA_SYSIRQ_RST 38 +#define MT8173_INFRA_MIPI_CSI_RST 39 +#define MT8173_INFRA_GCE_FAXI_RST 40 +#define MT8173_INFRA_MMIOMMURST 47 + + +/* PERICFG resets */ +#define MT8173_PERI_UART0_SW_RST 0 +#define MT8173_PERI_UART1_SW_RST 1 +#define MT8173_PERI_UART2_SW_RST 2 +#define MT8173_PERI_UART3_SW_RST 3 +#define MT8173_PERI_IRRX_SW_RST 4 +#define MT8173_PERI_PWM_SW_RST 8 +#define MT8173_PERI_AUXADC_SW_RST 10 +#define MT8173_PERI_DMA_SW_RST 11 +#define MT8173_PERI_I2C6_SW_RST 13 +#define MT8173_PERI_NFI_SW_RST 14 +#define MT8173_PERI_THERM_SW_RST 16 +#define MT8173_PERI_MSDC2_SW_RST 17 +#define MT8173_PERI_MSDC3_SW_RST 18 +#define MT8173_PERI_MSDC0_SW_RST 19 +#define MT8173_PERI_MSDC1_SW_RST 20 +#define MT8173_PERI_I2C0_SW_RST 22 +#define MT8173_PERI_I2C1_SW_RST 23 +#define MT8173_PERI_I2C2_SW_RST 24 +#define MT8173_PERI_I2C3_SW_RST 25 +#define MT8173_PERI_I2C4_SW_RST 26 +#define MT8173_PERI_HDMI_SW_RST 29 +#define MT8173_PERI_SPI0_SW_RST 33 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ -- cgit From fc63efdf4bbcc23968bc71cfbc7dedf56c5ff01e Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 13 Nov 2015 01:53:39 -0300 Subject: pinctrl: Move am4372 and dra7 macros to the the SoC header files The header file defines a set of macros for different SoCs families that falls under the OMAP sub-arch, that allow to define the padconf register physical address instead of the register offset from the padconf base. But the am43xx and dra7xx SoCs families have their own pinctrl header file so the DTS using these SoCs aren't able to use the AM4372_IOPAD() and DRA7XX_CORE_IOPAD() macros since is not included. Move the macros to the correct header files so can be used by the DTS. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- include/dt-bindings/pinctrl/am43xx.h | 6 ++++++ include/dt-bindings/pinctrl/dra.h | 6 ++++++ include/dt-bindings/pinctrl/omap.h | 2 -- 3 files changed, 12 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h index 774dc1e843c5..344bd1eb3386 100644 --- a/include/dt-bindings/pinctrl/am43xx.h +++ b/include/dt-bindings/pinctrl/am43xx.h @@ -31,5 +31,11 @@ #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN) +/* + * Macro to allow using the absolute physical address instead of the + * padconf registers instead of the offset from padconf base. + */ +#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) + #endif diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h index 4379e29f0460..5c75e80915fc 100644 --- a/include/dt-bindings/pinctrl/dra.h +++ b/include/dt-bindings/pinctrl/dra.h @@ -67,5 +67,11 @@ #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) +/* + * Macro to allow using the absolute physical address instead of the + * padconf registers instead of the offset from padconf base. + */ +#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) + #endif diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h index 13949259705a..8100de13851c 100644 --- a/include/dt-bindings/pinctrl/omap.h +++ b/include/dt-bindings/pinctrl/omap.h @@ -63,8 +63,6 @@ #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) /* * Macros to allow using the offset from the padconf physical address -- cgit From 23d711ab4dec7552cad8d03d12e253ac66e70a95 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 30 Nov 2015 15:16:51 +0100 Subject: ARM: shmobile: sh73a0: Add MSIOF clocks The 4 MSIOF clocks are MSTP clocks, and children of the SUB clock. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- include/dt-bindings/clock/sh73a0-clock.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h index 53369568c24c..2eca353a29d7 100644 --- a/include/dt-bindings/clock/sh73a0-clock.h +++ b/include/dt-bindings/clock/sh73a0-clock.h @@ -28,7 +28,8 @@ #define SH73A0_CLK_HP 14 /* MSTP0 */ -#define SH73A0_CLK_IIC2 1 +#define SH73A0_CLK_IIC2 1 +#define SH73A0_CLK_MSIOF0 0 /* MSTP1 */ #define SH73A0_CLK_CEU1 29 @@ -45,8 +46,11 @@ #define SH73A0_CLK_SCIFA7 19 #define SH73A0_CLK_SY_DMAC 18 #define SH73A0_CLK_MP_DMAC 17 +#define SH73A0_CLK_MSIOF3 15 +#define SH73A0_CLK_MSIOF1 8 #define SH73A0_CLK_SCIFA5 7 #define SH73A0_CLK_SCIFB 6 +#define SH73A0_CLK_MSIOF2 5 #define SH73A0_CLK_SCIFA0 4 #define SH73A0_CLK_SCIFA1 3 #define SH73A0_CLK_SCIFA2 2 -- cgit From eaa870b3055384092d8fc075bca3a3a819f73c43 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 3 Dec 2015 01:21:49 +0300 Subject: ARM: shmobile: r8a7791: add EtherAVB clock Add the EtherAVB clock to the R8A7791 device tree. Based on the commit 63d2d750c902 ("ARM: shmobile: r8a7790: add EtherAVB clocks"). Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- include/dt-bindings/clock/r8a7791-clock.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index dd09b73c4aaf..ffa11379b3f0 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -102,6 +102,7 @@ #define R8A7791_CLK_VIN2 9 #define R8A7791_CLK_VIN1 10 #define R8A7791_CLK_VIN0 11 +#define R8A7791_CLK_ETHERAVB 12 #define R8A7791_CLK_ETHER 13 #define R8A7791_CLK_SATA1 14 #define R8A7791_CLK_SATA0 15 -- cgit From b4d6df2a2324dbf567592d7995738950b5c325a5 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 22 Dec 2015 16:00:33 -0800 Subject: ARM: dts: Add pinctrl macros for dm814x Let's add the DM814X_IOPAD macro the same way as we have for dm816x and am33xx as this allows comparing the registers with the documentation easily. The pinctrl bits are yet again different on dm814x. Cc: Linus Walleij Signed-off-by: Tony Lindgren --- include/dt-bindings/pinctrl/dm814x.h | 48 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/pinctrl/omap.h | 1 + 2 files changed, 49 insertions(+) create mode 100644 include/dt-bindings/pinctrl/dm814x.h (limited to 'include') diff --git a/include/dt-bindings/pinctrl/dm814x.h b/include/dt-bindings/pinctrl/dm814x.h new file mode 100644 index 000000000000..0f484273da0d --- /dev/null +++ b/include/dt-bindings/pinctrl/dm814x.h @@ -0,0 +1,48 @@ +/* + * This header provides constants specific to DM814X pinctrl bindings. + */ + +#ifndef _DT_BINDINGS_PINCTRL_DM814X_H +#define _DT_BINDINGS_PINCTRL_DM814X_H + +#include + +#undef INPUT_EN +#undef PULL_UP +#undef PULL_ENA + +/* + * Note that dm814x silicon revision 2.1 and older require input enabled + * (bit 18 set) for all 3.3V I/Os to avoid cumulative hardware damage. For + * more info, see errata advisory 2.1.87. We leave bit 18 out of + * function-mask in dm814x.h and rely on the bootloader for it. + */ +#define INPUT_EN (1 << 18) +#define PULL_UP (1 << 17) +#define PULL_DISABLE (1 << 16) + +/* update macro depending on INPUT_EN and PULL_ENA */ +#undef PIN_OUTPUT +#undef PIN_OUTPUT_PULLUP +#undef PIN_OUTPUT_PULLDOWN +#undef PIN_INPUT +#undef PIN_INPUT_PULLUP +#undef PIN_INPUT_PULLDOWN + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +/* undef non-existing modes */ +#undef PIN_OFF_NONE +#undef PIN_OFF_OUTPUT_HIGH +#undef PIN_OFF_OUTPUT_LOW +#undef PIN_OFF_INPUT_PULLUP +#undef PIN_OFF_INPUT_PULLDOWN +#undef PIN_OFF_WAKEUPENABLE + +#endif + diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h index 13949259705a..d1e1512ac0f1 100644 --- a/include/dt-bindings/pinctrl/omap.h +++ b/include/dt-bindings/pinctrl/omap.h @@ -61,6 +61,7 @@ #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) +#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -- cgit