From b3c567e474b5ba4447b6e16063a3b0cffc22d205 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 21 Jul 2010 13:28:10 +0530 Subject: intel_mid: Add Mrst & Mfld DMA Drivers This patch add DMA drivers for DMA controllers in Langwell chipset of Intel(R) Moorestown platform and DMA controllers in Penwell of Intel(R) Medfield platfrom This patch adds support for Moorestown DMAC1 and DMAC2 controllers. It also add support for Medfiled GP DMA and DMAC1 controllers. These controllers supports memory to peripheral and peripheral to memory transfers. It support only single block transfers. This driver is based on Kernel DMA engine Anyone who wishes to use this controller should use DMA engine APIs This controller exposes DMA_SLAVE capabilities and notifies the client drivers of DMA transaction completion Config option required to be enabled CONFIG_INTEL_MID_DMAC=y Signed-off-by: Vinod Koul Signed-off-by: Alan Cox Signed-off-by: Dan Williams --- include/linux/intel_mid_dma.h | 86 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 include/linux/intel_mid_dma.h (limited to 'include') diff --git a/include/linux/intel_mid_dma.h b/include/linux/intel_mid_dma.h new file mode 100644 index 000000000000..d9d08b6269b6 --- /dev/null +++ b/include/linux/intel_mid_dma.h @@ -0,0 +1,86 @@ +/* + * intel_mid_dma.h - Intel MID DMA Drivers + * + * Copyright (C) 2008-10 Intel Corp + * Author: Vinod Koul + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * + */ +#ifndef __INTEL_MID_DMA_H__ +#define __INTEL_MID_DMA_H__ + +#include + +/*DMA transaction width, src and dstn width would be same +The DMA length must be width aligned, +for 32 bit width the length must be 32 bit (4bytes) aligned only*/ +enum intel_mid_dma_width { + LNW_DMA_WIDTH_8BIT = 0x0, + LNW_DMA_WIDTH_16BIT = 0x1, + LNW_DMA_WIDTH_32BIT = 0x2, +}; + +/*DMA mode configurations*/ +enum intel_mid_dma_mode { + LNW_DMA_PER_TO_MEM = 0, /*periphral to memory configuration*/ + LNW_DMA_MEM_TO_PER, /*memory to periphral configuration*/ + LNW_DMA_MEM_TO_MEM, /*mem to mem confg (testing only)*/ +}; + +/*DMA handshaking*/ +enum intel_mid_dma_hs_mode { + LNW_DMA_HW_HS = 0, /*HW Handshaking only*/ + LNW_DMA_SW_HS = 1, /*SW Handshaking not recommended*/ +}; + +/*Burst size configuration*/ +enum intel_mid_dma_msize { + LNW_DMA_MSIZE_1 = 0x0, + LNW_DMA_MSIZE_4 = 0x1, + LNW_DMA_MSIZE_8 = 0x2, + LNW_DMA_MSIZE_16 = 0x3, + LNW_DMA_MSIZE_32 = 0x4, + LNW_DMA_MSIZE_64 = 0x5, +}; + +/** + * struct intel_mid_dma_slave - DMA slave structure + * + * @dirn: DMA trf direction + * @src_width: tx register width + * @dst_width: rx register width + * @hs_mode: HW/SW handshaking mode + * @cfg_mode: DMA data transfer mode (per-per/mem-per/mem-mem) + * @src_msize: Source DMA burst size + * @dst_msize: Dst DMA burst size + * @device_instance: DMA peripheral device instance, we can have multiple + * peripheral device connected to single DMAC + */ +struct intel_mid_dma_slave { + enum dma_data_direction dirn; + enum intel_mid_dma_width src_width; /*width of DMA src txn*/ + enum intel_mid_dma_width dst_width; /*width of DMA dst txn*/ + enum intel_mid_dma_hs_mode hs_mode; /*handshaking*/ + enum intel_mid_dma_mode cfg_mode; /*mode configuration*/ + enum intel_mid_dma_msize src_msize; /*size if src burst*/ + enum intel_mid_dma_msize dst_msize; /*size of dst burst*/ + unsigned int device_instance; /*0, 1 for periphral instance*/ +}; + +#endif /*__INTEL_MID_DMA_H__*/ -- cgit From 0c42bd0e425e9c8ddb7019fc446f7d915e36c5f6 Mon Sep 17 00:00:00 2001 From: Yong Wang Date: Fri, 30 Jul 2010 16:23:03 +0800 Subject: dmaengine: Driver for Topcliff PCH DMA controller Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platforms. This adds the driver for Topcliff PCH DMA controller. The DMA channels are strictly for device to host or host to device transfers and cannot be used for generic memcpy. Signed-off-by: Yong Wang [kill GFP_ATOMIC, kill __raw_{read|write}l, locking fixlet] Signed-off-by: Dan Williams --- include/linux/pch_dma.h | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 include/linux/pch_dma.h (limited to 'include') diff --git a/include/linux/pch_dma.h b/include/linux/pch_dma.h new file mode 100644 index 000000000000..fdafe529ef8a --- /dev/null +++ b/include/linux/pch_dma.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2010 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef PCH_DMA_H +#define PCH_DMA_H + +#include + +enum pch_dma_width { + PCH_DMA_WIDTH_1_BYTE, + PCH_DMA_WIDTH_2_BYTES, + PCH_DMA_WIDTH_4_BYTES, +}; + +struct pch_dma_slave { + struct device *dma_dev; + unsigned int chan_id; + dma_addr_t tx_reg; + dma_addr_t rx_reg; + enum pch_dma_width width; +}; + +#endif -- cgit From c156d0a5b0c667999e06d0bb52e3d1376faec8bf Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 4 Aug 2010 13:37:33 +0200 Subject: DMAENGINE: generic slave channel control v3 This adds an interface to the DMAengine to make it possible to reconfigure a slave channel at runtime. We add a few foreseen config parameters to the passed struct, with a void * pointer for custom per-device or per-platform runtime slave data. Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- include/linux/dmaengine.h | 71 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) (limited to 'include') diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 5204f018931b..c61d4ca27bcc 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -114,11 +114,17 @@ enum dma_ctrl_flags { * @DMA_TERMINATE_ALL: terminate all ongoing transfers * @DMA_PAUSE: pause ongoing transfers * @DMA_RESUME: resume paused transfer + * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers + * that need to runtime reconfigure the slave channels (as opposed to passing + * configuration data in statically from the platform). An additional + * argument of struct dma_slave_config must be passed in with this + * command. */ enum dma_ctrl_cmd { DMA_TERMINATE_ALL, DMA_PAUSE, DMA_RESUME, + DMA_SLAVE_CONFIG, }; /** @@ -199,6 +205,71 @@ struct dma_chan_dev { atomic_t *idr_ref; }; +/** + * enum dma_slave_buswidth - defines bus with of the DMA slave + * device, source or target buses + */ +enum dma_slave_buswidth { + DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, + DMA_SLAVE_BUSWIDTH_1_BYTE = 1, + DMA_SLAVE_BUSWIDTH_2_BYTES = 2, + DMA_SLAVE_BUSWIDTH_4_BYTES = 4, + DMA_SLAVE_BUSWIDTH_8_BYTES = 8, +}; + +/** + * struct dma_slave_config - dma slave channel runtime config + * @direction: whether the data shall go in or out on this slave + * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are + * legal values, DMA_BIDIRECTIONAL is not acceptable since we + * need to differentiate source and target addresses. + * @src_addr: this is the physical address where DMA slave data + * should be read (RX), if the source is memory this argument is + * ignored. + * @dst_addr: this is the physical address where DMA slave data + * should be written (TX), if the source is memory this argument + * is ignored. + * @src_addr_width: this is the width in bytes of the source (RX) + * register where DMA data shall be read. If the source + * is memory this may be ignored depending on architecture. + * Legal values: 1, 2, 4, 8. + * @dst_addr_width: same as src_addr_width but for destination + * target (TX) mutatis mutandis. + * @src_maxburst: the maximum number of words (note: words, as in + * units of the src_addr_width member, not bytes) that can be sent + * in one burst to the device. Typically something like half the + * FIFO depth on I/O peripherals so you don't overflow it. This + * may or may not be applicable on memory sources. + * @dst_maxburst: same as src_maxburst but for destination target + * mutatis mutandis. + * + * This struct is passed in as configuration data to a DMA engine + * in order to set up a certain channel for DMA transport at runtime. + * The DMA device/engine has to provide support for an additional + * command in the channel config interface, DMA_SLAVE_CONFIG + * and this struct will then be passed in as an argument to the + * DMA engine device_control() function. + * + * The rationale for adding configuration information to this struct + * is as follows: if it is likely that most DMA slave controllers in + * the world will support the configuration option, then make it + * generic. If not: if it is fixed so that it be sent in static from + * the platform data, then prefer to do that. Else, if it is neither + * fixed at runtime, nor generic enough (such as bus mastership on + * some CPU family and whatnot) then create a custom slave config + * struct and pass that, then make this config a member of that + * struct, if applicable. + */ +struct dma_slave_config { + enum dma_data_direction direction; + dma_addr_t src_addr; + dma_addr_t dst_addr; + enum dma_slave_buswidth src_addr_width; + enum dma_slave_buswidth dst_addr_width; + u32 src_maxburst; + u32 dst_maxburst; +}; + static inline const char *dma_chan_name(struct dma_chan *chan) { return dev_name(&chan->dev->device); -- cgit