From 1e61405e201515d5767106babb4d750661ba5dcd Mon Sep 17 00:00:00 2001 From: Kirill Marinushkin Date: Mon, 11 Feb 2019 07:08:39 +0100 Subject: ASoC: pcm3060: Add clock select ADC and DAC can be clocked from separate or same sources CLK1 and CLK2. By default, ADC is clocked from CLK1, and DAC - from CLK2. This commits allows sound cards to selest a proper clock source during `hw_params()` via `snd_soc_dai_set_sysclk()`. It makes possible to have a single clock source for both ADC and DAC. Signed-off-by: Kirill Marinushkin Signed-off-by: Mark Brown --- sound/soc/codecs/pcm3060.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'sound/soc/codecs/pcm3060.c') diff --git a/sound/soc/codecs/pcm3060.c b/sound/soc/codecs/pcm3060.c index 543cb86fd764..32b26f1c2282 100644 --- a/sound/soc/codecs/pcm3060.c +++ b/sound/soc/codecs/pcm3060.c @@ -18,12 +18,39 @@ static int pcm3060_set_sysclk(struct snd_soc_dai *dai, int clk_id, { struct snd_soc_component *comp = dai->component; struct pcm3060_priv *priv = snd_soc_component_get_drvdata(comp); + unsigned int reg; + unsigned int val; if (dir != SND_SOC_CLOCK_IN) { dev_err(comp->dev, "unsupported sysclock dir: %d\n", dir); return -EINVAL; } + switch (clk_id) { + case PCM3060_CLK_DEF: + val = 0; + break; + + case PCM3060_CLK1: + val = (dai->id == PCM3060_DAI_ID_DAC ? PCM3060_REG_CSEL : 0); + break; + + case PCM3060_CLK2: + val = (dai->id == PCM3060_DAI_ID_DAC ? 0 : PCM3060_REG_CSEL); + break; + + default: + dev_err(comp->dev, "unsupported sysclock id: %d\n", clk_id); + return -EINVAL; + } + + if (dai->id == PCM3060_DAI_ID_DAC) + reg = PCM3060_REG67; + else + reg = PCM3060_REG72; + + regmap_update_bits(priv->regmap, reg, PCM3060_REG_CSEL, val); + priv->dai[dai->id].sclk_freq = freq; return 0; -- cgit