/* * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) * * Copyright (C) 2015 Russell King * * This board is in development; the contents of this file work with * the A1 rev 2.0 of the board, which does not represent final * production board. Things will change, don't expect this file to * remain compatible info the future. * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "armada-388-clearfog.dtsi" / { model = "SolidRun Clearfog A1"; compatible = "solidrun,clearfog-a1", "marvell,armada388", "marvell,armada385", "marvell,armada380"; soc { internal-regs { usb3@f0000 { /* CON2, nearest CPU, USB2 only. */ status = "okay"; }; }; pcie-controller { pcie@3,0 { /* Port 2, Lane 0. CON2, nearest CPU. */ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; status = "okay"; }; }; }; dsa@0 { compatible = "marvell,dsa"; dsa,ethernet = <ð1>; dsa,mii-bus = <&mdio>; pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; pinctrl-names = "default"; #address-cells = <2>; #size-cells = <0>; switch@0 { #address-cells = <1>; #size-cells = <0>; reg = <4 0>; port@0 { reg = <0>; label = "lan5"; }; port@1 { reg = <1>; label = "lan4"; }; port@2 { reg = <2>; label = "lan3"; }; port@3 { reg = <3>; label = "lan2"; }; port@4 { reg = <4>; label = "lan1"; }; port@5 { reg = <5>; label = "cpu"; }; port@6 { /* 88E1512 external phy */ reg = <6>; label = "lan6"; fixed-link { speed = <1000>; full-duplex; }; }; }; }; gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&rear_button_pins>; pinctrl-names = "default"; button_0 { /* The rear SW3 button */ label = "Rear Button"; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; linux,can-disable; linux,code = ; }; }; }; ð1 { /* ethernet@30000 */ fixed-link { speed = <1000>; full-duplex; }; }; &expander0 { /* * PCA9655 GPIO expander: * 0-CON3 CLKREQ# * 1-CON3 PERST# * 2-CON2 PERST# * 3-CON3 W_DISABLE * 4-CON2 CLKREQ# * 5-USB3 overcurrent * 6-USB3 power * 7-CON2 W_DISABLE * 8-JP4 P1 * 9-JP4 P4 * 10-JP4 P5 * 11-m.2 DEVSLP * 12-SFP_LOS * 13-SFP_TX_FAULT * 14-SFP_TX_DISABLE * 15-SFP_MOD_DEF0 */ pcie2_0_clkreq { gpio-hog; gpios = <4 GPIO_ACTIVE_LOW>; input; line-name = "pcie2.0-clkreq"; }; pcie2_0_w_disable { gpio-hog; gpios = <7 GPIO_ACTIVE_LOW>; output-low; line-name = "pcie2.0-w-disable"; }; }; &pinctrl { clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { marvell,pins = "mpp46"; marvell,function = "ref"; }; clearfog_dsa0_pins: clearfog-dsa0-pins { marvell,pins = "mpp23", "mpp41"; marvell,function = "gpio"; }; clearfog_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp55"; marvell,function = "spi1"; }; rear_button_pins: rear-button-pins { marvell,pins = "mpp34"; marvell,function = "gpio"; }; }; &spi1 { /* * Add SPI CS pins for clearfog: * CS0: W25Q32 (not populated on uSOM) * CS1: * CS2: mikrobus */ pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; }; /* +#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 MPP18: gpio ? (pca9655 int?) MPP19: gpio ? (clkreq?) MPP20: gpio ? (sd0 detect) MPP21: sd0:cmd x sd0 MPP22: gpio x mikro int MPP23: gpio x switch irq +#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333 MPP24: ua1:rxd x mikro rx MPP25: ua1:txd x mikro tx MPP26: i2c1:sck x mikro sck MPP27: i2c1:sda x mikro sda MPP28: sd0:clk x sd0 MPP29: gpio x mikro rst MPP30: ge1:txd2 ? (config) MPP31: ge1:txd3 ? (config) +#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002 MPP32: ge1:txctl ? (unused) MPP33: gpio ? (pic_com0) MPP34: gpio x rear button (pic_com1) MPP35: gpio ? (pic_com2) MPP36: gpio ? (unused) MPP37: sd0:d3 x sd0 MPP38: sd0:d0 x sd0 MPP39: sd0:d1 x sd0 +#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004 MPP40: sd0:d2 x sd0 MPP41: gpio x switch reset MPP42: gpio ? sw1-1 MPP43: spi1:cs2 x mikro cs MPP44: sata3:prsnt ? (unused) MPP45: ref:clk_out0 ? MPP46: ref:clk_out1 x switch clk MPP47: 4 ? (unused) +#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333 MPP48: tdm:pclk MPP49: tdm:fsync MPP50: tdm:drx MPP51: tdm:dtx MPP52: tdm:int MPP53: tdm:rst MPP54: gpio ? (pwm) MPP55: spi1:cs1 x slic +#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444 MPP56: spi1:mosi x mikro mosi MPP57: spi1:sck x mikro sck MPP58: spi1:miso x mikro miso MPP59: spi1:cs0 x w25q32 */