/* * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. * * Mingkai Hu * * This file is dual-licensed: you can use it either under the terms * of the GPLv2 or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This library is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include #include / { compatible = "fsl,ls1046a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { crypto = &crypto; fman0 = &fman0; ethernet0 = &enet0; ethernet1 = &enet1; ethernet2 = &enet2; ethernet3 = &enet3; ethernet4 = &enet4; ethernet5 = &enet5; ethernet6 = &enet6; ethernet7 = &enet7; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x1>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x2>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x3>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; }; l2: l2-cache { compatible = "cache"; }; }; idle-states { /* * PSCI node is not added default, U-boot will add missing * parts if it determines to use PSCI. */ entry-method = "arm,psci"; CPU_PH20: cpu-ph20 { compatible = "arm,idle-state"; idle-state-name = "PH20"; arm,psci-suspend-param = <0x00010000>; entry-latency-us = <1000>; exit-latency-us = <1000>; min-residency-us = <3000>; }; }; memory@80000000 { device_type = "memory"; }; sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "sysclk"; }; reboot { compatible ="syscon-reboot"; regmap = <&dcfg>; offset = <0xb0>; mask = <0x02>; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; pmu { compatible = "arm,cortex-a72-pmu"; interrupts = , , , ; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; gic: interrupt-controller@1400000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x1410000 0 0x10000>, /* GICD */ <0x0 0x1420000 0 0x20000>, /* GICC */ <0x0 0x1440000 0 0x20000>, /* GICH */ <0x0 0x1460000 0 0x20000>; /* GICV */ interrupts = ; }; soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; ddr: memory-controller@1080000 { compatible = "fsl,qoriq-memory-controller"; reg = <0x0 0x1080000 0x0 0x1000>; interrupts = ; big-endian; }; ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; big-endian; interrupts = ; }; qspi: quadspi@1550000 { compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1550000 0x0 0x10000>, <0x0 0x40000000 0x0 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = ; clock-names = "qspi_en", "qspi"; clocks = <&clockgen 4 1>, <&clockgen 4 1>; big-endian; fsl,qspi-has-second-chip; status = "disabled"; }; esdhc: esdhc@1560000 { compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 2 1>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; big-endian; bus-width = <4>; }; scfg: scfg@1570000 { compatible = "fsl,ls1046a-scfg", "syscon"; reg = <0x0 0x1570000 0x0 0x10000>; big-endian; }; crypto: crypto@1700000 { compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <8>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x1700000 0x100000>; reg = <0x00 0x1700000 0x0 0x100000>; interrupts = ; sec_jr0: jr@10000 { compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x10000 0x10000>; interrupts = ; }; sec_jr1: jr@20000 { compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x20000 0x10000>; interrupts = ; }; sec_jr2: jr@30000 { compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x30000 0x10000>; interrupts = ; }; sec_jr3: jr@40000 { compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x40000 0x10000>; interrupts = ; }; }; qman: qman@1880000 { compatible = "fsl,qman"; reg = <0x0 0x1880000 0x0 0x10000>; interrupts = ; memory-region = <&qman_fqd &qman_pfdr>; }; bman: bman@1890000 { compatible = "fsl,bman"; reg = <0x0 0x1890000 0x0 0x10000>; interrupts = ; memory-region = <&bman_fbpr>; }; qportals: qman-portals@500000000 { ranges = <0x0 0x5 0x00000000 0x8000000>; }; bportals: bman-portals@508000000 { ranges = <0x0 0x5 0x08000000 0x8000000>; }; dcfg: dcfg@1ee0000 { compatible = "fsl,ls1046a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x10000>; big-endian; }; clockgen: clocking@1ee1000 { compatible = "fsl,ls1046a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; #clock-cells = <2>; clocks = <&sysclk>; }; tmu: tmu@1f00000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = <0 33 0x4>; fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; fsl,tmu-calibration = /* Calibration data group 1 */ <0x00000000 0x00000026 0x00000001 0x0000002d 0x00000002 0x00000032 0x00000003 0x00000039 0x00000004 0x0000003f 0x00000005 0x00000046 0x00000006 0x0000004d 0x00000007 0x00000054 0x00000008 0x0000005a 0x00000009 0x00000061 0x0000000a 0x0000006a 0x0000000b 0x00000071 /* Calibration data group 2 */ 0x00010000 0x00000025 0x00010001 0x0000002c 0x00010002 0x00000035 0x00010003 0x0000003d 0x00010004 0x00000045 0x00010005 0x0000004e 0x00010006 0x00000057 0x00010007 0x00000061 0x00010008 0x0000006b 0x00010009 0x00000076 /* Calibration data group 3 */ 0x00020000 0x00000029 0x00020001 0x00000033 0x00020002 0x0000003d 0x00020003 0x00000049 0x00020004 0x00000056 0x00020005 0x00000061 0x00020006 0x0000006d /* Calibration data group 4 */ 0x00030000 0x00000021 0x00030001 0x0000002a 0x00030002 0x0000003c 0x00030003 0x0000004e>; big-endian; #thermal-sensor-cells = <1>; }; thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 3>; trips { cpu_alert: cpu-alert { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; cpu_crit: cpu-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; dspi: dspi@2100000 { compatible = "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; clocks = <&clockgen 4 1>; spi-num-chipselects = <5>; big-endian; status = "disabled"; }; i2c0: i2c@2180000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; dmas = <&edma0 1 39>, <&edma0 1 38>; dma-names = "tx", "rx"; status = "disabled"; }; i2c1: i2c@2190000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; i2c2: i2c@21a0000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21a0000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; i2c3: i2c@21b0000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21b0000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; }; duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0600 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; }; duart2: serial@21d0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0500 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; }; duart3: serial@21d0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0600 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; }; gpio0: gpio@2300000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio1: gpio@2310000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@2320000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@2330000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2330000 0x0 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; lpuart0: serial@2950000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2950000 0x0 0x1000>; interrupts = ; clocks = <&clockgen 4 0>; clock-names = "ipg"; status = "disabled"; }; lpuart1: serial@2960000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2960000 0x0 0x1000>; interrupts = ; clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; lpuart2: serial@2970000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2970000 0x0 0x1000>; interrupts = ; clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; lpuart3: serial@2980000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2980000 0x0 0x1000>; interrupts = ; clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; lpuart4: serial@2990000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2990000 0x0 0x1000>; interrupts = ; clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; lpuart5: serial@29a0000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x29a0000 0x0 0x1000>; interrupts = ; clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; wdog0: watchdog@2ad0000 { compatible = "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; big-endian; }; edma0: edma@2c00000 { #dma-cells = <2>; compatible = "fsl,vf610-edma"; reg = <0x0 0x2c00000 0x0 0x10000>, <0x0 0x2c10000 0x0 0x10000>, <0x0 0x2c20000 0x0 0x10000>; interrupts = , ; interrupt-names = "edma-tx", "edma-err"; dma-channels = <32>; big-endian; clock-names = "dmamux0", "dmamux1"; clocks = <&clockgen 4 1>, <&clockgen 4 1>; }; usb0: usb@2f00000 { compatible = "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; }; usb1: usb@3000000 { compatible = "snps,dwc3"; reg = <0x0 0x3000000 0x0 0x10000>; interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; }; usb2: usb@3100000 { compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; }; sata: sata@3200000 { compatible = "fsl,ls1046a-ahci"; reg = <0x0 0x3200000 0x0 0x10000>, <0x0 0x20140520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; clocks = <&clockgen 4 1>; }; msi1: msi-controller@1580000 { compatible = "fsl,ls1046a-msi"; msi-controller; reg = <0x0 0x1580000 0x0 0x10000>; interrupts = , , , ; }; msi2: msi-controller@1590000 { compatible = "fsl,ls1046a-msi"; msi-controller; reg = <0x0 0x1590000 0x0 0x10000>; interrupts = , , , ; }; msi3: msi-controller@15a0000 { compatible = "fsl,ls1046a-msi"; msi-controller; reg = <0x0 0x15a0000 0x0 0x10000>; interrupts = , , , ; }; pcie@3400000 { compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = , /* controller interrupt */ ; /* PME interrupt */ interrupt-names = "aer", "pme"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&msi1>, <&msi2>, <&msi3>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; }; pcie@3500000 { compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = , /* controller interrupt */ ; /* PME interrupt */ interrupt-names = "aer", "pme"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; dma-coherent; num-lanes = <2>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&msi2>, <&msi3>, <&msi1>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; }; pcie@3600000 { compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = , /* controller interrupt */ ; /* PME interrupt */ interrupt-names = "aer", "pme"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; dma-coherent; num-lanes = <2>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&msi3>, <&msi1>, <&msi2>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; }; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; bman_fbpr: bman-fbpr { compatible = "shared-dma-pool"; size = <0 0x1000000>; alignment = <0 0x1000000>; no-map; }; qman_fqd: qman-fqd { compatible = "shared-dma-pool"; size = <0 0x800000>; alignment = <0 0x800000>; no-map; }; qman_pfdr: qman-pfdr { compatible = "shared-dma-pool"; size = <0 0x2000000>; alignment = <0 0x2000000>; no-map; }; }; firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; }; }; }; #include "qoriq-qman-portals.dtsi" #include "qoriq-bman-portals.dtsi"