// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * Copyright 2020-2021 TQ-Systems GmbH */ #include "imx8mn.dtsi" / { model = "TQ-Systems i.MX8MN TQMa8MxNL"; compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; memory@40000000 { device_type = "memory"; /* our minimum RAM config will be 1024 MiB */ reg = <0x00000000 0x40000000 0 0x40000000>; }; /* e-MMC IO, needed for HS modes */ reg_vcc1v8: regulator-vcc1v8 { compatible = "regulator-fixed"; regulator-name = "TQMA8MXNL_VCC1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; reg_vcc3v3: regulator-vcc3v3 { compatible = "regulator-fixed"; regulator-name = "TQMA8MXNL_VCC3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; reusable; /* 640 MiB */ size = <0 0x28000000>; /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ alloc-ranges = <0 0x40000000 0 0x78000000>; linux,cma-default; }; }; }; &A53_0 { cpu-supply = <&buck2_reg>; }; &flexspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; }; }; &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; sensor0: temperature-sensor@1b { compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x1b>; }; pca9450: pmic@25 { compatible = "nxp,pca9450a"; reg = <0x25>; /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ pinctrl-0 = <&pinctrl_pmic>; pinctrl-names = "default"; interrupt-parent = <&gpio1>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; regulators { /* V_0V85_SOC: 0.85 .. 0.95 */ buck1_reg: BUCK1 { regulator-name = "BUCK1"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <950000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; }; /* VDD_ARM */ buck2_reg: BUCK2 { regulator-name = "BUCK2"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; nxp,dvs-run-voltage = <950000>; nxp,dvs-standby-voltage = <850000>; regulator-ramp-delay = <3125>; }; /* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */ buck3_reg: BUCK3 { regulator-name = "BUCK3"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <950000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; }; /* VCC3V3 -> VMMC, ... must not be changed */ buck4_reg: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ buck5_reg: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; /* V_1V1 -> RAM, ... must not be changed */ buck6_reg: BUCK6 { regulator-name = "BUCK6"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; /* V_1V8_SNVS */ ldo1_reg: LDO1 { regulator-name = "LDO1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; /* V_0V8_SNVS */ ldo2_reg: LDO2 { regulator-name = "LDO2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <850000>; regulator-boot-on; regulator-always-on; }; /* V_1V8_ANA */ ldo3_reg: LDO3 { regulator-name = "LDO3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; /* V_0V9_MIPI */ ldo4_reg: LDO4 { regulator-name = "LDO4"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; }; /* VCC SD IO - switched using SD2 VSELECT */ ldo5_reg: LDO5 { regulator-name = "LDO5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; }; }; pcf85063: rtc@51 { compatible = "nxp,pcf85063a"; reg = <0x51>; quartz-load-femtofarads = <7000>; }; eeprom1: eeprom@53 { compatible = "nxp,se97b", "atmel,24c02"; read-only; reg = <0x53>; pagesize = <16>; vcc-supply = <®_vcc3v3>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; vcc-supply = <®_vcc3v3>; }; }; &mipi_dsi { vddcore-supply = <&ldo4_reg>; vddio-supply = <&ldo3_reg>; }; &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; bus-width = <8>; non-removable; no-sd; no-sdio; vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc1v8>; status = "okay"; }; /* * Attention: * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. */ &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; }; &iomuxc { pinctrl_flexspi: flexspigrp { fsl,pins = , , , , , ; }; pinctrl_i2c1: i2c1grp { fsl,pins = , ; }; pinctrl_i2c1_gpio: i2c1gpiogrp { fsl,pins = , ; }; pinctrl_pmic: pmicgrp { fsl,pins = ; }; pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = ; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = , , , , , , , , , , , ; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = , , , , , , , , , , , ; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = , , , , , , , , , , , ; }; pinctrl_wdog: wdoggrp { fsl,pins = ; }; };