// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
#include <dt-bindings/reset/mediatek,mt6795-resets.h>

/ {
	compatible = "mediatek,mt6795";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x000>;
			cci-control-port = <&cci_control2>;
			next-level-cache = <&l2_0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x001>;
			cci-control-port = <&cci_control2>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x002>;
			cci-control-port = <&cci_control2>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x003>;
			cci-control-port = <&cci_control2>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x100>;
			cci-control-port = <&cci_control1>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_1>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x101>;
			cci-control-port = <&cci_control1>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_1>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x102>;
			cci-control-port = <&cci_control1>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_1>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x103>;
			cci-control-port = <&cci_control1>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_1>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};

				core1 {
					cpu = <&cpu5>;
				};

				core2 {
					cpu = <&cpu6>;
				};

				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		l2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-size = <1048576>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-unified;
		};

		l2_1: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
			cache-size = <1048576>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-unified;
		};
	};

	clk26m: oscillator-26m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	clk32k: oscillator-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "clk32k";
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		topckgen: syscon@10000000 {
			compatible = "mediatek,mt6795-topckgen", "syscon";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: syscon@10001000 {
			compatible = "mediatek,mt6795-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pericfg: syscon@10003000 {
			compatible = "mediatek,mt6795-pericfg", "syscon";
			reg = <0 0x10003000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pio: pinctrl@10005000 {
			compatible = "mediatek,mt6795-pinctrl";
			reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
			reg-names = "base", "eint";
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pio 0 0 196>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		watchdog: watchdog@10007000 {
			compatible = "mediatek,mt6795-wdt";
			reg = <0 0x10007000 0 0x100>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
			#reset-cells = <1>;
			timeout-sec = <20>;
		};

		timer: timer@10008000 {
			compatible = "mediatek,mt6795-timer",
				     "mediatek,mt6577-timer";
			reg = <0 0x10008000 0 0x1000>;
			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&system_clk>, <&clk32k>;
		};

		sysirq: intpol-controller@10200620 {
			compatible = "mediatek,mt6795-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10200620 0 0x20>;
		};

		systimer: timer@10200670 {
			compatible = "mediatek,mt6795-systimer";
			reg = <0 0x10200670 0 0x10>;
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&system_clk>;
			clock-names = "clk13m";
		};

		gic: interrupt-controller@10221000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x10221000 0 0x1000>,
			      <0 0x10222000 0 0x2000>,
			      <0 0x10224000 0 0x2000>,
			      <0 0x10226000 0 0x2000>;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		cci: cci@10390000 {
			compatible = "arm,cci-400";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0 0x10390000 0 0x1000>;
			ranges = <0 0 0x10390000 0x10000>;

			cci_control0: slave-if@1000 {
				compatible = "arm,cci-400-ctrl-if";
				interface-type = "ace-lite";
				reg = <0x1000 0x1000>;
			};

			cci_control1: slave-if@4000 {
				compatible = "arm,cci-400-ctrl-if";
				interface-type = "ace";
				reg = <0x4000 0x1000>;
			};

			cci_control2: slave-if@5000 {
				compatible = "arm,cci-400-ctrl-if";
				interface-type = "ace";
				reg = <0x5000 0x1000>;
			};

			pmu@9000 {
				compatible = "arm,cci-400-pmu,r1";
				reg = <0x9000 0x5000>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt6795-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x400>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
			clock-names = "baud", "bus";
			dmas = <&apdma 0>, <&apdma 1>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt6795-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x400>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
			clock-names = "baud", "bus";
			dmas = <&apdma 2>, <&apdma 3>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		apdma: dma-controller@11000380 {
			compatible = "mediatek,mt6795-uart-dma",
				     "mediatek,mt6577-uart-dma";
			reg = <0 0x11000380 0 0x60>,
			      <0 0x11000400 0 0x60>,
			      <0 0x11000480 0 0x60>,
			      <0 0x11000500 0 0x60>,
			      <0 0x11000580 0 0x60>,
			      <0 0x11000600 0 0x60>,
			      <0 0x11000680 0 0x60>,
			      <0 0x11000700 0 0x60>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
			dma-requests = <8>;
			clocks = <&pericfg CLK_PERI_AP_DMA>;
			clock-names = "apdma";
			mediatek,dma-33bits;
			#dma-cells = <1>;
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt6795-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x400>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
			clock-names = "baud", "bus";
			dmas = <&apdma 4>, <&apdma 5>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		uart3: serial@11005000 {
			compatible = "mediatek,mt6795-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11005000 0 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
			clock-names = "baud", "bus";
			dmas = <&apdma 6>, <&apdma 7>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mmc0: mmc@11230000 {
			compatible = "mediatek,mt6795-mmc";
			reg = <0 0x11230000 0 0x1000>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_0>,
				 <&topckgen CLK_TOP_MSDC50_0_H_SEL>,
				 <&topckgen CLK_TOP_MSDC50_0_SEL>;
			clock-names = "source", "hclk", "source_cg";
			status = "disabled";
		};

		mmc1: mmc@11240000 {
			compatible = "mediatek,mt6795-mmc";
			reg = <0 0x11240000 0 0x1000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_1>,
				 <&topckgen CLK_TOP_AXI_SEL>;
			clock-names = "source", "hclk";
			status = "disabled";
		};

		mmc2: mmc@11250000 {
			compatible = "mediatek,mt6795-mmc";
			reg = <0 0x11250000 0 0x1000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_2>,
				 <&topckgen CLK_TOP_AXI_SEL>;
			clock-names = "source", "hclk";
			status = "disabled";
		};

		mmc3: mmc@11260000 {
			compatible = "mediatek,mt6795-mmc";
			reg = <0 0x11260000 0 0x1000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_3>,
				 <&topckgen CLK_TOP_AXI_SEL>;
			clock-names = "source", "hclk";
			status = "disabled";
		};
	};
};