/* * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) * * Right now, I am very wasteful with the buffers. I allocate memory * pages and then divide them into 2K frame buffers. This way I know I * have buffers large enough to hold one frame within one buffer descriptor. * Once I get this working, I will use 64 or 128 byte CPM buffers, which * will be much more memory efficient and will easily handle lots of * small packets. * * Much better multiple PHY support by Magnus Damm. * Copyright (c) 2000 Ericsson Radio Systems AB. * * Support for FEC controller of ColdFire processors. * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) * * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) * Copyright (c) 2004-2006 Macq Electronique SA. * * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "fec.h" static void set_multicast_list(struct net_device *ndev); #if defined(CONFIG_ARM) #define FEC_ALIGNMENT 0xf #else #define FEC_ALIGNMENT 0x3 #endif #define DRIVER_NAME "fec" /* Pause frame field and FIFO threshold */ #define FEC_ENET_FCE (1 << 5) /* * RSEM: the FIFO threshold in 64-bit words (from zero bytes) at which * XOFF will be sent. Minimum 0, maximum possible 255. * RAFL: the number of remaining 64-bit words in the FIFO at which the * frame is marked with overrun. Minimum 4, maximum possible 255. * * When XOFF is sent, the link partner should continue sending any * packet currently in progress, and then pause transmission for the * specified duration. It should not terminate transmission of the * packet. * * The FIFO can store the full frame and the FCS value, which on standard * Ethernet is 1518 bytes, or 190 FIFO entries. However, we do not know * the size of the receive FIFO, so we are unable to properly calculate * the thresholds. * * Practical tests with 1514 byte ethernet packets show that with * RSEM = 132, RAFL = 8, we see a large quantity of overflowed UDP packets. * Reducing RAFL to 4 has almost no effect. Reducing RSEM to 78 gives us * a small number of overflow errors, and at 77 it gives only a single * error per UDP iperf run. */ #define FEC_ENET_RSEM_V 77 #define FEC_ENET_RSFL_V 16 #define FEC_ENET_RAEM_V 0x8 #define FEC_ENET_RAFL_V 4 #define FEC_ENET_OPD_V 0xFFF0 /* Controller is ENET-MAC */ #define FEC_QUIRK_ENET_MAC (1 << 0) /* Controller needs driver to swap frame */ #define FEC_QUIRK_SWAP_FRAME (1 << 1) /* Controller uses gasket */ #define FEC_QUIRK_USE_GASKET (1 << 2) /* Controller has GBIT support */ #define FEC_QUIRK_HAS_GBIT (1 << 3) /* Controller has extend desc buffer */ #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) /* Controller has hardware checksum support */ #define FEC_QUIRK_HAS_CSUM (1 << 5) /* Controller has hardware vlan support */ #define FEC_QUIRK_HAS_VLAN (1 << 6) /* Controller has ability to offset rx packets */ #define FEC_QUIRK_RX_SHIFT16 (1 << 8) static struct platform_device_id fec_devtype[] = { { /* keep it for coldfire */ .name = DRIVER_NAME, .driver_data = 0, }, { .name = "imx25-fec", .driver_data = FEC_QUIRK_USE_GASKET, }, { .name = "imx27-fec", .driver_data = 0, }, { .name = "imx28-fec", .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, }, { .name = "imx6q-fec", .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | FEC_QUIRK_HAS_VLAN | FEC_QUIRK_RX_SHIFT16, }, { .name = "mvf600-fec", .driver_data = FEC_QUIRK_ENET_MAC, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, fec_devtype); enum imx_fec_type { IMX25_FEC = 1, /* runs on i.mx25/50/53 */ IMX27_FEC, /* runs on i.mx27/35/51 */ IMX28_FEC, IMX6Q_FEC, MVF600_FEC, }; static const struct of_device_id fec_dt_ids[] = { { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fec_dt_ids); static unsigned char macaddr[ETH_ALEN]; module_param_array(macaddr, byte, NULL, 0); MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); #if defined(CONFIG_M5272) /* * Some hardware gets it MAC address out of local flash memory. * if this is non-zero then assume it is the address to get MAC from. */ #if defined(CONFIG_NETtel) #define FEC_FLASHMAC 0xf0006006 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) #define FEC_FLASHMAC 0xf0006000 #elif defined(CONFIG_CANCam) #define FEC_FLASHMAC 0xf0020000 #elif defined (CONFIG_M5272C3) #define FEC_FLASHMAC (0xffe04000 + 4) #elif defined(CONFIG_MOD5272) #define FEC_FLASHMAC 0xffc0406b #else #define FEC_FLASHMAC 0 #endif #endif /* CONFIG_M5272 */ /* Minimum TX ring size when using NETIF_F_SG */ #define TX_RING_SIZE_MIN_SG (2 * (MAX_SKB_FRAGS + 1)) /* Interrupt events/masks. */ #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. */ #define PKT_MAXBUF_SIZE 1522 #define PKT_MINBUF_SIZE 64 #define PKT_MAXBLR_SIZE 1536 /* FEC receive acceleration */ #define FEC_RACC_IPDIS (1 << 1) #define FEC_RACC_PRODIS (1 << 2) #define FEC_RACC_SHIFT16 BIT(7) #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) /* * The 5270/5271/5280/5282/532x RX control register also contains maximum frame * size bits. Other FEC hardware does not, so we need to take that into * account when setting it. */ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) #else #define OPT_FRAME_SIZE 0 #endif /* FEC MII MMFR bits definition */ #define FEC_MMFR_ST (1 << 30) #define FEC_MMFR_OP_READ (2 << 28) #define FEC_MMFR_OP_WRITE (1 << 28) #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) #define FEC_MMFR_TA (2 << 16) #define FEC_MMFR_DATA(v) (v & 0xffff) #define FEC_MII_TIMEOUT 30000 /* us */ /* Transmitter timeout */ #define TX_TIMEOUT (2 * HZ) /* pause mode/flag */ #define FEC_PAUSE_FLAG_AUTONEG BIT(0) #define FEC_PAUSE_FLAG_RX BIT(1) #define FEC_PAUSE_FLAG_TX BIT(2) /* flags */ #define FEC_FLAG_BUFDESC_EX BIT(0) #define FEC_FLAG_RX_CSUM BIT(1) #define FEC_FLAG_RX_VLAN BIT(2) static int mii_cnt; static unsigned copybreak = 200; module_param(copybreak, uint, 0644); MODULE_PARM_DESC(copybreak, "Maximum size of packet that is copied to a new buffer on receive"); static unsigned long total_stopped; module_param(total_stopped, ulong, 0644); static unsigned long start_latency; module_param(start_latency, ulong, 0644); static bool fec_enet_rx_zerocopy(struct fec_enet_private *fep, unsigned pktlen) { #ifndef CONFIG_M5272 if (fep->quirks & FEC_QUIRK_RX_SHIFT16 && pktlen >= copybreak) return true; #endif return false; } static union bufdesc_u * fec_enet_tx_get(unsigned int index, struct fec_enet_private *fep) { union bufdesc_u *base = fep->tx_bd_base; union bufdesc_u *bdp; if (fep->flags & FEC_FLAG_BUFDESC_EX) bdp = (union bufdesc_u *)(&base->ebd + index); else bdp = (union bufdesc_u *)(&base->bd + index); return bdp; } static union bufdesc_u * fec_enet_rx_get(unsigned int index, struct fec_enet_private *fep) { union bufdesc_u *base = fep->rx_bd_base; union bufdesc_u *bdp; index &= fep->rx_ring_size - 1; if (fep->flags & FEC_FLAG_BUFDESC_EX) bdp = (union bufdesc_u *)(&base->ebd + index); else bdp = (union bufdesc_u *)(&base->bd + index); return bdp; } static unsigned ring_free(unsigned ins, unsigned rem, unsigned size) { int num = rem - ins; return num < 0 ? num + size : num; } static void *swap_buffer(void *bufaddr, int len) { int i; unsigned int *buf = bufaddr; for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) *buf = cpu_to_be32(*buf); return bufaddr; } static void fec_dump(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); union bufdesc_u *bdp; unsigned int index = 0; netdev_info(ndev, "TX ring dump\n"); pr_info("Nr SC addr len SKB\n"); for (index = 0; index < fep->tx_ring_size; index++) { bdp = fec_enet_tx_get(index, fep); pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p", index, index == fep->tx_next ? 'S' : ' ', index == fep->tx_dirty ? 'H' : ' ', bdp->bd.cbd_sc, bdp->bd.cbd_bufaddr, bdp->bd.cbd_datlen, fep->tx_skbuff[index]); if (fep->flags & FEC_FLAG_BUFDESC_EX) pr_cont(" %08lx", bdp->ebd.cbd_esc); pr_cont("\n"); } } static int fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) { int csum_start; /* Only run for packets requiring a checksum. */ if (skb->ip_summed != CHECKSUM_PARTIAL) return 0; csum_start = skb_checksum_start_offset(skb); if (csum_start + skb->csum_offset > skb_headlen(skb)) { netdev_err(ndev, "checksum outside skb head: headlen %u start %u offset %u\n", skb_headlen(skb), csum_start, skb->csum_offset); return -1; } if (unlikely(skb_cow_head(skb, 0))) return -1; *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; return 0; } static void fec_enet_tx_unmap(unsigned index, union bufdesc_u *bdp, struct fec_enet_private *fep) { dma_addr_t addr = bdp->bd.cbd_bufaddr; size_t length = bdp->bd.cbd_datlen; if (fep->tx_page_map[index]) dma_unmap_page(&fep->pdev->dev, addr, length, DMA_TO_DEVICE); else dma_unmap_single(&fep->pdev->dev, addr, length, DMA_TO_DEVICE); } static bool fec_enet_txq_submit_frag_skb(struct sk_buff *skb, struct net_device *ndev, unsigned int estatus) { struct fec_enet_private *fep = netdev_priv(ndev); const struct platform_device_id *id_entry = platform_get_device_id(fep->pdev); union bufdesc_u *bdp; int nr_frags = skb_shinfo(skb)->nr_frags; unsigned short status; const skb_frag_t *this_frag; unsigned int frag_len, index = fep->tx_next; dma_addr_t addr; int frag, i; for (frag = 0; frag < nr_frags; frag++) { this_frag = &skb_shinfo(skb)->frags[frag]; if (++index >= fep->tx_ring_size) index = 0; frag_len = skb_frag_size(this_frag); /* If the alignment is unsuitable, we need to bounce. */ if (this_frag->page_offset & FEC_ALIGNMENT || id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) { unsigned char *bounce = fep->tx_bounce[index]; memcpy(bounce, skb_frag_address(this_frag), frag_len); if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) swap_buffer(bounce, frag_len); addr = dma_map_single(&fep->pdev->dev, bounce, frag_len, DMA_TO_DEVICE); fep->tx_page_map[index] = 0; } else { addr = skb_frag_dma_map(&fep->pdev->dev, this_frag, 0, frag_len, DMA_TO_DEVICE); fep->tx_page_map[index] = 1; } if (dma_mapping_error(&fep->pdev->dev, addr)) goto dma_mapping_error; status = BD_ENET_TX_TC | BD_ENET_TX_READY; /* Handle the last BD specially */ if (frag == nr_frags - 1) status |= BD_ENET_TX_INTR | BD_ENET_TX_LAST; bdp = fec_enet_tx_get(index, fep); if (fep->flags & FEC_FLAG_BUFDESC_EX) { bdp->ebd.cbd_bdu = 0; bdp->ebd.cbd_esc = estatus; } bdp->bd.cbd_bufaddr = addr; bdp->bd.cbd_datlen = frag_len; bdp->bd.cbd_sc = (bdp->bd.cbd_sc & ~BD_ENET_TX_STATS) | status; } fep->tx_next = index; return true; dma_mapping_error: index = fep->tx_next; for (i = 0; i < frag; i++) { if (++index >= fep->tx_ring_size) index = 0; bdp = fec_enet_tx_get(index, fep); fec_enet_tx_unmap(index, bdp, fep); } return false; } static bool fec_enet_txq_submit_skb(struct sk_buff *skb, struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); union bufdesc_u *bdp; void *bufaddr; dma_addr_t addr; unsigned short status; unsigned int index, buflen, estatus; if (fep->start_ns) { unsigned delta = sched_clock() - fep->start_ns; if (start_latency == 0 && delta < 1000000) WARN_ON(1); if (delta < 1000000) start_latency += delta; fep->start_ns = 0; } /* Protocol checksum off-load for TCP and UDP. */ if (fec_enet_clear_csum(skb, ndev)) return false; /* Set buffer length and buffer pointer */ bufaddr = skb->data; buflen = skb_headlen(skb); index = fep->tx_next; /* * On some FEC implementations data must be aligned on * 4-byte boundaries. Use bounce buffers to copy data * and get it aligned. Ugh. */ if (((unsigned long) bufaddr) & FEC_ALIGNMENT || fep->quirks & FEC_QUIRK_SWAP_FRAME) { memcpy(fep->tx_bounce[index], skb->data, buflen); bufaddr = fep->tx_bounce[index]; if (fep->quirks & FEC_QUIRK_SWAP_FRAME) swap_buffer(bufaddr, buflen); } /* Push the data cache so the CPM does not get stale memory data. */ addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); if (dma_mapping_error(&fep->pdev->dev, addr)) goto release; bdp = fec_enet_tx_get(index, fep); /* Fill in a Tx ring entry */ bdp->bd.cbd_datlen = buflen; bdp->bd.cbd_bufaddr = addr; fep->tx_page_map[index] = 0; estatus = BD_ENET_TX_INT; if (fep->flags & FEC_FLAG_BUFDESC_EX) { if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && fep->hwts_tx_en)) { estatus |= BD_ENET_TX_TS; skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; } if (skb->ip_summed == CHECKSUM_PARTIAL) estatus |= BD_ENET_TX_PINS; bdp->ebd.cbd_bdu = 0; bdp->ebd.cbd_esc = estatus; } status = BD_ENET_TX_READY | BD_ENET_TX_TC; if (skb_shinfo(skb)->nr_frags) { if (!fec_enet_txq_submit_frag_skb(skb, ndev, estatus)) goto unmap; } else { status |= BD_ENET_TX_INTR | BD_ENET_TX_LAST; } index = fep->tx_next; /* Save skb pointer */ fep->tx_skbuff[index] = skb; /* * We need the preceding stores to the descriptor to complete * before updating the status field, which hands it over to the * hardware. The corresponding rmb() is "in the hardware". */ wmb(); /* Send it on its way. Tell FEC it's ready, interrupt when done, * it's the last BD of the frame, and to put the CRC on the end. */ bdp->bd.cbd_sc = status | (bdp->bd.cbd_sc & BD_ENET_TX_WRAP); skb_tx_timestamp(skb); netdev_sent_queue(ndev, skb->len); if (++index >= fep->tx_ring_size) index = 0; fep->tx_next = index; /* Trigger transmission start */ if (readl(fep->hwp + FEC_X_DES_ACTIVE) == 0) writel(0, fep->hwp + FEC_X_DES_ACTIVE); return true; unmap: fec_enet_tx_unmap(index, bdp, fep); release: if (net_ratelimit()) netdev_err(ndev, "Tx DMA memory map failed\n"); return false; } static netdev_tx_t fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); int nr_frags = skb_shinfo(skb)->nr_frags; if (ring_free(fep->tx_next, fep->tx_dirty, fep->tx_ring_size) < 1 + nr_frags) { /* Ooops. All transmit buffers are full. Bail out. * This should not happen, since ndev->tbusy should be set. */ if (net_ratelimit()) netdev_err(ndev, "tx queue full!\n"); return NETDEV_TX_BUSY; } if (!fec_enet_txq_submit_skb(skb, ndev)) { dev_kfree_skb_any(skb); return NETDEV_TX_OK; } if (ring_free(fep->tx_next, fep->tx_dirty, fep->tx_ring_size) < fep->tx_min) { fep->stop_ns = sched_clock(); netif_stop_queue(ndev); } return NETDEV_TX_OK; } /* Init RX & TX buffer descriptors */ static void fec_enet_bd_init(struct net_device *dev) { struct fec_enet_private *fep = netdev_priv(dev); union bufdesc_u *bdp; unsigned int i; /* Initialize the receive buffer descriptors. */ for (i = 0; i < fep->rx_ring_size; i++) { bdp = fec_enet_rx_get(i, fep); /* Initialize the BD for every fragment in the page. */ if (bdp->bd.cbd_bufaddr) bdp->bd.cbd_sc = BD_ENET_RX_EMPTY; else bdp->bd.cbd_sc = 0; if (i == fep->rx_ring_size - 1) bdp->bd.cbd_sc |= BD_SC_WRAP; } fep->rx_next = 0; /* ...and the same for transmit */ for (i = 0; i < fep->tx_ring_size; i++) { bdp = fec_enet_tx_get(i, fep); /* Initialize the BD for every fragment in the page. */ if (i == fep->tx_ring_size - 1) bdp->bd.cbd_sc = BD_SC_WRAP; else bdp->bd.cbd_sc = 0; if (bdp->bd.cbd_bufaddr) fec_enet_tx_unmap(i, bdp, fep); bdp->bd.cbd_bufaddr = 0; if (fep->tx_skbuff[i]) { dev_kfree_skb_any(fep->tx_skbuff[i]); fep->tx_skbuff[i] = NULL; } } fep->tx_next = 0; fep->tx_dirty = fep->tx_ring_size - 1; } /* * This function is called to start or restart the FEC during a link * change, transmit timeout, or to reconfigure the FEC. The network * packet processing for this device must be stopped before this call. */ static void fec_restart(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); u32 val; u32 temp_mac[2]; u32 rcntl = OPT_FRAME_SIZE | 0x04; u32 ecntl = 0x2; /* ETHEREN */ /* Whack a reset. We should wait for this. */ writel(1, fep->hwp + FEC_ECNTRL); udelay(10); /* * enet-mac reset will reset mac address registers too, * so need to reconfigure it. */ if (fep->quirks & FEC_QUIRK_ENET_MAC) { memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); } /* Clear any outstanding interrupt. */ writel(0xffc00000, fep->hwp + FEC_IEVENT); /* Set maximum receive buffer size. */ writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); if (fep->rx_bd_base) fec_enet_bd_init(ndev); netdev_reset_queue(ndev); /* Set receive and transmit descriptor base. */ writel(fep->rx_bd_dma, fep->hwp + FEC_R_DES_START); writel(fep->tx_bd_dma, fep->hwp + FEC_X_DES_START); /* Enable MII mode */ if (fep->full_duplex == DUPLEX_FULL) { /* FD enable */ writel(0x04, fep->hwp + FEC_X_CNTRL); } else { /* No Rcv on Xmit */ rcntl |= 0x02; writel(0x0, fep->hwp + FEC_X_CNTRL); } /* Set MII speed */ writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); #if !defined(CONFIG_M5272) /* set RX checksum */ val = readl(fep->hwp + FEC_RACC); if (fep->quirks & FEC_QUIRK_RX_SHIFT16) val |= FEC_RACC_SHIFT16; if (fep->flags & FEC_FLAG_RX_CSUM) val |= FEC_RACC_OPTIONS; else val &= ~FEC_RACC_OPTIONS; writel(val, fep->hwp + FEC_RACC); #endif /* * The phy interface and speed need to get configured * differently on enet-mac. */ if (fep->quirks & FEC_QUIRK_ENET_MAC) { /* Enable flow control and length check */ rcntl |= 0x40000000; /* RGMII, RMII or MII */ if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) rcntl |= (1 << 6); else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) rcntl |= (1 << 8); else rcntl &= ~(1 << 8); /* 1G, 100M or 10M */ if (fep->phy_dev) { if (fep->phy_dev->speed == SPEED_1000) ecntl |= (1 << 5); else if (fep->phy_dev->speed == SPEED_100) rcntl &= ~(1 << 9); else rcntl |= (1 << 9); } } else { #ifdef FEC_MIIGSK_ENR if (fep->quirks & FEC_QUIRK_USE_GASKET) { u32 cfgr; /* disable the gasket and wait */ writel(0, fep->hwp + FEC_MIIGSK_ENR); while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) udelay(1); /* * configure the gasket: * RMII, 50 MHz, no loopback, no echo * MII, 25 MHz, no loopback, no echo */ cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); /* re-enable the gasket */ writel(2, fep->hwp + FEC_MIIGSK_ENR); } #endif } #if !defined(CONFIG_M5272) if (fep->full_duplex == DUPLEX_FULL) { /* * Configure pause modes according to the current status. * Must only be enabled for full duplex links. */ if (fep->pause_mode & FEC_PAUSE_FLAG_RX) rcntl |= FEC_ENET_FCE; if (fep->pause_mode & FEC_PAUSE_FLAG_TX) { /* set FIFO threshold parameter to reduce overrun */ writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); /* OPD */ writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); } } #endif /* !defined(CONFIG_M5272) */ writel(rcntl, fep->hwp + FEC_R_CNTRL); /* Setup multicast filter. */ set_multicast_list(ndev); #ifndef CONFIG_M5272 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); writel(0, fep->hwp + FEC_HASH_TABLE_LOW); #endif if (fep->quirks & FEC_QUIRK_ENET_MAC) { /* enable ENET endian swap */ ecntl |= (1 << 8); /* enable ENET store and forward mode */ writel(1 << 8, fep->hwp + FEC_X_WMRK); } if (fep->flags & FEC_FLAG_BUFDESC_EX) ecntl |= (1 << 4); #ifndef CONFIG_M5272 /* Enable the MIB statistic event counters */ writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); #endif /* And last, enable the transmit and receive processing */ writel(ecntl, fep->hwp + FEC_ECNTRL); writel(0, fep->hwp + FEC_R_DES_ACTIVE); if (fep->flags & FEC_FLAG_BUFDESC_EX) fec_ptp_start_cyclecounter(ndev); /* Enable interrupts we wish to service */ writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); } static void fec_stop(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); /* We cannot expect a graceful transmit stop without link !!! */ if (fep->link) { writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ udelay(10); if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) netdev_err(ndev, "Graceful transmit stop did not complete!\n"); } /* Whack a reset. We should wait for this. */ writel(1, fep->hwp + FEC_ECNTRL); udelay(10); writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); /* We have to keep ENET enabled to have MII interrupt stay working */ if (fep->quirks & FEC_QUIRK_ENET_MAC) { writel(2, fep->hwp + FEC_ECNTRL); writel(rmii_mode, fep->hwp + FEC_R_CNTRL); } } static void fec_timeout(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); fec_dump(ndev); ndev->stats.tx_errors++; schedule_work(&fep->tx_timeout_work); } static void fec_enet_timeout_work(struct work_struct *work) { struct fec_enet_private *fep = container_of(work, struct fec_enet_private, tx_timeout_work); struct net_device *ndev = fep->netdev; rtnl_lock(); if (netif_device_present(ndev) || netif_running(ndev)) { mutex_lock(&fep->mutex); napi_disable(&fep->napi); netif_tx_lock_bh(ndev); fec_restart(ndev); netif_wake_queue(ndev); netif_tx_unlock_bh(ndev); napi_enable(&fep->napi); mutex_unlock(&fep->mutex); } rtnl_unlock(); } static void fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, struct skb_shared_hwtstamps *hwtstamps) { unsigned long flags; u64 ns; spin_lock_irqsave(&fep->tmreg_lock, flags); ns = timecounter_cyc2time(&fep->tc, ts); spin_unlock_irqrestore(&fep->tmreg_lock, flags); memset(hwtstamps, 0, sizeof(*hwtstamps)); hwtstamps->hwtstamp = ns_to_ktime(ns); } static void noinline fec_enet_tx(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); union bufdesc_u *bdp; struct sk_buff *skb; unsigned int index = fep->tx_dirty; unsigned int pkts_compl, bytes_compl; pkts_compl = bytes_compl = 0; do { unsigned status, cbd_esc; if (++index >= fep->tx_ring_size) index = 0; /* current queue is empty */ if (index == fep->tx_next) break; bdp = fec_enet_tx_get(index, fep); status = bdp->bd.cbd_sc; if (status & BD_ENET_TX_READY) break; skb = fep->tx_skbuff[index]; fep->tx_skbuff[index] = NULL; fec_enet_tx_unmap(index, bdp, fep); if (!skb) continue; /* Check for errors. */ if (fep->flags & FEC_FLAG_BUFDESC_EX) { cbd_esc = bdp->ebd.cbd_esc; if (cbd_esc & BD_ENET_TX_TXE) { ndev->stats.tx_errors++; if (cbd_esc & BD_ENET_TX_EE) { /* excess collision */ ndev->stats.collisions += 16; ndev->stats.tx_aborted_errors++; } if (cbd_esc & BD_ENET_TX_LCE) /* late collision error */ ndev->stats.tx_window_errors++; if (cbd_esc & (BD_ENET_TX_UE | BD_ENET_TX_FE | BD_ENET_TX_OE)) ndev->stats.tx_fifo_errors++; goto next; } } else { if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN | BD_ENET_TX_CSL)) { ndev->stats.tx_errors++; if (status & BD_ENET_TX_HB) /* No heartbeat */ ndev->stats.tx_heartbeat_errors++; if (status & BD_ENET_TX_LC) /* Late collision */ ndev->stats.tx_window_errors++; if (status & BD_ENET_TX_RL) /* Retrans limit */ ndev->stats.tx_aborted_errors++; if (status & BD_ENET_TX_UN) /* Underrun */ ndev->stats.tx_fifo_errors++; if (status & BD_ENET_TX_CSL) /* Carrier lost */ ndev->stats.tx_carrier_errors++; goto next; } } ndev->stats.tx_packets++; ndev->stats.tx_bytes += skb->len; if (fep->flags & FEC_FLAG_BUFDESC_EX && unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { struct skb_shared_hwtstamps shhwtstamps; fec_enet_hwtstamp(fep, bdp->ebd.ts, &shhwtstamps); skb_tstamp_tx(skb, &shhwtstamps); } /* Deferred means some collisions occurred during transmit, * but we eventually sent the packet OK. */ if (status & BD_ENET_TX_DEF) ndev->stats.collisions++; next: pkts_compl++; bytes_compl += skb->len; /* Free the sk buffer associated with this last transmit */ dev_kfree_skb_any(skb); fep->tx_dirty = index; } while (1); netdev_completed_queue(ndev, pkts_compl, bytes_compl); /* ERR006538: Keep the transmitter going */ if (index != fep->tx_next && readl(fep->hwp + FEC_X_DES_ACTIVE) == 0) writel(0, fep->hwp + FEC_X_DES_ACTIVE); if (netif_queue_stopped(ndev) && ring_free(fep->tx_next, fep->tx_dirty, fep->tx_ring_size) >= fep->tx_min) { total_stopped += sched_clock() - fep->stop_ns; if (start_latency == 0) { // WARN_ON(1); extern int __trace2; __trace2 = 1; } netif_wake_queue(ndev); fep->start_ns = sched_clock(); } } static void fec_enet_receive(struct sk_buff *skb, union bufdesc_u *bdp, struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); skb->protocol = eth_type_trans(skb, ndev); /* Get receive timestamp from the skb */ if (fep->hwts_rx_en && fep->flags & FEC_FLAG_BUFDESC_EX) fec_enet_hwtstamp(fep, bdp->ebd.ts, skb_hwtstamps(skb)); if (fep->flags & FEC_FLAG_RX_CSUM) { if (!(bdp->ebd.cbd_esc & FLAG_RX_CSUM_ERROR)) { /* don't check it */ skb->ip_summed = CHECKSUM_UNNECESSARY; } else { skb_checksum_none_assert(skb); } } napi_gro_receive(&fep->napi, skb); } static void noinline fec_enet_receive_copy(unsigned pkt_len, unsigned index, union bufdesc_u *bdp, struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); struct sk_buff *skb; unsigned char *data; bool vlan_packet_rcvd = false; /* * Detect the presence of the VLAN tag, and adjust * the packet length appropriately. */ if (fep->flags & FEC_FLAG_RX_VLAN && bdp->ebd.cbd_esc & BD_ENET_RX_VLAN) { pkt_len -= VLAN_HLEN; vlan_packet_rcvd = true; } /* This does 16 byte alignment, exactly what we need. */ skb = netdev_alloc_skb(ndev, pkt_len + NET_IP_ALIGN); if (unlikely(!skb)) { ndev->stats.rx_dropped++; return; } dma_sync_single_for_cpu(&fep->pdev->dev, bdp->bd.cbd_bufaddr, FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); data = fep->rx_skbuff[index]->data; #ifndef CONFIG_M5272 /* * If we have enabled this feature, we need to discard * the two bytes at the beginning of the packet before * copying it. */ if (fep->quirks & FEC_QUIRK_RX_SHIFT16) { pkt_len -= 2; data += 2; } #endif if (fep->quirks & FEC_QUIRK_SWAP_FRAME) swap_buffer(data, pkt_len); skb_reserve(skb, NET_IP_ALIGN); skb_put(skb, pkt_len); /* Make room */ /* If this is a VLAN packet remove the VLAN Tag */ if (vlan_packet_rcvd) { struct vlan_hdr *vlan = (struct vlan_hdr *)(data + ETH_HLEN); __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(vlan->h_vlan_TCI)); /* Extract the frame data without the VLAN header. */ skb_copy_to_linear_data(skb, data, 2 * ETH_ALEN); skb_copy_to_linear_data_offset(skb, 2 * ETH_ALEN, data + 2 * ETH_ALEN + VLAN_HLEN, pkt_len - 2 * ETH_ALEN); } else { skb_copy_to_linear_data(skb, data, pkt_len); } dma_sync_single_for_device(&fep->pdev->dev, bdp->bd.cbd_bufaddr, FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); fec_enet_receive(skb, bdp, ndev); } static void noinline fec_enet_receive_nocopy(unsigned pkt_len, unsigned index, union bufdesc_u *bdp, struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); struct sk_buff *skb, *skb_new; unsigned char *data; dma_addr_t addr; skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); if (!skb_new) { ndev->stats.rx_dropped++; return; } addr = dma_map_single(&fep->pdev->dev, skb_new->data, FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); if (dma_mapping_error(&fep->pdev->dev, addr)) { dev_kfree_skb(skb_new); ndev->stats.rx_dropped++; return; } /* We have the new skb, so proceed to deal with the received data. */ dma_unmap_single(&fep->pdev->dev, bdp->bd.cbd_bufaddr, FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); skb = fep->rx_skbuff[index]; /* Now subsitute in the new skb */ fep->rx_skbuff[index] = skb_new; bdp->bd.cbd_bufaddr = addr; /* * Update the skb length according to the raw packet length. * Then remove the two bytes of additional padding. */ skb_put(skb, pkt_len); data = skb_pull_inline(skb, 2); if (fep->quirks & FEC_QUIRK_SWAP_FRAME) swap_buffer(data, skb->len); /* * Now juggle things for the VLAN tag - if the hardware * flags this as present, we need to read the tag, and * then shuffle the ethernet addresses up. */ if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX && bdp->ebd.cbd_esc & BD_ENET_RX_VLAN) { struct vlan_hdr *vlan = (struct vlan_hdr *)(data + ETH_HLEN); __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(vlan->h_vlan_TCI)); memmove(data + VLAN_HLEN, data, 2 * ETH_ALEN); skb_pull_inline(skb, VLAN_HLEN); } fec_enet_receive(skb, bdp, ndev); } /* During a receive, the rx_next points to the current incoming buffer. * When we update through the ring, if the next incoming buffer has * not been given to the system, we just set the empty indicator, * effectively tossing the packet. */ static int noinline fec_enet_rx(struct net_device *ndev, int budget) { struct fec_enet_private *fep = netdev_priv(ndev); int pkt_received = 0; unsigned int index = fep->rx_next; #ifdef CONFIG_M532x flush_cache_all(); #endif /* First, grab all of the stats for the incoming packet. * These get messed up if we get called due to a busy condition. */ do { union bufdesc_u *bdp = fec_enet_rx_get(index, fep); unsigned status, pkt_len; status = bdp->bd.cbd_sc; if (status & BD_ENET_RX_EMPTY) break; if (pkt_received >= budget) break; pkt_received++; /* Since we have allocated space to hold a complete frame, * the last indicator should be set. */ if ((status & BD_ENET_RX_LAST) == 0) netdev_err(ndev, "rcv is not +last\n"); writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); /* Check for errors. */ if (status & BD_ENET_RX_ERROR) { ndev->stats.rx_errors++; if (status & BD_ENET_RX_OV) { /* * FIFO overrun - stored frame and the other * status (M, LG, NO, CR, CL) are invalid. * Although docs say these status bits will * be zero, it has been observed on iMX6 FEC * that OV is always accompanied by CR set. */ ndev->stats.rx_fifo_errors++; } else if (status & BD_ENET_RX_CL) { /* * Report late collisions as a frame error. * On this error, the BD is closed, but we * don't know what we have in the buffer. * So, just drop this frame on the floor. */ ndev->stats.rx_frame_errors++; } else { if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) /* Frame too long or too short. */ ndev->stats.rx_length_errors++; if (status & BD_ENET_RX_NO) /* Frame alignment */ ndev->stats.rx_frame_errors++; if (status & BD_ENET_RX_CR) /* CRC Error */ ndev->stats.rx_crc_errors++; } goto rx_processing_done; } /* Process the incoming frame. */ ndev->stats.rx_packets++; /* * The packet length includes FCS, but we don't want * to include that when passing upstream as it messes * up bridging applications. */ pkt_len = bdp->bd.cbd_datlen - 4; ndev->stats.rx_bytes += pkt_len; if (fec_enet_rx_zerocopy(fep, pkt_len)) { fec_enet_receive_nocopy(pkt_len, index, bdp, ndev); } else { fec_enet_receive_copy(pkt_len, index, bdp, ndev); } rx_processing_done: if (fep->flags & FEC_FLAG_BUFDESC_EX) { bdp->ebd.cbd_esc = BD_ENET_RX_INT; bdp->ebd.cbd_prot = 0; bdp->ebd.cbd_bdu = 0; } /* * Ensure that the previous writes have completed before * the status update becomes visible. */ wmb(); /* Clear the status flags for this buffer */ status &= ~BD_ENET_RX_STATS; /* Mark the buffer empty */ status |= BD_ENET_RX_EMPTY; bdp->bd.cbd_sc = status; /* Doing this here will keep the FEC running while we process * incoming frames. On a heavily loaded network, we should be * able to keep up at the expense of system resources. */ writel(0, fep->hwp + FEC_R_DES_ACTIVE); if (++index >= fep->rx_ring_size) index = 0; } while (1); fep->rx_next = index; return pkt_received; } static irqreturn_t fec_enet_interrupt(int irq, void *dev_id) { struct net_device *ndev = dev_id; struct fec_enet_private *fep = netdev_priv(ndev); const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF; uint int_events; irqreturn_t ret = IRQ_NONE; int_events = readl(fep->hwp + FEC_IEVENT); writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT); if (int_events & napi_mask) { ret = IRQ_HANDLED; /* Disable the NAPI interrupts */ writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); napi_schedule(&fep->napi); } if (int_events & FEC_ENET_MII) { ret = IRQ_HANDLED; complete(&fep->mdio_done); } return ret; } static int fec_enet_rx_napi(struct napi_struct *napi, int budget) { struct net_device *ndev = napi->dev; struct fec_enet_private *fep = netdev_priv(ndev); int pkts; /* * Clear any pending transmit or receive interrupts before * processing the rings to avoid racing with the hardware. */ writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT); pkts = fec_enet_rx(ndev, budget); fec_enet_tx(ndev); if (pkts < budget) { napi_complete(napi); writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); } return pkts; } /* ------------------------------------------------------------------------- */ static void fec_get_mac(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); unsigned char *iap, tmpaddr[ETH_ALEN]; /* * try to get mac address in following order: * * 1) module parameter via kernel command line in form * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 */ iap = macaddr; /* * 2) from device tree data */ if (!is_valid_ether_addr(iap)) { struct device_node *np = fep->pdev->dev.of_node; if (np) { const char *mac = of_get_mac_address(np); if (mac) iap = (unsigned char *) mac; } } /* * 3) from flash or fuse (via platform data) */ if (!is_valid_ether_addr(iap)) { #ifdef CONFIG_M5272 if (FEC_FLASHMAC) iap = (unsigned char *)FEC_FLASHMAC; #else if (pdata) iap = (unsigned char *)&pdata->mac; #endif } /* * 4) FEC mac registers set by bootloader */ if (!is_valid_ether_addr(iap)) { *((__be32 *) &tmpaddr[0]) = cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); *((__be16 *) &tmpaddr[4]) = cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); iap = &tmpaddr[0]; } /* * 5) random mac address */ if (!is_valid_ether_addr(iap)) { /* Report it and use a random ethernet address instead */ netdev_err(ndev, "Invalid MAC address: %pM\n", iap); eth_hw_addr_random(ndev); netdev_info(ndev, "Using random MAC address: %pM\n", ndev->dev_addr); return; } memcpy(ndev->dev_addr, iap, ETH_ALEN); /* Adjust MAC if using macaddr */ if (iap == macaddr) ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; } /* ------------------------------------------------------------------------- */ /* * Phy section */ static void fec_enet_adjust_link(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); struct phy_device *phy_dev = fep->phy_dev; int status_change = 0; /* Prevent a state halted on mii error */ if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { phy_dev->state = PHY_RESUMING; return; } /* * If the netdev is down, or is going down, we're not interested * in link state events, so just mark our idea of the link as down * and ignore the event. */ if (!netif_running(ndev) || !netif_device_present(ndev)) { fep->link = 0; } else if (phy_dev->link) { if (!fep->link) { fep->link = phy_dev->link; status_change = 1; } if (fep->full_duplex != phy_dev->duplex) { fep->full_duplex = phy_dev->duplex; status_change = 1; } if (phy_dev->speed != fep->speed) { fep->speed = phy_dev->speed; status_change = 1; } if (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) { u32 lcl_adv = phy_dev->advertising; u32 rmt_adv = phy_dev->lp_advertising; unsigned mode = 0; if (lcl_adv & rmt_adv & ADVERTISED_Pause) { /* * Local Device Link Partner * Pause AsymDir Pause AsymDir Result * 1 X 1 X TX+RX */ mode = FEC_PAUSE_FLAG_TX | FEC_PAUSE_FLAG_RX; } else if (lcl_adv & rmt_adv & ADVERTISED_Asym_Pause) { /* * 0 1 1 1 RX * 1 1 0 1 TX */ if (rmt_adv & ADVERTISED_Pause) mode = FEC_PAUSE_FLAG_RX; else mode = FEC_PAUSE_FLAG_TX; } if (mode != fep->pause_mode) { fep->pause_mode = mode; status_change = 1; } } /* if any of the above changed restart the FEC */ if (status_change) { mutex_lock(&fep->mutex); napi_disable(&fep->napi); netif_tx_lock_bh(ndev); fec_restart(ndev); netif_wake_queue(ndev); netif_tx_unlock_bh(ndev); napi_enable(&fep->napi); mutex_unlock(&fep->mutex); } } else { if (fep->link) { mutex_lock(&fep->mutex); napi_disable(&fep->napi); netif_tx_lock_bh(ndev); fec_stop(ndev); netif_tx_unlock_bh(ndev); napi_enable(&fep->napi); mutex_unlock(&fep->mutex); fep->link = phy_dev->link; status_change = 1; } } if (status_change) phy_print_status(phy_dev); } static unsigned long fec_enet_mdio_op(struct fec_enet_private *fep, unsigned data) { unsigned long time_left; fep->mii_timeout = 0; init_completion(&fep->mdio_done); mutex_lock(&fep->mutex); /* start operation */ writel(data, fep->hwp + FEC_MII_DATA); /* wait for end of transfer */ time_left = wait_for_completion_timeout(&fep->mdio_done, usecs_to_jiffies(FEC_MII_TIMEOUT)); mutex_unlock(&fep->mutex); return time_left; } static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) { struct fec_enet_private *fep = bus->priv; if (fec_enet_mdio_op(fep, FEC_MMFR_ST | FEC_MMFR_OP_READ | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | FEC_MMFR_TA) == 0) { fep->mii_timeout = 1; netdev_err(fep->netdev, "MDIO read timeout\n"); return -ETIMEDOUT; } /* return value */ return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); } static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) { struct fec_enet_private *fep = bus->priv; if (fec_enet_mdio_op(fep, FEC_MMFR_ST | FEC_MMFR_OP_WRITE | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | FEC_MMFR_TA | FEC_MMFR_DATA(value)) == 0) { fep->mii_timeout = 1; netdev_err(fep->netdev, "MDIO write timeout\n"); return -ETIMEDOUT; } return 0; } static int fec_enet_clk_enable(struct net_device *ndev, bool enable) { struct fec_enet_private *fep = netdev_priv(ndev); int ret; if (enable) { ret = clk_prepare_enable(fep->clk_ahb); if (ret) return ret; ret = clk_prepare_enable(fep->clk_ipg); if (ret) goto failed_clk_ipg; if (fep->clk_enet_out) { ret = clk_prepare_enable(fep->clk_enet_out); if (ret) goto failed_clk_enet_out; } if (fep->clk_ptp) { mutex_lock(&fep->ptp_clk_mutex); ret = clk_prepare_enable(fep->clk_ptp); if (ret) { mutex_unlock(&fep->ptp_clk_mutex); goto failed_clk_ptp; } else { fep->ptp_clk_on = true; } mutex_unlock(&fep->ptp_clk_mutex); } } else { clk_disable_unprepare(fep->clk_ahb); clk_disable_unprepare(fep->clk_ipg); if (fep->clk_enet_out) clk_disable_unprepare(fep->clk_enet_out); if (fep->clk_ptp) { mutex_lock(&fep->ptp_clk_mutex); clk_disable_unprepare(fep->clk_ptp); fep->ptp_clk_on = false; mutex_unlock(&fep->ptp_clk_mutex); } } return 0; failed_clk_ptp: if (fep->clk_enet_out) clk_disable_unprepare(fep->clk_enet_out); failed_clk_enet_out: clk_disable_unprepare(fep->clk_ipg); failed_clk_ipg: clk_disable_unprepare(fep->clk_ahb); return ret; } static void fec_enet_phy_config(struct net_device *ndev) { #ifndef CONFIG_M5272 struct fec_enet_private *fep = netdev_priv(ndev); struct phy_device *phy = fep->phy_dev; unsigned pause = 0; /* * Pause advertisment logic is weird. We don't advertise the raw * "can tx" and "can rx" modes, but instead it is whether we support * symmetric flow or asymmetric flow. * * Symmetric flow means we can only support both transmit and receive * flow control frames together. Asymmetric flow means we can * independently control each. Note that there is no bit encoding * for "I can only receive flow control frames." */ if (fep->pause_flag & FEC_PAUSE_FLAG_RX) pause |= ADVERTISED_Asym_Pause | ADVERTISED_Pause; if (fep->pause_flag & FEC_PAUSE_FLAG_TX) pause |= ADVERTISED_Asym_Pause; pause &= phy->supported; pause |= phy->advertising & ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); phy->advertising = pause; #endif } static int fec_enet_mii_probe(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); struct phy_device *phy_dev = NULL; char mdio_bus_id[MII_BUS_ID_SIZE]; char phy_name[MII_BUS_ID_SIZE + 3]; int phy_id; int dev_id = fep->dev_id; fep->phy_dev = NULL; if (fep->phy_node) { phy_dev = of_phy_connect(ndev, fep->phy_node, &fec_enet_adjust_link, 0, fep->phy_interface); } else { /* check for attached phy */ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { if ((fep->mii_bus->phy_mask & (1 << phy_id))) continue; if (fep->mii_bus->phy_map[phy_id] == NULL) continue; if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) continue; if (dev_id--) continue; strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); break; } if (phy_id >= PHY_MAX_ADDR) { netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); phy_id = 0; } snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, fep->phy_interface); } if (IS_ERR(phy_dev)) { netdev_err(ndev, "could not attach to PHY\n"); return PTR_ERR(phy_dev); } /* mask with MAC supported features */ if (fep->quirks & FEC_QUIRK_HAS_GBIT) { phy_dev->supported &= PHY_GBIT_FEATURES; phy_dev->supported &= ~SUPPORTED_1000baseT_Half; #if !defined(CONFIG_M5272) phy_dev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; #endif } else phy_dev->supported &= PHY_BASIC_FEATURES; phy_dev->advertising = phy_dev->supported; fep->phy_dev = phy_dev; fep->link = 0; fep->full_duplex = 0; fec_enet_phy_config(ndev); netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), fep->phy_dev->irq); return 0; } static int fec_enet_mii_init(struct platform_device *pdev) { static struct mii_bus *fec0_mii_bus; struct net_device *ndev = platform_get_drvdata(pdev); struct fec_enet_private *fep = netdev_priv(ndev); struct device_node *node; int err = -ENXIO, i; /* * The dual fec interfaces are not equivalent with enet-mac. * Here are the differences: * * - fec0 supports MII & RMII modes while fec1 only supports RMII * - fec0 acts as the 1588 time master while fec1 is slave * - external phys can only be configured by fec0 * * That is to say fec1 can not work independently. It only works * when fec0 is working. The reason behind this design is that the * second interface is added primarily for Switch mode. * * Because of the last point above, both phys are attached on fec0 * mdio interface in board design, and need to be configured by * fec0 mii_bus. */ if ((fep->quirks & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { /* fec1 uses fec0 mii_bus */ if (mii_cnt && fec0_mii_bus) { fep->mii_bus = fec0_mii_bus; mii_cnt++; return 0; } return -ENOENT; } fep->mii_timeout = 0; /* * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) * * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 * Reference Manual has an error on this, and gets fixed on i.MX6Q * document. */ fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); if (fep->quirks & FEC_QUIRK_ENET_MAC) fep->phy_speed--; fep->phy_speed <<= 1; writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); fep->mii_bus = mdiobus_alloc(); if (fep->mii_bus == NULL) { err = -ENOMEM; goto err_out; } fep->mii_bus->name = "fec_enet_mii_bus"; fep->mii_bus->read = fec_enet_mdio_read; fep->mii_bus->write = fec_enet_mdio_write; snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", pdev->name, fep->dev_id + 1); fep->mii_bus->priv = fep; fep->mii_bus->parent = &pdev->dev; fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); if (!fep->mii_bus->irq) { err = -ENOMEM; goto err_out_free_mdiobus; } for (i = 0; i < PHY_MAX_ADDR; i++) fep->mii_bus->irq[i] = PHY_POLL; node = of_get_child_by_name(pdev->dev.of_node, "mdio"); if (node) { err = of_mdiobus_register(fep->mii_bus, node); of_node_put(node); } else { err = mdiobus_register(fep->mii_bus); } if (err) goto err_out_free_mdio_irq; mii_cnt++; /* save fec0 mii_bus */ if (fep->quirks & FEC_QUIRK_ENET_MAC) fec0_mii_bus = fep->mii_bus; return 0; err_out_free_mdio_irq: kfree(fep->mii_bus->irq); err_out_free_mdiobus: mdiobus_free(fep->mii_bus); err_out: return err; } static void fec_enet_mii_remove(struct fec_enet_private *fep) { if (--mii_cnt == 0) { mdiobus_unregister(fep->mii_bus); kfree(fep->mii_bus->irq); mdiobus_free(fep->mii_bus); } } static int fec_enet_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd) { struct fec_enet_private *fep = netdev_priv(ndev); struct phy_device *phydev = fep->phy_dev; if (!phydev) return -ENODEV; return phy_ethtool_gset(phydev, cmd); } static int fec_enet_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd) { struct fec_enet_private *fep = netdev_priv(ndev); struct phy_device *phydev = fep->phy_dev; if (!phydev) return -ENODEV; return phy_ethtool_sset(phydev, cmd); } static void fec_enet_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info) { struct fec_enet_private *fep = netdev_priv(ndev); strlcpy(info->driver, fep->pdev->dev.driver->name, sizeof(info->driver)); strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); } static int fec_enet_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) { struct fec_enet_private *fep = netdev_priv(ndev); if (fep->flags & FEC_FLAG_BUFDESC_EX) { info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | SOF_TIMESTAMPING_RX_SOFTWARE | SOF_TIMESTAMPING_SOFTWARE | SOF_TIMESTAMPING_TX_HARDWARE | SOF_TIMESTAMPING_RX_HARDWARE | SOF_TIMESTAMPING_RAW_HARDWARE; if (fep->ptp_clock) info->phc_index = ptp_clock_index(fep->ptp_clock); else info->phc_index = -1; info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | (1 << HWTSTAMP_FILTER_ALL); return 0; } else { return ethtool_op_get_ts_info(ndev, info); } } static void fec_enet_get_ringparam(struct net_device *ndev, struct ethtool_ringparam *ring) { struct fec_enet_private *fep = netdev_priv(ndev); ring->rx_max_pending = RX_RING_SIZE; ring->tx_max_pending = TX_RING_SIZE; ring->rx_pending = fep->rx_ring_size; ring->tx_pending = fep->tx_ring_size; } static int fec_enet_set_ringparam(struct net_device *ndev, struct ethtool_ringparam *ring) { struct fec_enet_private *fep = netdev_priv(ndev); unsigned rx, tx, tx_min; tx_min = ndev->features & NETIF_F_SG ? TX_RING_SIZE_MIN_SG : 16; rx = clamp_t(u32, ring->rx_pending, 16, RX_RING_SIZE); tx = clamp_t(u32, ring->tx_pending, tx_min, TX_RING_SIZE); if (tx == fep->tx_ring_size && rx == fep->rx_ring_size) return 0; /* Setting the ring size while the interface is down is easy */ if (!netif_running(ndev)) { fep->tx_ring_size = tx; fep->rx_ring_size = rx; } else { return -EINVAL; napi_disable(&fep->napi); netif_tx_lock_bh(ndev); fec_stop(ndev); /* reallocate ring */ fec_restart(ndev); netif_wake_queue(ndev); netif_tx_unlock_bh(ndev); napi_enable(&fep->napi); } return 0; } #if !defined(CONFIG_M5272) static void fec_enet_get_pauseparam(struct net_device *ndev, struct ethtool_pauseparam *pause) { struct fec_enet_private *fep = netdev_priv(ndev); pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; pause->rx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_RX) != 0; pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_TX) != 0; } static int fec_enet_set_pauseparam(struct net_device *ndev, struct ethtool_pauseparam *pause) { struct fec_enet_private *fep = netdev_priv(ndev); unsigned pause_flag, changed; struct phy_device *phy = fep->phy_dev; if (!phy) return -ENODEV; if (!(phy->supported & SUPPORTED_Pause)) return -EINVAL; if (!(phy->supported & SUPPORTED_Asym_Pause) && pause->rx_pause != pause->tx_pause) return -EINVAL; pause_flag = 0; if (pause->autoneg) pause_flag |= FEC_PAUSE_FLAG_AUTONEG; if (pause->rx_pause) pause_flag |= FEC_PAUSE_FLAG_RX; if (pause->tx_pause) pause_flag |= FEC_PAUSE_FLAG_TX; changed = fep->pause_flag ^ pause_flag; fep->pause_flag = pause_flag; /* configure the phy advertisment according to our new options */ fec_enet_phy_config(ndev); if (changed) { if (pause_flag & FEC_PAUSE_FLAG_AUTONEG) { if (netif_running(ndev)) phy_start_aneg(fep->phy_dev); } else { int adv, old_adv; /* * Even if we are not in autonegotiate mode, we * still update the phy with our capabilities so * our link parter can make the appropriate * decision. PHYLIB provides no way to do this. */ adv = phy_read(phy, MII_ADVERTISE); if (adv >= 0) { old_adv = adv; adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); if (phy->advertising & ADVERTISED_Pause) adv |= ADVERTISE_PAUSE_CAP; if (phy->advertising & ADVERTISED_Asym_Pause) adv |= ADVERTISE_PAUSE_ASYM; if (old_adv != adv) phy_write(phy, MII_ADVERTISE, adv); } /* Forced pause mode */ fep->pause_mode = fep->pause_flag; if (netif_running(ndev)) { mutex_lock(&fep->mutex); napi_disable(&fep->napi); netif_tx_lock_bh(ndev); fec_stop(ndev); fec_restart(ndev); netif_wake_queue(ndev); netif_tx_unlock_bh(ndev); napi_enable(&fep->napi); mutex_unlock(&fep->mutex); } } } return 0; } static const struct fec_stat { char name[ETH_GSTRING_LEN]; u16 offset; } fec_stats[] = { /* RMON TX */ { "tx_dropped", RMON_T_DROP }, { "tx_packets", RMON_T_PACKETS }, { "tx_broadcast", RMON_T_BC_PKT }, { "tx_multicast", RMON_T_MC_PKT }, { "tx_crc_errors", RMON_T_CRC_ALIGN }, { "tx_undersize", RMON_T_UNDERSIZE }, { "tx_oversize", RMON_T_OVERSIZE }, { "tx_fragment", RMON_T_FRAG }, { "tx_jabber", RMON_T_JAB }, { "tx_collision", RMON_T_COL }, { "tx_64byte", RMON_T_P64 }, { "tx_65to127byte", RMON_T_P65TO127 }, { "tx_128to255byte", RMON_T_P128TO255 }, { "tx_256to511byte", RMON_T_P256TO511 }, { "tx_512to1023byte", RMON_T_P512TO1023 }, { "tx_1024to2047byte", RMON_T_P1024TO2047 }, { "tx_GTE2048byte", RMON_T_P_GTE2048 }, { "tx_octets", RMON_T_OCTETS }, /* IEEE TX */ { "IEEE_tx_drop", IEEE_T_DROP }, { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, { "IEEE_tx_1col", IEEE_T_1COL }, { "IEEE_tx_mcol", IEEE_T_MCOL }, { "IEEE_tx_def", IEEE_T_DEF }, { "IEEE_tx_lcol", IEEE_T_LCOL }, { "IEEE_tx_excol", IEEE_T_EXCOL }, { "IEEE_tx_macerr", IEEE_T_MACERR }, { "IEEE_tx_cserr", IEEE_T_CSERR }, { "IEEE_tx_sqe", IEEE_T_SQE }, { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, /* RMON RX */ { "rx_packets", RMON_R_PACKETS }, { "rx_broadcast", RMON_R_BC_PKT }, { "rx_multicast", RMON_R_MC_PKT }, { "rx_crc_errors", RMON_R_CRC_ALIGN }, { "rx_undersize", RMON_R_UNDERSIZE }, { "rx_oversize", RMON_R_OVERSIZE }, { "rx_fragment", RMON_R_FRAG }, { "rx_jabber", RMON_R_JAB }, { "rx_64byte", RMON_R_P64 }, { "rx_65to127byte", RMON_R_P65TO127 }, { "rx_128to255byte", RMON_R_P128TO255 }, { "rx_256to511byte", RMON_R_P256TO511 }, { "rx_512to1023byte", RMON_R_P512TO1023 }, { "rx_1024to2047byte", RMON_R_P1024TO2047 }, { "rx_GTE2048byte", RMON_R_P_GTE2048 }, { "rx_octets", RMON_R_OCTETS }, /* IEEE RX */ { "IEEE_rx_drop", IEEE_R_DROP }, { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, { "IEEE_rx_crc", IEEE_R_CRC }, { "IEEE_rx_align", IEEE_R_ALIGN }, { "IEEE_rx_macerr", IEEE_R_MACERR }, { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, }; static void fec_enet_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) { struct fec_enet_private *fep = netdev_priv(dev); int i; for (i = 0; i < ARRAY_SIZE(fec_stats); i++) data[i] = readl(fep->hwp + fec_stats[i].offset); } static void fec_enet_get_strings(struct net_device *netdev, u32 stringset, u8 *data) { int i; switch (stringset) { case ETH_SS_STATS: for (i = 0; i < ARRAY_SIZE(fec_stats); i++) memcpy(data + i * ETH_GSTRING_LEN, fec_stats[i].name, ETH_GSTRING_LEN); break; } } static int fec_enet_get_sset_count(struct net_device *dev, int sset) { switch (sset) { case ETH_SS_STATS: return ARRAY_SIZE(fec_stats); default: return -EOPNOTSUPP; } } #endif /* !defined(CONFIG_M5272) */ static int fec_enet_nway_reset(struct net_device *dev) { struct fec_enet_private *fep = netdev_priv(dev); struct phy_device *phydev = fep->phy_dev; if (!phydev) return -ENODEV; return genphy_restart_aneg(phydev); } static const struct ethtool_ops fec_enet_ethtool_ops = { .get_settings = fec_enet_get_settings, .set_settings = fec_enet_set_settings, .get_drvinfo = fec_enet_get_drvinfo, .nway_reset = fec_enet_nway_reset, .get_link = ethtool_op_get_link, .get_ringparam = fec_enet_get_ringparam, .set_ringparam = fec_enet_set_ringparam, #ifndef CONFIG_M5272 .get_pauseparam = fec_enet_get_pauseparam, .set_pauseparam = fec_enet_set_pauseparam, .get_strings = fec_enet_get_strings, .get_ethtool_stats = fec_enet_get_ethtool_stats, .get_sset_count = fec_enet_get_sset_count, #endif .get_ts_info = fec_enet_get_ts_info, }; static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) { struct fec_enet_private *fep = netdev_priv(ndev); struct phy_device *phydev = fep->phy_dev; if (!netif_running(ndev)) return -EINVAL; if (!phydev) return -ENODEV; if (fep->flags & FEC_FLAG_BUFDESC_EX) { if (cmd == SIOCSHWTSTAMP) return fec_ptp_set(ndev, rq); if (cmd == SIOCGHWTSTAMP) return fec_ptp_get(ndev, rq); } return phy_mii_ioctl(phydev, rq, cmd); } static void fec_enet_free_buffers(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); unsigned int i; struct sk_buff *skb; union bufdesc_u *bdp; int rx_cbd_size, tx_cbd_size; for (i = 0; i < fep->rx_ring_size; i++) { bdp = fec_enet_rx_get(i, fep); skb = fep->rx_skbuff[i]; fep->rx_skbuff[i] = NULL; if (skb) { dma_unmap_single(&fep->pdev->dev, bdp->bd.cbd_bufaddr, FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); dev_kfree_skb(skb); } } for (i = 0; i < fep->tx_ring_size; i++) { bdp = fec_enet_tx_get(i, fep); if (bdp->bd.cbd_bufaddr) fec_enet_tx_unmap(i, bdp, fep); bdp->bd.cbd_bufaddr = 0; kfree(fep->tx_bounce[i]); fep->tx_bounce[i] = NULL; skb = fep->tx_skbuff[i]; fep->tx_skbuff[i] = NULL; dev_kfree_skb(skb); } rx_cbd_size = fep->rx_ring_size; tx_cbd_size = fep->tx_ring_size; if (fep->flags & FEC_FLAG_BUFDESC_EX) { rx_cbd_size *= sizeof(struct bufdesc_ex); tx_cbd_size *= sizeof(struct bufdesc_ex); } else { rx_cbd_size *= sizeof(struct bufdesc); tx_cbd_size *= sizeof(struct bufdesc); } dma_free_coherent(NULL, rx_cbd_size, fep->rx_bd_base, fep->rx_bd_dma); dma_free_coherent(NULL, tx_cbd_size, fep->tx_bd_base, fep->tx_bd_dma); } static int fec_enet_alloc_buffers(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); unsigned int i; struct sk_buff *skb; union bufdesc_u *rx_cbd_cpu, *tx_cbd_cpu; dma_addr_t rx_cbd_dma, tx_cbd_dma; union bufdesc_u *bdp; int rx_cbd_size, tx_cbd_size; rx_cbd_size = fep->rx_ring_size; tx_cbd_size = fep->tx_ring_size; if (fep->flags & FEC_FLAG_BUFDESC_EX) { rx_cbd_size *= sizeof(struct bufdesc_ex); tx_cbd_size *= sizeof(struct bufdesc_ex); } else { rx_cbd_size *= sizeof(struct bufdesc); tx_cbd_size *= sizeof(struct bufdesc); } /* Allocate memory for buffer descriptors. */ rx_cbd_cpu = dma_alloc_coherent(NULL, rx_cbd_size, &rx_cbd_dma, GFP_KERNEL); tx_cbd_cpu = dma_alloc_coherent(NULL, tx_cbd_size, &tx_cbd_dma, GFP_KERNEL); if (!rx_cbd_cpu || !tx_cbd_cpu) { if (rx_cbd_cpu) dma_free_coherent(NULL, rx_cbd_size, rx_cbd_cpu, rx_cbd_dma); if (tx_cbd_cpu) dma_free_coherent(NULL, tx_cbd_size, tx_cbd_cpu, tx_cbd_dma); return -ENOMEM; } memset(rx_cbd_cpu, 0, PAGE_SIZE); memset(tx_cbd_cpu, 0, PAGE_SIZE); /* Set receive and transmit descriptor base. */ fep->rx_bd_base = rx_cbd_cpu; fep->rx_bd_dma = rx_cbd_dma; fep->tx_bd_base = tx_cbd_cpu; fep->tx_bd_dma = tx_cbd_dma; for (i = 0; i < fep->rx_ring_size; i++) { dma_addr_t addr; skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); if (!skb) goto err_alloc; addr = dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); if (dma_mapping_error(&fep->pdev->dev, addr)) { dev_kfree_skb(skb); if (net_ratelimit()) netdev_err(ndev, "Rx DMA memory map failed\n"); goto err_alloc; } fep->rx_skbuff[i] = skb; bdp = fec_enet_rx_get(i, fep); bdp->bd.cbd_bufaddr = addr; bdp->bd.cbd_sc = BD_ENET_RX_EMPTY; /* Set the last buffer to wrap. */ if (i == fep->rx_ring_size - 1) bdp->bd.cbd_sc |= BD_SC_WRAP; if (fep->flags & FEC_FLAG_BUFDESC_EX) bdp->ebd.cbd_esc = BD_ENET_RX_INT; } for (i = 0; i < fep->tx_ring_size; i++) { bdp = fec_enet_tx_get(i, fep); fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); if (!fep->tx_bounce[i]) goto err_alloc; /* Set the last buffer to wrap. */ if (i == fep->tx_ring_size - 1) bdp->bd.cbd_sc = BD_SC_WRAP; else bdp->bd.cbd_sc = 0; bdp->bd.cbd_bufaddr = 0; if (fep->flags & FEC_FLAG_BUFDESC_EX) bdp->ebd.cbd_esc = BD_ENET_TX_INT; } return 0; err_alloc: fec_enet_free_buffers(ndev); return -ENOMEM; } static int fec_enet_open(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); int ret; pinctrl_pm_select_default_state(&fep->pdev->dev); ret = fec_enet_clk_enable(ndev, true); if (ret) return ret; /* I should reset the ring buffers here, but I don't yet know * a simple way to do that. */ ret = fec_enet_alloc_buffers(ndev); if (ret) return ret; /* Probe and connect to PHY when open the interface */ ret = fec_enet_mii_probe(ndev); if (ret) { fec_enet_free_buffers(ndev); return ret; } mutex_lock(&fep->mutex); fec_restart(ndev); mutex_unlock(&fep->mutex); napi_enable(&fep->napi); phy_start(fep->phy_dev); netif_start_queue(ndev); return 0; } static int fec_enet_close(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); phy_stop(fep->phy_dev); if (netif_device_present(ndev)) { napi_disable(&fep->napi); netif_tx_disable(ndev); mutex_lock(&fep->mutex); fec_stop(ndev); mutex_unlock(&fep->mutex); } phy_disconnect(fep->phy_dev); fep->phy_dev = NULL; fec_enet_clk_enable(ndev, false); pinctrl_pm_select_sleep_state(&fep->pdev->dev); fec_enet_free_buffers(ndev); return 0; } /* Set or clear the multicast filter for this adaptor. * Skeleton taken from sunlance driver. * The CPM Ethernet implementation allows Multicast as well as individual * MAC address filtering. Some of the drivers check to make sure it is * a group multicast address, and discard those that are not. I guess I * will do the same for now, but just remove the test if you want * individual filtering as well (do the upper net layers want or support * this kind of feature?). */ #define HASH_BITS 6 /* #bits in hash */ #define CRC32_POLY 0xEDB88320 static void set_multicast_list(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); struct netdev_hw_addr *ha; unsigned int i, bit, data, crc, tmp; unsigned char hash; if (ndev->flags & IFF_PROMISC) { tmp = readl(fep->hwp + FEC_R_CNTRL); tmp |= 0x8; writel(tmp, fep->hwp + FEC_R_CNTRL); return; } tmp = readl(fep->hwp + FEC_R_CNTRL); tmp &= ~0x8; writel(tmp, fep->hwp + FEC_R_CNTRL); if (ndev->flags & IFF_ALLMULTI) { /* Catch all multicast addresses, so set the * filter to all 1's */ writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); return; } /* Clear filter and add the addresses in hash register */ writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); netdev_for_each_mc_addr(ha, ndev) { /* calculate crc32 value of mac address */ crc = 0xffffffff; for (i = 0; i < ndev->addr_len; i++) { data = ha->addr[i]; for (bit = 0; bit < 8; bit++, data >>= 1) { crc = (crc >> 1) ^ (((crc ^ data) & 1) ? CRC32_POLY : 0); } } /* only upper 6 bits (HASH_BITS) are used * which point to specific bit in he hash registers */ hash = (crc >> (32 - HASH_BITS)) & 0x3f; if (hash > 31) { tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); tmp |= 1 << (hash - 32); writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); } else { tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); tmp |= 1 << hash; writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); } } } /* Set a MAC change in hardware. */ static int fec_set_mac_address(struct net_device *ndev, void *p) { struct fec_enet_private *fep = netdev_priv(ndev); struct sockaddr *addr = p; if (addr) { if (!is_valid_ether_addr(addr->sa_data)) return -EADDRNOTAVAIL; memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); } writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), fep->hwp + FEC_ADDR_LOW); writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), fep->hwp + FEC_ADDR_HIGH); return 0; } #ifdef CONFIG_NET_POLL_CONTROLLER /** * fec_poll_controller - FEC Poll controller function * @dev: The FEC network adapter * * Polled functionality used by netconsole and others in non interrupt mode * */ static void fec_poll_controller(struct net_device *dev) { int i; struct fec_enet_private *fep = netdev_priv(dev); for (i = 0; i < FEC_IRQ_NUM; i++) { if (fep->irq[i] > 0) { disable_irq(fep->irq[i]); fec_enet_interrupt(fep->irq[i], dev); enable_irq(fep->irq[i]); } } } #endif static netdev_features_t fec_fix_features(struct net_device *ndev, netdev_features_t features) { struct fec_enet_private *fep = netdev_priv(ndev); /* * NETIF_F_SG requires a minimum transmit ring size. If we * have less than this size, we can't support this feature. */ if (fep->tx_ring_size < TX_RING_SIZE_MIN_SG) features &= ~NETIF_F_SG; return features; } #define FEATURES_NEED_QUIESCE (NETIF_F_RXCSUM | NETIF_F_SG) static int fec_set_features(struct net_device *netdev, netdev_features_t features) { struct fec_enet_private *fep = netdev_priv(netdev); netdev_features_t changed = features ^ netdev->features; /* Quiesce the device if necessary */ if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) { mutex_lock(&fep->mutex); napi_disable(&fep->napi); netif_tx_lock_bh(netdev); fec_stop(netdev); } netdev->features = features; /* Receive checksum has been changed */ if (changed & NETIF_F_RXCSUM) { if (features & NETIF_F_RXCSUM) fep->flags |= FEC_FLAG_RX_CSUM; else fep->flags &= ~FEC_FLAG_RX_CSUM; } if (changed & NETIF_F_HW_VLAN_CTAG_RX) { if (features & NETIF_F_HW_VLAN_CTAG_RX) fep->flags |= FEC_FLAG_RX_VLAN; else fep->flags &= ~FEC_FLAG_RX_VLAN; } /* Set the appropriate minimum transmit ring free threshold */ if (features & NETIF_F_SG) fep->tx_min = MAX_SKB_FRAGS + 1; else fep->tx_min = 1; /* Resume the device after updates */ if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) { fec_restart(netdev); netif_wake_queue(netdev); netif_tx_unlock_bh(netdev); napi_enable(&fep->napi); mutex_unlock(&fep->mutex); } return 0; } static const struct net_device_ops fec_netdev_ops = { .ndo_open = fec_enet_open, .ndo_stop = fec_enet_close, .ndo_start_xmit = fec_enet_start_xmit, .ndo_set_rx_mode = set_multicast_list, .ndo_change_mtu = eth_change_mtu, .ndo_validate_addr = eth_validate_addr, .ndo_tx_timeout = fec_timeout, .ndo_set_mac_address = fec_set_mac_address, .ndo_do_ioctl = fec_enet_ioctl, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = fec_poll_controller, #endif .ndo_fix_features = fec_fix_features, .ndo_set_features = fec_set_features, }; static void fec_enet_init(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); /* init the tx & rx ring size */ fep->tx_ring_size = TX_RING_SIZE; fep->rx_ring_size = RX_RING_SIZE; fep->netdev = ndev; /* Get the Ethernet address */ fec_get_mac(ndev); /* make sure MAC we just acquired is programmed into the hw */ fec_set_mac_address(ndev, NULL); fep->rx_bd_base = fep->tx_bd_base = NULL; fep->rx_bd_dma = fep->tx_bd_dma = 0; /* The FEC Ethernet specific entries in the device structure */ ndev->watchdog_timeo = TX_TIMEOUT; ndev->netdev_ops = &fec_netdev_ops; ndev->ethtool_ops = &fec_enet_ethtool_ops; writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); if (fep->flags & FEC_FLAG_BUFDESC_EX) { /* Features which require the enhanced buffer descriptors */ if (fep->quirks & FEC_QUIRK_HAS_VLAN) { /* enable hw VLAN support */ ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; fep->flags |= FEC_FLAG_RX_VLAN; } if (fep->quirks & FEC_QUIRK_HAS_CSUM) { /* enable hw accelerator */ ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM); fep->flags |= FEC_FLAG_RX_CSUM; } } ndev->features |= NETIF_F_SG; if (ndev->features & NETIF_F_SG) fep->tx_min = MAX_SKB_FRAGS + 1; else fep->tx_min = 1; ndev->hw_features = ndev->features; fec_restart(ndev); } #ifdef CONFIG_OF static void fec_reset_phy(struct platform_device *pdev) { int err, phy_reset; int msec = 1; struct device_node *np = pdev->dev.of_node; if (!np) return; of_property_read_u32(np, "phy-reset-duration", &msec); /* A sane reset duration should not be longer than 1s */ if (msec > 1000) msec = 1; phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); if (!gpio_is_valid(phy_reset)) return; err = devm_gpio_request_one(&pdev->dev, phy_reset, GPIOF_OUT_INIT_LOW, "phy-reset"); if (err) { dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); return; } msleep(msec); gpio_set_value(phy_reset, 1); } #else /* CONFIG_OF */ static void fec_reset_phy(struct platform_device *pdev) { /* * In case of platform probe, the reset has been done * by machine code. */ } #endif /* CONFIG_OF */ static int fec_probe(struct platform_device *pdev) { struct fec_enet_private *fep; struct fec_platform_data *pdata; struct net_device *ndev; int i, irq, ret = 0; struct resource *r; const struct of_device_id *of_id; static int dev_id; struct device_node *np = pdev->dev.of_node, *phy_node; of_id = of_match_device(fec_dt_ids, &pdev->dev); if (of_id) pdev->id_entry = of_id->data; /* Init network device */ ndev = alloc_etherdev(sizeof(struct fec_enet_private)); if (!ndev) return -ENOMEM; SET_NETDEV_DEV(ndev, &pdev->dev); /* setup board info structure */ fep = netdev_priv(ndev); mutex_init(&fep->mutex); if (pdev->id_entry) fep->quirks = pdev->id_entry->driver_data; #if !defined(CONFIG_M5272) /* default enable pause frame auto negotiation */ if (fep->quirks & FEC_QUIRK_HAS_GBIT) fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG | FEC_PAUSE_FLAG_TX | FEC_PAUSE_FLAG_RX; #endif /* Select default pin state */ pinctrl_pm_select_default_state(&pdev->dev); r = platform_get_resource(pdev, IORESOURCE_MEM, 0); fep->hwp = devm_ioremap_resource(&pdev->dev, r); if (IS_ERR(fep->hwp)) { ret = PTR_ERR(fep->hwp); goto failed_ioremap; } fep->pdev = pdev; fep->dev_id = dev_id++; fep->flags = 0; if (pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX) fep->flags |= FEC_FLAG_BUFDESC_EX; platform_set_drvdata(pdev, ndev); phy_node = of_parse_phandle(np, "phy-handle", 0); if (!phy_node && of_phy_is_fixed_link(np)) { ret = of_phy_register_fixed_link(np); if (ret < 0) { dev_err(&pdev->dev, "broken fixed-link specification\n"); goto failed_phy; } phy_node = of_node_get(np); } fep->phy_node = phy_node; ret = of_get_phy_mode(pdev->dev.of_node); if (ret < 0) { pdata = dev_get_platdata(&pdev->dev); if (pdata) fep->phy_interface = pdata->phy; else fep->phy_interface = PHY_INTERFACE_MODE_MII; } else { fep->phy_interface = ret; } fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); if (IS_ERR(fep->clk_ipg)) { ret = PTR_ERR(fep->clk_ipg); goto failed_clk; } fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); if (IS_ERR(fep->clk_ahb)) { ret = PTR_ERR(fep->clk_ahb); goto failed_clk; } /* enet_out is optional, depends on board */ fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); if (IS_ERR(fep->clk_enet_out)) fep->clk_enet_out = NULL; fep->ptp_clk_on = false; mutex_init(&fep->ptp_clk_mutex); fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); if (IS_ERR(fep->clk_ptp)) { fep->clk_ptp = NULL; fep->flags &= ~FEC_FLAG_BUFDESC_EX; } ret = fec_enet_clk_enable(ndev, true); if (ret) goto failed_clk; fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); if (!IS_ERR(fep->reg_phy)) { ret = regulator_enable(fep->reg_phy); if (ret) { dev_err(&pdev->dev, "Failed to enable phy regulator: %d\n", ret); goto failed_regulator; } } else { fep->reg_phy = NULL; } fec_reset_phy(pdev); if (fep->flags & FEC_FLAG_BUFDESC_EX) fec_ptp_init(pdev); fec_enet_init(ndev); for (i = 0; i < FEC_IRQ_NUM; i++) { irq = platform_get_irq(pdev, i); if (irq < 0) { if (i) break; ret = irq; goto failed_irq; } ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 0, pdev->name, ndev); if (ret) goto failed_irq; } ret = fec_enet_mii_init(pdev); if (ret) goto failed_mii_init; /* Carrier starts down, phylib will bring it up */ netif_carrier_off(ndev); fec_enet_clk_enable(ndev, false); pinctrl_pm_select_sleep_state(&pdev->dev); ret = register_netdev(ndev); if (ret) goto failed_register; if (fep->flags & FEC_FLAG_BUFDESC_EX && fep->ptp_clock) netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); return 0; failed_register: fec_enet_mii_remove(fep); failed_mii_init: failed_irq: if (fep->reg_phy) regulator_disable(fep->reg_phy); failed_regulator: fec_enet_clk_enable(ndev, false); failed_clk: failed_phy: of_node_put(phy_node); failed_ioremap: free_netdev(ndev); return ret; } static int fec_drv_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct fec_enet_private *fep = netdev_priv(ndev); cancel_delayed_work_sync(&fep->time_keep); cancel_work_sync(&fep->tx_timeout_work); unregister_netdev(ndev); fec_enet_mii_remove(fep); if (fep->reg_phy) regulator_disable(fep->reg_phy); if (fep->ptp_clock) ptp_clock_unregister(fep->ptp_clock); fec_enet_clk_enable(ndev, false); of_node_put(fep->phy_node); free_netdev(ndev); return 0; } static int __maybe_unused fec_suspend(struct device *dev) { struct net_device *ndev = dev_get_drvdata(dev); struct fec_enet_private *fep = netdev_priv(ndev); rtnl_lock(); if (netif_running(ndev)) { phy_stop(fep->phy_dev); napi_disable(&fep->napi); netif_tx_lock_bh(ndev); netif_device_detach(ndev); netif_tx_unlock_bh(ndev); mutex_lock(&fep->mutex); fec_stop(ndev); mutex_unlock(&fep->mutex); } rtnl_unlock(); fec_enet_clk_enable(ndev, false); pinctrl_pm_select_sleep_state(&fep->pdev->dev); if (fep->reg_phy) regulator_disable(fep->reg_phy); return 0; } static int __maybe_unused fec_resume(struct device *dev) { struct net_device *ndev = dev_get_drvdata(dev); struct fec_enet_private *fep = netdev_priv(ndev); int ret; if (fep->reg_phy) { ret = regulator_enable(fep->reg_phy); if (ret) return ret; } pinctrl_pm_select_default_state(&fep->pdev->dev); ret = fec_enet_clk_enable(ndev, true); if (ret) goto failed_clk; rtnl_lock(); if (netif_running(ndev)) { mutex_lock(&fep->mutex); fec_restart(ndev); mutex_unlock(&fep->mutex); netif_tx_lock_bh(ndev); netif_device_attach(ndev); netif_tx_unlock_bh(ndev); napi_enable(&fep->napi); phy_start(fep->phy_dev); } rtnl_unlock(); return 0; failed_clk: if (fep->reg_phy) regulator_disable(fep->reg_phy); return ret; } static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); static struct platform_driver fec_driver = { .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, .pm = &fec_pm_ops, .of_match_table = fec_dt_ids, }, .id_table = fec_devtype, .probe = fec_probe, .remove = fec_drv_remove, }; module_platform_driver(fec_driver); MODULE_ALIAS("platform:"DRIVER_NAME); MODULE_LICENSE("GPL");