summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
blob: df2bec18870651386ea857681ce4ae4073e5e3ee (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip LAN966X Generic Clock Controller

maintainers:
  - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>

description: |
  The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
  ddr_clk and sys_clk. This clock controller generates and supplies
  clock to various peripherals within the SoC.

properties:
  compatible:
    const: microchip,lan966x-gck

  reg:
    minItems: 1
    items:
      - description: Generic clock registers
      - description: Optional gate clock registers

  clocks:
    items:
      - description: CPU clock source
      - description: DDR clock source
      - description: System clock source

  clock-names:
    items:
      - const: cpu
      - const: ddr
      - const: sys

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clks: clock-controller@e00c00a8 {
        compatible = "microchip,lan966x-gck";
        #clock-cells = <1>;
        clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
        clock-names = "cpu", "ddr", "sys";
        reg = <0xe00c00a8 0x38>;
    };
...