summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
blob: 27ffbccc2a082eb04ec4b4c8463e0e38e19c4ffb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek DSI Controller

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>
  - Jitao Shi <jitao.shi@mediatek.com>

description: |
  The MediaTek DSI function block is a sink of the display subsystem and can
  drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
  channel output.

allOf:
  - $ref: /schemas/display/dsi-controller.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt2701-dsi
          - mediatek,mt7623-dsi
          - mediatek,mt8167-dsi
          - mediatek,mt8173-dsi
          - mediatek,mt8183-dsi
          - mediatek,mt8186-dsi
          - mediatek,mt8188-dsi
      - items:
          - enum:
              - mediatek,mt6795-dsi
          - const: mediatek,mt8173-dsi
      - items:
          - enum:
              - mediatek,mt8195-dsi
              - mediatek,mt8365-dsi
          - const: mediatek,mt8183-dsi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  clocks:
    items:
      - description: Engine Clock
      - description: Digital Clock
      - description: HS Clock

  clock-names:
    items:
      - const: engine
      - const: digital
      - const: hs

  resets:
    maxItems: 1

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: dphy

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      Output port node. This port should be connected to the input
      port of an attached DSI panel or DSI-to-eDP encoder chip.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description:
      Input ports can have multiple endpoints, each of those connects
      to either the primary, secondary, etc, display pipeline.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: DSI input port, usually from DITHER, DSC or MERGE

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          DSI output to an attached DSI panel, or a DSI-to-X encoder chip

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks
  - clock-names
  - phys
  - phy-names

oneOf:
  - required:
      - port
  - required:
      - ports

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/mt8183-power.h>
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/reset/mt8183-resets.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        dsi0: dsi@14014000 {
            compatible = "mediatek,mt8183-dsi";
            reg = <0 0x14014000 0 0x1000>;
            interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
            clocks = <&mmsys CLK_MM_DSI0_MM>,
                <&mmsys CLK_MM_DSI0_IF>,
                <&mipi_tx0>;
            clock-names = "engine", "digital", "hs";
            resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
            phys = <&mipi_tx0>;
            phy-names = "dphy";
            port {
                dsi0_out: endpoint {
                    remote-endpoint = <&panel_in>;
                };
            };
        };
    };

...