summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
blob: 2181855a0920ea2d5decc842e45f2a4a1615ff6e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Video Input controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^vi@[0-9a-f]+$"

  compatible:
    oneOf:
      - const: nvidia,tegra20-vi
      - const: nvidia,tegra30-vi
      - const: nvidia,tegra114-vi
      - const: nvidia,tegra124-vi
      - items:
          - const: nvidia,tegra132-vi
          - const: nvidia,tegra124-vi
      - const: nvidia,tegra210-vi
      - const: nvidia,tegra186-vi
      - const: nvidia,tegra194-vi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: vi

  iommus:
    maxItems: 1

  interconnects:
    minItems: 4
    maxItems: 5

  interconnect-names:
    minItems: 4
    maxItems: 5

  operating-points-v2: true

  power-domains:
    items:
      - description: phandle to the VENC power domain

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges:
    maxItems: 1

  avdd-dsi-csi-supply:
    description: DSI/CSI power supply. Must supply 1.2 V.

  vip:
    $ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Input from the VIP (parallel input capture) module

patternProperties:
  "^csi@[0-9a-f]+$":
    type: object

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra20-vi
              - nvidia,tegra30-vi
              - nvidia,tegra114-vi
              - nvidia,tegra124-vi
    then:
      required:
        - resets
        - reset-names
    else:
      required:
        - power-domains

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;
        camera@48 {
            compatible = "aptina,mt9v111";
            reg = <0x48>;
            clocks = <&camera_clk>;

            port {
                mt9v111_out: endpoint {
                    remote-endpoint = <&vi_vip_in>;
                };
            };
        };
    };

    vi@54080000 {
        compatible = "nvidia,tegra20-vi";
        reg = <0x54080000 0x00040000>;
        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA20_CLK_VI>;
        resets = <&tegra_car 100>;
        reset-names = "vi";

        vip {
            compatible = "nvidia,tegra20-vip";
            ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                    reg = <0>;
                    vi_vip_in: endpoint {
                        remote-endpoint = <&mt9v111_out>;
                    };
                };
                port@1 {
                    reg = <1>;
                    vi_vip_out: endpoint {
                        remote-endpoint = <&vi_in>;
                    };
                };
            };
        };

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;
                vi_in: endpoint {
                    remote-endpoint = <&vi_vip_out>;
                };
            };
        };
    };

  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    vi@54080000 {
        compatible = "nvidia,tegra210-vi";
        reg = <0x54080000 0x00000700>;
        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
        assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;

        clocks = <&tegra_car TEGRA210_CLK_VI>;
        power-domains = <&pd_venc>;

        #address-cells = <1>;
        #size-cells = <1>;

        ranges = <0x0 0x54080000 0x2000>;

        csi@838 {
            compatible = "nvidia,tegra210-csi";
            reg = <0x838 0x1300>;
            assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
                              <&tegra_car TEGRA210_CLK_CILCD>,
                              <&tegra_car TEGRA210_CLK_CILE>,
                              <&tegra_car TEGRA210_CLK_CSI_TPG>;
            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
                                     <&tegra_car TEGRA210_CLK_PLL_P>,
                                     <&tegra_car TEGRA210_CLK_PLL_P>;
            assigned-clock-rates = <102000000>,
                                   <102000000>,
                                   <102000000>,
                                   <972000000>;

            clocks = <&tegra_car TEGRA210_CLK_CSI>,
                     <&tegra_car TEGRA210_CLK_CILAB>,
                     <&tegra_car TEGRA210_CLK_CILCD>,
                     <&tegra_car TEGRA210_CLK_CILE>,
                     <&tegra_car TEGRA210_CLK_CSI_TPG>;
            clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
            power-domains = <&pd_sor>;
        };
    };