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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Baikal-T1 PCIe Root Port Controller
maintainers:
- Serge Semin <fancer.lancer@gmail.com>
description:
Embedded into Baikal-T1 SoC Root Complex controller with a single port
activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
to have just a single Root Port function and is capable of establishing the
link up to Gen.3 speed on x4 lanes. It doesn't have embedded clock and reset
control module, so the proper interface initialization is supposed to be
performed by software. There four in- and four outbound iATU regions
which can be used to emit all required TLP types on the PCIe bus.
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
const: baikal,bt1-pcie
reg:
description:
DBI, DBI2 and at least 4KB outbound iATU-capable region for the
peripheral devices CFG-space access.
maxItems: 3
reg-names:
items:
- const: dbi
- const: dbi2
- const: config
interrupts:
description:
MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization
request and eight Read/Write eDMA IRQ lines are available.
maxItems: 14
interrupt-names:
items:
- const: dma0
- const: dma1
- const: dma2
- const: dma3
- const: dma4
- const: dma5
- const: dma6
- const: dma7
- const: msi
- const: aer
- const: pme
- const: hp
- const: bw_mg
- const: l_eq
clocks:
description:
DBI (attached to the APB bus), AXI-bus master and slave interfaces
are fed up by the dedicated application clocks. A common reference
clock signal is supposed to be attached to the corresponding Ref-pad
of the SoC. It will be redistributed amongst the controller core
sub-modules (pipe, core, aux, etc).
maxItems: 4
clock-names:
items:
- const: dbi
- const: mstr
- const: slv
- const: ref
resets:
description:
A comprehensive controller reset logic is supposed to be implemented
by software, so almost all the possible application and core reset
signals are exposed via the system CCU module.
maxItems: 9
reset-names:
items:
- const: mstr
- const: slv
- const: pwr
- const: hot
- const: phy
- const: core
- const: pipe
- const: sticky
- const: non-sticky
baikal,bt1-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the Baikal-T1 System Controller DT node. It's required to
access some additional PM, Reset-related and LTSSM signals.
num-lanes:
maximum: 4
max-link-speed:
maximum: 3
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/gpio/gpio.h>
pcie@1f052000 {
compatible = "baikal,bt1-pcie";
device_type = "pci";
reg = <0x1f052000 0x1000>, <0x1f053000 0x1000>, <0x1bdbf000 0x1000>;
reg-names = "dbi", "dbi2", "config";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x00000000 0x1bdb0000 0 0x00008000>,
<0x82000000 0 0x20000000 0x08000000 0 0x13db0000>;
bus-range = <0x0 0xff>;
interrupts = <GIC_SHARED 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma0", "dma1", "dma2", "dma3",
"dma4", "dma5", "dma6", "dma7",
"msi", "aer", "pme", "hp", "bw_mg",
"l_eq";
clocks = <&ccu_sys 1>, <&ccu_axi 6>, <&ccu_axi 7>, <&clk_pcie>;
clock-names = "dbi", "mstr", "slv", "ref";
resets = <&ccu_axi 6>, <&ccu_axi 7>, <&ccu_sys 7>, <&ccu_sys 10>,
<&ccu_sys 4>, <&ccu_sys 6>, <&ccu_sys 5>, <&ccu_sys 8>,
<&ccu_sys 9>;
reset-names = "mstr", "slv", "pwr", "hot", "phy", "core", "pipe",
"sticky", "non-sticky";
reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>;
num-lanes = <4>;
max-link-speed = <3>;
};
...
|
