summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
blob: d476de82e5c3f487b0275d1f2d8d8b5a79a6a116 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

description:
  The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
  GPIO controller.
  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
  Each port features up to 8 pins, each of them configurable for GPIO function
  (port mode) or in alternate function mode.
  Up to 8 different alternate function modes exist for each single pin.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
              - renesas,r9a08g045-pinctrl # RZ/G3S

      - items:
          - enum:
              - renesas,r9a07g054-pinctrl     # RZ/V2L
          - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2
    description:
      The first cell contains the global GPIO port index, constructed using the
      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
      second cell represents consumer flag as mentioned in ../gpio/gpio.txt
      E.g. "RZG2L_GPIO(39, 1)" for P39_1.

  gpio-ranges:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2
    description:
      The first cell contains the global GPIO port index, constructed using the
      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
      second cell is used to specify the flag.
      E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is
      being used as an interrupt.

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    items:
      - description: GPIO_RSTN signal
      - description: GPIO_PORT_RESETN signal
      - description: GPIO_SPARE_RESETN signal

additionalProperties:
  anyOf:
    - type: object
      additionalProperties: false
      allOf:
        - $ref: pincfg-node.yaml#
        - $ref: pinmux-node.yaml#

        - if:
            properties:
              compatible:
                contains:
                  enum:
                    - renesas,r9a08g045-pinctrl
          then:
            properties:
              drive-strength: false
              output-impedance-ohms: false
              slew-rate: false
          else:
            properties:
              drive-strength-microamp: false

      description:
        Pin controller client devices use pin configuration subnodes (children
        and grandchildren) for desired pin configuration.
        Client device subnodes use below standard properties.

      properties:
        pinmux:
          description:
            Values are constructed from GPIO port number, pin number, and
            alternate function configuration number using the RZG2L_PORT_PINMUX()
            helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
        pins: true
        drive-strength:
          enum: [ 2, 4, 8, 12 ]
        drive-strength-microamp:
          enum: [ 1900, 2200, 4000, 4400, 4500, 4700, 5200, 5300, 5700,
                  5800, 6000, 6050, 6100, 6550, 6800, 7000, 8000, 9000,
                  10000 ]
        output-impedance-ohms:
          enum: [ 33, 50, 66, 100 ]
        power-source:
          description: I/O voltage in millivolt.
          enum: [ 1800, 2500, 3300 ]
        slew-rate: true
        gpio-hog: true
        gpios: true
        input-enable: true
        output-high: true
        output-low: true
        line-name: true

    - type: object
      additionalProperties:
        $ref: "#/additionalProperties/anyOf/0"

allOf:
  - $ref: pinctrl.yaml#

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - interrupt-controller
  - '#interrupt-cells'
  - clocks
  - power-domains
  - resets

examples:
  - |
    #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
    #include <dt-bindings/clock/r9a07g044-cpg.h>

    pinctrl: pinctrl@11030000 {
            compatible = "renesas,r9a07g044-pinctrl";
            reg = <0x11030000 0x10000>;

            gpio-controller;
            #gpio-cells = <2>;
            gpio-ranges = <&pinctrl 0 0 392>;
            interrupt-controller;
            #interrupt-cells = <2>;
            clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
            resets = <&cpg R9A07G044_GPIO_RSTN>,
                     <&cpg R9A07G044_GPIO_PORT_RESETN>,
                     <&cpg R9A07G044_GPIO_SPARE_RESETN>;
            power-domains = <&cpg>;

            scif0_pins: serial0 {
                    pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
                             <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
            };

            i2c1_pins: i2c1 {
                    pins = "RIIC1_SDA", "RIIC1_SCL";
                    input-enable;
            };

            sd1-pwr-en-hog {
                    gpio-hog;
                    gpios = <RZG2L_GPIO(39, 2) 0>;
                    output-high;
                    line-name = "sd1_pwr_en";
            };

            sdhi1_pins: sd1 {
                    sd1_mux {
                            pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
                                     <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
                            power-source = <3300>;
                    };

                    sd1_data {
                            pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
                            power-source = <3300>;
                    };

                    sd1_ctrl {
                            pins = "SD1_CLK", "SD1_CMD";
                            power-source = <3300>;
                    };
            };
    };