summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/usb/exynos-usb.txt
blob: 66c394f9e11f2317653fe24c9c20b0137119eb71 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Samsung Exynos SoC USB controller

The USB devices interface with USB controllers on Exynos SOCs.
The device node has following properties.

EHCI
Required properties:
 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
   EHCI controller in host mode.
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: interrupt number to the cpu.
 - clocks: from common clock binding: handle to usb clock.
 - clock-names: from common clock binding: Shall be "usbhost".
 - phys: from the *Generic PHY* bindings; array specifying phy(s) used
   by the root port.
 - phy-names: from the *Generic PHY* bindings; array of the names for
   each phy for the root ports, must be a subset of the following:
   "host", "hsic0", "hsic1".

Optional properties:
 - samsung,vbus-gpio:  if present, specifies the GPIO that
   needs to be pulled up for the bus to be powered.

Example:

	usb@12110000 {
		compatible = "samsung,exynos4210-ehci";
		reg = <0x12110000 0x100>;
		interrupts = <0 71 0>;
		samsung,vbus-gpio = <&gpx2 6 1 3 3>;

		clocks = <&clock 285>;
		clock-names = "usbhost";

		phys = <&usb2phy 1>;
		phy-names = "host";
	};

OHCI
Required properties:
 - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
   OHCI companion controller in host mode.
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: interrupt number to the cpu.
 - clocks: from common clock binding: handle to usb clock.
 - clock-names: from common clock binding: Shall be "usbhost".
 - phys: from the *Generic PHY* bindings; array specifying phy(s) used
   by the root port.
 - phy-names: from the *Generic PHY* bindings; array of the names for
   each phy for the root ports, must be a subset of the following:
   "host", "hsic0", "hsic1".

Example:
	usb@12120000 {
		compatible = "samsung,exynos4210-ohci";
		reg = <0x12120000 0x100>;
		interrupts = <0 71 0>;

		clocks = <&clock 285>;
		clock-names = "usbhost";

		phys = <&usb2phy 1>;
		phy-names = "host";
	};

DWC3
Required properties:
 - compatible: should be one of the following -
	       "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
					    Exynos5250/5420.
	       "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on
					    Exynos5433.
	       "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
				 with 'reg' property.
 - ranges: allows valid 1:1 translation between child's address space and
	   parent's address space
 - clocks: Clock IDs array as required by the controller.
 - clock-names: names of clocks correseponding to IDs in the clock property
 - vdd10-supply: 1.0V powr supply
 - vdd33-supply: 3.0V/3.3V power supply

Sub-nodes:
The dwc3 core should be added as subnode to Exynos dwc3 glue.
- dwc3 :
   The binding details of dwc3 can be found in:
   Documentation/devicetree/bindings/usb/dwc3.txt

Example:
	usb@12000000 {
		compatible = "samsung,exynos5250-dwusb3";
		clocks = <&clock 286>;
		clock-names = "usbdrd30";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		vdd10-supply = <&ldo11_reg>;
		vdd33-supply = <&ldo9_reg>;

		dwc3 {
			compatible = "synopsys,dwc3";
			reg = <0x12000000 0x10000>;
			interrupts = <0 72 0>;
			usb-phy = <&usb2_phy &usb3_phy>;
		};
	};