1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)
*
* Copyright (C) 2015 Russell King
*/
/dts-v1/;
#include "armada-388-clearfog.dtsi"
#include "armada-38x-solidrun-microsom-emmc.dtsi"
/ {
model = "SolidRun Clearfog Base A1";
compatible = "solidrun,clearfog-base-a1",
"solidrun,clearfog-a1", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&rear_button_pins>;
pinctrl-names = "default";
button_0 {
/* The rear SW3 button */
label = "Rear Button";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_0>;
};
};
};
ð1 {
phy = <&phy1>;
};
&gpio0 {
phy1_reset {
gpio-hog;
gpios = <19 GPIO_ACTIVE_LOW>;
output-low;
line-name = "phy1-reset";
};
};
&mdio {
pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>;
phy1: ethernet-phy@1 {
/*
* Annoyingly, the marvell phy driver configures the LED
* register, rather than preserving reset-loaded setting.
* We undo that rubbish here.
*/
marvell,reg-init = <3 16 0 0x101e>;
reg = <1>;
};
};
&pinctrl {
/* phy1 reset */
clearfog_phy_pins: clearfog-phy-pins {
marvell,pins = "mpp19";
marvell,function = "gpio";
};
rear_button_pins: rear-button-pins {
marvell,pins = "mpp44";
marvell,function = "gpio";
};
};
/*
MPP
18: pu gpio pca9655 int
19: gpio phy reset
20: pu gpio sd0 detect
21: sd0:cmd
22: pd gpio mikro int
23:
24: ua1:rxd mikro rx
25: ua1:txd mikro tx
26: pu i2c1:sck
27: pu i2c1:sda
28: sd0:clk
29: pd gpio mikro rst
30:
31:
32:
33:
34:
35:
36:
37: sd0:d3
38: sd0:d0
39: sd0:d1
40: sd0:d2
41:
42:
43: spi1:cs2 mikro cs
44: gpio rear button sw3
45: ref:clk_out0 phy#0 clock
46: ref:clk_out1 phy#1 clock
47:
48: gpio J18 spare gpio
49: gpio U10 I2C_IRQ(GNSS)
50: gpio board id?
51:
52:
53:
54: gpio mikro pwm
55:
56: pu spi1:mosi mikro mosi
57: pd spi1:sck mikro sck
58: spi1:miso mikro miso
59:
*/
|
