summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/marvell/armada-385.dtsi
blob: be8d607c59b21dbadd1436f67012fe668ab5a914 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 385 SoC.
 *
 * Copyright (C) 2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 */

#include "armada-38x.dtsi"

/ {
	model = "Marvell Armada 385 family SoC";
	compatible = "marvell,armada385", "marvell,armada380";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-380-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	soc {
		pciec: pcie {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;

			/*
			 * This port can be either x4 or x1. When
			 * configured in x4 by the bootloader, then
			 * pcie@4,0 is not available.
			 */
			pcie1: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
						<0 0 0 2 &pcie1_intc 1>,
						<0 0 0 3 &pcie1_intc 2>,
						<0 0 0 4 &pcie1_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 8>;
				status = "disabled";
				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			/* x1 port */
			pcie2: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
						<0 0 0 2 &pcie2_intc 1>,
						<0 0 0 3 &pcie2_intc 2>,
						<0 0 0 4 &pcie2_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			/* x1 port */
			pcie3: pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
						<0 0 0 2 &pcie3_intc 1>,
						<0 0 0 3 &pcie3_intc 2>,
						<0 0 0 4 &pcie3_intc 3>;
				marvell,pcie-port = <2>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 6>;
				status = "disabled";
				pcie3_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			/*
			 * x1 port only available when pcie@1,0 is
			 * configured as a x1 port
			 */
			pcie4: pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82002000 0 0x48000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
						<0 0 0 2 &pcie4_intc 1>,
						<0 0 0 3 &pcie4_intc 2>,
						<0 0 0 4 &pcie4_intc 3>;
				marvell,pcie-port = <3>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 7>;
				status = "disabled";
				pcie4_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};
		};
	};
};

&pinctrl {
	compatible = "marvell,mv88f6820-pinctrl";
};