summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/microchip/at91sam9g25ek.dts
blob: 61b0bdb615dc60a45dedb385f537131647b0cd9e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
 *
 *  Copyright (C) 2012 Atmel,
 *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
 */
/dts-v1/;
#include "at91sam9g25.dtsi"
#include "at91sam9x5ek.dtsi"

/ {
	model = "Atmel AT91SAM9G25-EK";
	compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
};

&i2c0 {
	camera@30 {
		compatible = "ovti,ov2640";
		reg = <0x30>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
		resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
		pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
		clocks = <&pmc PMC_TYPE_SYSTEM 8>;
		clock-names = "xvclk";
		assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
		assigned-clock-rates = <25000000>;
		status = "okay";

		port {
			ov2640_0: endpoint {
				remote-endpoint = <&isi_0>;
				bus-width = <8>;
			};
		};
	};
};

&isi {
	status = "okay";

	port {
		isi_0: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&ov2640_0>;
			bus-width = <8>;
			vsync-active = <1>;
			hsync-active = <1>;
		};
	};
};

&macb0 {
	phy-mode = "rmii";
	status = "okay";
};

&mmc1 {
	status = "disabled";
};

&spi0 {
	status = "disabled";
};