summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/mt8135.dtsi
blob: a031b36363187f58efd0187393c7a71dd01e22b0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Joe.C <yingjoe.chen@mediatek.com>
 *
 */

#include <dt-bindings/clock/mt8135-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt8135-resets.h>
#include <dt-bindings/pinctrl/mt8135-pinfunc.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "mediatek,mt8135";
	interrupt-parent = <&sysirq>;

	cpu-map {
		cluster0 {
			core0 {
				cpu = <&cpu0>;
			};
			core1 {
				cpu = <&cpu1>;
			};
		};

		cluster1 {
			core0 {
				cpu = <&cpu2>;
			};
			core1 {
				cpu = <&cpu3>;
			};
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt81xx-tz-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x001>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x100>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x101>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		trustzone-bootinfo@80002000 {
			compatible = "mediatek,trustzone-bootinfo";
			reg = <0 0x80002000 0 0x1000>;
		};
	};

	clocks {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		system_clk: dummy13m {
			compatible = "fixed-clock";
			clock-frequency = <13000000>;
			#clock-cells = <0>;
		};

		rtc_clk: dummy32k {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			#clock-cells = <0>;
		};

		clk26m: clk26m {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <13000000>;
		arm,cpu-registers-not-fw-configured;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		topckgen: topckgen@10000000 {
			compatible = "mediatek,mt8135-topckgen";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: infracfg@10001000 {
			#reset-cells = <1>;
			#clock-cells = <1>;
			compatible = "mediatek,mt8135-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
		};

		pericfg: pericfg@10003000 {
			#reset-cells = <1>;
			#clock-cells = <1>;
			compatible = "mediatek,mt8135-pericfg", "syscon";
			reg = <0 0x10003000 0 0x1000>;
		};

		/*
		 * Pinctrl access register at 0x10005000 and 0x1020c000 through
		 * regmap. Register 0x1000b000 is used by EINT.
		 */
		pio: pinctrl@10005000 {
			compatible = "mediatek,mt8135-pinctrl";
			reg = <0 0x1000b000 0 0x1000>;
			mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
			pins-are-numbered;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
		};

		syscfg_pctl_a: syscfg_pctl_a@10005000 {
			compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
			reg = <0 0x10005000 0 0x1000>;
		};

		timer: timer@10008000 {
			compatible = "mediatek,mt8135-timer",
					"mediatek,mt6577-timer";
			reg = <0 0x10008000 0 0x80>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&system_clk>, <&rtc_clk>;
			clock-names = "system-clk", "rtc-clk";
		};

		pwrap: pwrap@1000f000 {
			compatible = "mediatek,mt8135-pwrap";
			reg = <0 0x1000f000 0 0x1000>,
				<0 0x11017000 0 0x1000>;
			reg-names = "pwrap", "pwrap-bridge";
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
					<&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
			reset-names = "pwrap", "pwrap-bridge";
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "spi", "wrap";
		};

		sysirq: interrupt-controller@10200030 {
			compatible = "mediatek,mt8135-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10200030 0 0x1c>;
		};

		apmixedsys: apmixedsys@10209000 {
			compatible = "mediatek,mt8135-apmixedsys";
			reg = <0 0x10209000 0 0x1000>;
			#clock-cells = <1>;
		};

		syscfg_pctl_b: syscfg_pctl_b@1020c000 {
			compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
			reg = <0 0x1020c000 0 0x1000>;
		};

		gic: interrupt-controller@10211000 {
			compatible = "arm,cortex-a15-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10211000 0 0x1000>,
			      <0 0x10212000 0 0x2000>,
			      <0 0x10214000 0 0x2000>,
			      <0 0x10216000 0 0x2000>;
		};

		uart0: serial@11006000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11006000 0 0x400>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart1: serial@11007000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11007000 0 0x400>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart2: serial@11008000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11008000 0 0x400>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart3: serial@11009000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11009000 0 0x400>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

	};
};