summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/omap34xx.dtsi
blob: feaa43b785354384b8800834bddb30c1411e2f2e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
/*
 * Device Tree Source for OMAP34xx/OMAP35xx SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/media/omap3-isp.h>

#include "omap3.dtsi"

/ {
	cpus {
		cpu: cpu@0 {
			/* OMAP343x/OMAP35xx variants OPP1-6 */
			operating-points-v2 = <&cpu0_opp_table>;

			clock-latency = <300000>; /* From legacy driver */
			#cooling-cells = <2>;
		};
	};

	/* see Documentation/devicetree/bindings/opp/opp.txt */
	cpu0_opp_table: opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <&scm_conf>;

		opp1-125000000 {
			opp-hz = /bits/ 64 <125000000>;
			/*
			 * we currently only select the max voltage from table
			 * Table 3-3 of the omap3530 Data sheet (SPRS507F).
			 * Format is: <target min max>
			 */
			opp-microvolt = <975000 975000 975000>;
			/*
			 * first value is silicon revision bit mask
			 * second one 720MHz Device Identification bit mask
			 */
			opp-supported-hw = <0xffffffff 3>;
		};

		opp2-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <1075000 1075000 1075000>;
			opp-supported-hw = <0xffffffff 3>;
			opp-suspend;
		};

		opp3-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <1200000 1200000 1200000>;
			opp-supported-hw = <0xffffffff 3>;
		};

		opp4-550000000 {
			opp-hz = /bits/ 64 <550000000>;
			opp-microvolt = <1275000 1275000 1275000>;
			opp-supported-hw = <0xffffffff 3>;
		};

		opp5-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1350000 1350000 1350000>;
			opp-supported-hw = <0xffffffff 3>;
		};

		opp6-720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt = <1350000 1350000 1350000>;
			/* only high-speed grade omap3530 devices */
			opp-supported-hw = <0xffffffff 2>;
			turbo-mode;
		};
	};

	ocp@68000000 {
		omap3_pmx_core2: pinmux@480025d8 {
			compatible = "ti,omap3-padconf", "pinctrl-single";
			reg = <0x480025d8 0x24>;
			#address-cells = <1>;
			#size-cells = <0>;
			#pinctrl-cells = <1>;
			#interrupt-cells = <1>;
			interrupt-controller;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0xff1f>;
		};

		isp: isp@480bc000 {
			compatible = "ti,omap3-isp";
			reg = <0x480bc000 0x12fc
			       0x480bd800 0x017c>;
			interrupts = <24>;
			iommus = <&mmu_isp>;
			syscon = <&scm_conf 0x6c>;
			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
			#clock-cells = <1>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		bandgap: bandgap@48002524 {
			reg = <0x48002524 0x4>;
			compatible = "ti,omap34xx-bandgap";
			#thermal-sensor-cells = <0>;
		};

		target-module@480cb000 {
			compatible = "ti,sysc-omap3430-sr", "ti,sysc";
			ti,hwmods = "smartreflex_core";
			reg = <0x480cb024 0x4>;
			reg-names = "sysc";
			ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
			clocks = <&sr2_fck>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x480cb000 0x001000>;

			smartreflex_core: smartreflex@0 {
				compatible = "ti,omap3-smartreflex-core";
				reg = <0 0x400>;
				interrupts = <19>;
			};
		};

		target-module@480c9000 {
			compatible = "ti,sysc-omap3430-sr", "ti,sysc";
			ti,hwmods = "smartreflex_mpu_iva";
			reg = <0x480c9024 0x4>;
			reg-names = "sysc";
			ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
			clocks = <&sr1_fck>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x480c9000 0x001000>;

			smartreflex_mpu_iva: smartreflex@480c9000 {
				compatible = "ti,omap3-smartreflex-mpu-iva";
				reg = <0 0x400>;
				interrupts = <18>;
			};
		};

		/*
		 * On omap34xx the OCP registers do not seem to be accessible
		 * at all unlike on 36xx. Maybe SGX is permanently set to
		 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
		 * write-only at 0x50000e10. We detect SGX based on the SGX
		 * revision register instead of the unreadable OCP revision
		 * register. Also note that on early 34xx es1 revision there
		 * are also different clocks, but we do not have any dts users
		 * for it.
		 */
		sgx_module: target-module@50000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x50000014 0x4>;
			reg-names = "rev";
			clocks = <&sgx_fck>, <&sgx_ick>;
			clock-names = "fck", "ick";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x50000000 0x4000>;

			/*
			 * Closed source PowerVR driver, no child device
			 * binding or driver in mainline
			 */
		};
	};

	thermal_zones: thermal-zones {
		#include "omap3-cpu-thermal.dtsi"
	};
};

&ssi {
	status = "okay";

	clocks = <&ssi_ssr_fck>,
		 <&ssi_sst_fck>,
		 <&ssi_ick>;
	clock-names = "ssi_ssr_fck",
		      "ssi_sst_fck",
		      "ssi_ick";
};

/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"