summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
blob: 0c742befb7612fc293f16a93a920d0eafe210ead (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 *
 * Mingkai Hu <mingkai.hu@nxp.com>
 */

/dts-v1/;

#include "fsl-ls1046a.dtsi"

/ {
	model = "LS1046A RDB Board";
	compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";

	aliases {
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&esdhc {
	mmc-hs200-1_8v;
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
};

&i2c0 {
	status = "okay";

	ina220@40 {
		compatible = "ti,ina220";
		reg = <0x40>;
		shunt-resistor = <1000>;
	};

	temp-sensor@4c {
		compatible = "adi,adt7461";
		reg = <0x4c>;
	};

	eeprom@52 {
		compatible = "atmel,24c512";
		reg = <0x52>;
	};

	eeprom@53 {
		compatible = "atmel,24c512";
		reg = <0x53>;
	};
};

&i2c3 {
	status = "okay";

	rtc@51 {
		compatible = "nxp,pcf2129";
		reg = <0x51>;
	};
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	/* NAND Flashe and CPLD on board */
	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
	status = "okay";

	nand@0,0 {
		compatible = "fsl,ifc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0 0x0 0x10000>;
	};

	cpld: board-control@2,0 {
		compatible = "fsl,ls1046ardb-cpld";
		reg = <0x2 0x0 0x0000100>;
	};
};

&qspi {
	status = "okay";

	qflash0: flash@0 {
		compatible = "spansion,m25p80";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		reg = <0>;
	};

	qflash1: flash@1 {
		compatible = "spansion,m25p80";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		reg = <1>;
	};
};

&usb1 {
	dr_mode = "otg";
};

#include "fsl-ls1046-post.dtsi"

&fman0 {
	ethernet@e4000 {
		phy-handle = <&rgmii_phy1>;
		phy-connection-type = "rgmii";
	};

	ethernet@e6000 {
		phy-handle = <&rgmii_phy2>;
		phy-connection-type = "rgmii";
	};

	ethernet@e8000 {
		phy-handle = <&sgmii_phy1>;
		phy-connection-type = "sgmii";
	};

	ethernet@ea000 {
		phy-handle = <&sgmii_phy2>;
		phy-connection-type = "sgmii";
	};

	ethernet@f0000 { /* 10GEC1 */
		phy-handle = <&aqr106_phy>;
		phy-connection-type = "xgmii";
	};

	ethernet@f2000 { /* 10GEC2 */
		fixed-link = <0 1 1000 0 0>;
		phy-connection-type = "xgmii";
	};

	mdio@fc000 {
		rgmii_phy1: ethernet-phy@1 {
			reg = <0x1>;
		};

		rgmii_phy2: ethernet-phy@2 {
			reg = <0x2>;
		};

		sgmii_phy1: ethernet-phy@3 {
			reg = <0x3>;
		};

		sgmii_phy2: ethernet-phy@4 {
			reg = <0x4>;
		};
	};

	mdio@fd000 {
		aqr106_phy: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c45";
			interrupts = <0 131 4>;
			reg = <0x0>;
		};
	};
};