summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
blob: 50f68ca5a9af710eba8044f1f164142791cab0ec (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for NXP Layerscape-1046A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2018, 2020 NXP
 *
 * Mingkai Hu <mingkai.hu@nxp.com>
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "fsl,ls1046a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		crypto = &crypto;
		fman0 = &fman0;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		ethernet4 = &enet4;
		ethernet5 = &enet5;
		ethernet6 = &enet6;
		ethernet7 = &enet7;
		rtc1 = &ftm_alarm0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x1>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x2>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x3>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		l2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	idle-states {
		/*
		 * PSCI node is not added default, U-boot will add missing
		 * parts if it determines to use PSCI.
		 */
		entry-method = "psci";

		CPU_PH20: cpu-ph20 {
			compatible = "arm,idle-state";
			idle-state-name = "PH20";
			arm,psci-suspend-param = <0x0>;
			entry-latency-us = <1000>;
			exit-latency-us = <1000>;
			min-residency-us = <3000>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* Real size will be filled by bootloader */
		reg = <0x0 0x80000000 0x0 0x0>;
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

	thermal-zones {
		ddr-controller {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 0>;

			trips {
				ddr-ctrler-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				ddr-ctrler-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		serdes {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 1>;

			trips {
				serdes-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				serdes-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		fman {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 2>;

			trips {
				fman-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				fman-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		core-cluster {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 3>;

			trips {
				core_cluster_alert: core-cluster-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				core_cluster_crit: core-cluster-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&core_cluster_alert>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		sec {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 4>;

			trips {
				sec-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				sec-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
					  IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
	};

	gic: interrupt-controller@1400000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x1410000 0 0x10000>, /* GICD */
		      <0x0 0x1420000 0 0x20000>, /* GICC */
		      <0x0 0x1440000 0 0x20000>, /* GICH */
		      <0x0 0x1460000 0 0x20000>; /* GICV */
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
					 IRQ_TYPE_LEVEL_LOW)>;
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
		dma-coherent;

		ddr: memory-controller@1080000 {
			compatible = "fsl,qoriq-memory-controller";
			reg = <0x0 0x1080000 0x0 0x1000>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};

		ifc: memory-controller@1530000 {
			compatible = "fsl,ifc";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		qspi: spi@1550000 {
			compatible = "fsl,ls1021a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>,
				<0x0 0x40000000 0x0 0x10000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "qspi_en", "qspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1046a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x1570000 0x10000>;

			extirq: interrupt-controller@1ac {
				compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq";
				#interrupt-cells = <2>;
				#address-cells = <0>;
				interrupt-controller;
				reg = <0x1ac 4>;
				interrupt-map =
					<0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
					<1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
					<2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
					<3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
					<4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
					<5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
					<6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
					<7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
					<8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
					<9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
					<10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
					<11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-map-mask = <0xf 0x0>;
			};
		};

		crypto: crypto@1700000 {
			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
				     "fsl,sec-v4.0";
			fsl,sec-era = <8>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x1700000 0x100000>;
			reg = <0x00 0x1700000 0x0 0x100000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x10000 0x10000>;
				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x20000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x30000 0x10000>;
				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x40000 0x10000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		qman: qman@1880000 {
			compatible = "fsl,qman";
			reg = <0x0 0x1880000 0x0 0x10000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			memory-region = <&qman_fqd &qman_pfdr>;

		};

		bman: bman@1890000 {
			compatible = "fsl,bman";
			reg = <0x0 0x1890000 0x0 0x10000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			memory-region = <&bman_fbpr>;

		};

		qportals: qman-portals@500000000 {
			ranges = <0x0 0x5 0x00000000 0x8000000>;
		};

		bportals: bman-portals@508000000 {
			ranges = <0x0 0x5 0x08000000 0x8000000>;
		};

		sfp: efuse@1e80000 {
			compatible = "fsl,ls1021a-sfp";
			reg = <0x0 0x1e80000 0x0 0x10000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "sfp";
		};

		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1046a-dcfg", "syscon";
			reg = <0x0 0x1ee0000 0x0 0x1000>;
			big-endian;
		};

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1046a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x1000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		tmu: tmu@1f00000 {
			compatible = "fsl,qoriq-tmu";
			reg = <0x0 0x1f00000 0x0 0x10000>;
			interrupts = <0 33 0x4>;
			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
			fsl,tmu-calibration =
				/* Calibration data group 1 */
				<0x00000000 0x00000023
				0x00000001 0x00000029
				0x00000002 0x0000002f
				0x00000003 0x00000036
				0x00000004 0x0000003c
				0x00000005 0x00000042
				0x00000006 0x00000049
				0x00000007 0x0000004f
				0x00000008 0x00000055
				0x00000009 0x0000005c
				0x0000000a 0x00000062
				0x0000000b 0x00000068
				/* Calibration data group 2 */
				0x00010000 0x00000022
				0x00010001 0x0000002a
				0x00010002 0x00000032
				0x00010003 0x0000003a
				0x00010004 0x00000042
				0x00010005 0x0000004a
				0x00010006 0x00000052
				0x00010007 0x0000005a
				0x00010008 0x00000062
				0x00010009 0x0000006a
				/* Calibration data group 3 */
				0x00020000 0x00000021
				0x00020001 0x0000002b
				0x00020002 0x00000035
				0x00020003 0x0000003e
				0x00020004 0x00000048
				0x00020005 0x00000052
				0x00020006 0x0000005c
				/* Calibration data group 4 */
				0x00030000 0x00000011
				0x00030001 0x0000001a
				0x00030002 0x00000024
				0x00030003 0x0000002e
				0x00030004 0x00000038
				0x00030005 0x00000042
				0x00030006 0x0000004c
				0x00030007 0x00000056>;
			big-endian;
			#thermal-sensor-cells = <1>;
		};

		dspi: spi@2100000 {
			compatible = "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			dmas = <&edma0 1 38>,
			       <&edma0 1 39>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			scl-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			scl-gpios = <&gpio3 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
			status = "disabled";
		};

		i2c3: i2c@21b0000 {
			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21b0000 0x0 0x10000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			scl-gpios = <&gpio3 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		duart2: serial@21d0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		duart3: serial@21d0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		gpio0: gpio@2300000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@2310000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2320000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2330000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			status = "disabled";
		};

		wdog0: watchdog@2ad0000 {
			compatible = "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			big-endian;
		};

		edma0: dma-controller@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
			      <0x0 0x2c10000 0x0 0x10000>,
			      <0x0 0x2c20000 0x0 0x10000>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
		};

		aux_bus: aux_bus {
			#address-cells = <2>;
			#size-cells = <2>;
			compatible = "simple-bus";
			ranges;
			dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;

			usb0: usb@2f00000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x2f00000 0x0 0x10000>;
				interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
				dr_mode = "host";
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,dis_rxdet_inp3_quirk;
				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
				usb3-lpm-capable;
			};

			usb1: usb@3000000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x3000000 0x0 0x10000>;
				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
				dr_mode = "host";
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,dis_rxdet_inp3_quirk;
				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
				usb3-lpm-capable;
			};

			usb2: usb@3100000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x3100000 0x0 0x10000>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				dr_mode = "host";
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,dis_rxdet_inp3_quirk;
				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
				usb3-lpm-capable;
			};

			sata: sata@3200000 {
				compatible = "fsl,ls1046a-ahci";
				reg = <0x0 0x3200000 0x0 0x10000>,
					<0x0 0x20140520 0x0 0x4>;
				reg-names = "ahci", "sata-ecc";
				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
						    QORIQ_CLK_PLL_DIV(2)>;
			};
		};

		msi1: msi-controller@1580000 {
			compatible = "fsl,ls1046a-msi";
			msi-controller;
			reg = <0x0 0x1580000 0x0 0x10000>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
		};

		msi2: msi-controller@1590000 {
			compatible = "fsl,ls1046a-msi";
			msi-controller;
			reg = <0x0 0x1590000 0x0 0x10000>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		};

		msi3: msi-controller@15a0000 {
			compatible = "fsl,ls1046a-msi";
			msi-controller;
			reg = <0x0 0x15a0000 0x0 0x10000>;
			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
		};

		pcie1: pcie@3400000 {
			compatible = "fsl,ls1046a-pcie";
			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
			      <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
			interrupt-names = "aer", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <8>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi1>, <&msi2>, <&msi3>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
			status = "disabled";
		};

		pcie_ep1: pcie_ep@3400000 {
			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
			reg = <0x00 0x03400000 0x0 0x00100000>,
			      <0x40 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pme";
			num-ib-windows = <6>;
			num-ob-windows = <8>;
			big-endian;
			status = "disabled";
		};

		pcie2: pcie@3500000 {
			compatible = "fsl,ls1046a-pcie";
			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
			      <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
			interrupt-names = "aer", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <8>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi2>, <&msi3>, <&msi1>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
			status = "disabled";
		};

		pcie_ep2: pcie_ep@3500000 {
			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
			reg = <0x00 0x03500000 0x0 0x00100000>,
			      <0x48 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pme";
			num-ib-windows = <6>;
			num-ob-windows = <8>;
			big-endian;
			status = "disabled";
		};

		pcie3: pcie@3600000 {
			compatible = "fsl,ls1046a-pcie";
			reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
			      <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
			interrupt-names = "aer", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <8>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi3>, <&msi1>, <&msi2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
			status = "disabled";
		};

		pcie_ep3: pcie_ep@3600000 {
			compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
			reg = <0x00 0x03600000 0x0 0x00100000>,
			      <0x50 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pme";
			num-ib-windows = <6>;
			num-ob-windows = <8>;
			big-endian;
			status = "disabled";
		};

		qdma: dma-controller@8380000 {
			compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "qdma-error", "qdma-queue0",
				"qdma-queue1", "qdma-queue2", "qdma-queue3";
			dma-channels = <8>;
			block-number = <1>;
			block-offset = <0x10000>;
			fsl,dma-queues = <2>;
			status-sizes = <64>;
			queue-sizes = <64 64>;
			big-endian;
		};

		rcpm: power-controller@1ee2140 {
			compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
			reg = <0x0 0x1ee2140 0x0 0x4>;
			#fsl,rcpm-wakeup-cells = <1>;
		};

		ftm_alarm0: timer@29d0000 {
			compatible = "fsl,ls1046a-ftm-alarm";
			reg = <0x0 0x29d0000 0x0 0x10000>;
			fsl,rcpm-wakeup = <&rcpm 0x20000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		bman_fbpr: bman-fbpr {
			compatible = "shared-dma-pool";
			size = <0 0x1000000>;
			alignment = <0 0x1000000>;
			no-map;
		};

		qman_fqd: qman-fqd {
			compatible = "shared-dma-pool";
			size = <0 0x800000>;
			alignment = <0 0x800000>;
			no-map;
		};

		qman_pfdr: qman-pfdr {
			compatible = "shared-dma-pool";
			size = <0 0x2000000>;
			alignment = <0 0x2000000>;
			no-map;
		};
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"