summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
blob: f61c48776cf394e0512f8ef3714f37686b4f8d34 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019-2020 Variscite Ltd.
 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
 */

/dts-v1/;

#include "imx8mn-var-som.dtsi"

/ {
	model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
	compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";

	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	gpio-keys {
		compatible = "gpio-keys";

		back {
			label = "Back";
			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_BACK>;
		};

		home {
			label = "Home";
			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_HOME>;
		};

		menu {
			label = "Menu";
			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_MENU>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led {
			label = "Heartbeat";
			gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
		};
	};
};

&ethphy {
	reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pca9534: gpio@20 {
		compatible = "nxp,pca9534";
		reg = <0x20>;
		gpio-controller;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pca9534>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
		#gpio-cells = <2>;
		wakeup-source;

		/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
		usb3-sata-sel-hog {
			gpio-hog;
			gpios = <4 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "usb3_sata_sel";
		};

		som-vselect-hog {
			gpio-hog;
			gpios = <6 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "som_vselect";
		};

		enet-sel-hog {
			gpio-hog;
			gpios = <7 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "enet_sel";
		};
	};

	extcon_usbotg1: typec@3d {
		compatible = "nxp,ptn5150";
		reg = <0x3d>;
		interrupt-parent = <&gpio1>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ptn5150>;
		status = "okay";
	};
};

&i2c3 {
	/* Capacitive touch controller */
	ft5x06_ts: touchscreen@38 {
		compatible = "edt,edt-ft5406";
		reg = <0x38>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_captouch>;
		interrupt-parent = <&gpio5>;
		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

		touchscreen-size-x = <800>;
		touchscreen-size-y = <480>;
		touchscreen-inverted-x;
		touchscreen-inverted-y;
	};

	rtc@68 {
		compatible = "dallas,ds1337";
		reg = <0x68>;
	};
};

/* Header */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* Header */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&usbotg1 {
	disable-over-current;
	extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
};

&pinctrl_fec1 {
	fsl,pins = <
		MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
		MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
		MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
		MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
		MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
		MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
		MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
		MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
		MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
		MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
		MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
		MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
		MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
		MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
	>;
};

&pinctrl_fec1_sleep {
	fsl,pins = <
		MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16		0x120
		MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120
		MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x120
		MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19		0x120
		MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20		0x120
		MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21		0x120
		MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x120
		MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x120
		MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27		0x120
		MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26		0x120
		MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23		0x120
		MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25		0x120
		MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120
		MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120
		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
	>;
};

&iomuxc {
	pinctrl_captouch: captouchgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4		0x16
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_pca9534: pca9534grp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16
		>;
	};

	pinctrl_ptn5150: ptn5150grp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x16
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x41
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
		>;
	};
};