1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
*
* DTS for common base of SolidRun CN9130 Clearfog Base and Pro.
*
*/
/ {
aliases {
/* label nics same order as armada 388 clearfog */
ethernet0 = &cp0_eth2;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth0;
i2c1 = &cp0_i2c1;
mmc1 = &cp0_sdhci0;
};
reg_usb3_vbus0: regulator-usb3-vbus0 {
compatible = "regulator-fixed";
regulator-name = "vbus0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
};
sfp: sfp {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
los-gpios = <&expander0 12 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&expander0 15 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&expander0 14 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&expander0 13 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
};
/* SRDS #2 - SFP+ 10GE */
&cp0_eth0 {
managed = "in-band-status";
phys = <&cp0_comphy2 0>;
phy-mode = "10gbase-r";
sfp = <&sfp>;
status = "okay";
};
&cp0_i2c0 {
expander0: gpio-expander@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-0 = <&expander0_pins>;
pinctrl-names = "default";
interrupt-parent = <&cp0_gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
/* CON3 */
pcie2-0-clkreq-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie2.0-clkreq";
};
/* CON3 */
pcie2-0-w-disable-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie2.0-w-disable";
};
usb3-ilimit-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
input;
line-name = "usb3-current-limit";
};
m2-devslp-hog {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "m.2 devslp";
};
};
/* The MCP3021 supports standard and fast modes */
adc@4c {
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
carrier_eeprom: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <8>;
};
};
&cp0_i2c1 {
/*
* Routed to SFP, M.2, mikrobus, and miniPCIe
* SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
* address pins tied low, which takes addresses 0x50 and 0x51.
* Mikrobus doesn't specify beyond an I2C bus being present.
* PCIe uses ARP to assign addresses, or 0x63-0x64.
*/
clock-frequency = <100000>;
pinctrl-0 = <&cp0_i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
/* SRDS #5 - miniPCIe (CON3) */
&cp0_pcie2 {
num-lanes = <1>;
phys = <&cp0_comphy5 2>;
/* dw-pcie inverts internally */
reset-gpios = <&expander0 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&cp0_pinctrl {
cp0_i2c1_pins: cp0-i2c1-pins {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_mmc0_pins: cp0-mmc0-pins {
marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58",
"mpp59", "mpp60", "mpp61";
marvell,function = "sdio";
};
mikro_spi_pins: cp0-spi1-cs1-pins {
marvell,pins = "mpp12";
marvell,function = "spi1";
};
mikro_uart_pins: cp0-uart-pins {
marvell,pins = "mpp2", "mpp3";
marvell,function = "uart1";
};
expander0_pins: cp0-expander0-pins {
marvell,pins = "mpp4";
marvell,function = "gpio";
};
};
/* SRDS #0 - SATA on M.2 connector */
&cp0_sata0 {
phys = <&cp0_comphy0 1>;
status = "okay";
/* only port 1 is available */
/delete-node/ sata-port@0;
};
/* microSD */
&cp0_sdhci0 {
pinctrl-0 = <&cp0_mmc0_pins>;
pinctrl-names = "default";
bus-width = <4>;
no-1-8-v;
status = "okay";
};
&cp0_spi1 {
/* CS1 for mikrobus */
pinctrl-0 = <&cp0_spi1_pins &mikro_spi_pins>;
};
/*
* SRDS #1 - USB-3.0 Host on Type-A connector
* USB-2.0 Host on mPCI-e connector (CON3)
*/
&cp0_usb3_0 {
phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
phy-names = "comphy", "utmi";
vbus-supply = <®_usb3_vbus0>;
dr_mode = "host";
status = "okay";
};
&cp0_utmi {
status = "okay";
};
/* mikrobus uart */
&cp0_uart0 {
pinctrl-0 = <&mikro_uart_pins>;
pinctrl-names = "default";
status = "okay";
};
|
