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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* SolidRun CN92130 Clearfog family
*/
#include "cn9130-sr-som.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sfp: sfp {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
los-gpios = <&expander0 12 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&expander0 15 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&expander0 14 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&expander0 13 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
rfkill-gnss {
compatible = "rfkill-gpio";
label = "m.2 GNSS";
radio-type = "gps";
/* rfkill-gpio inverts internally */
shutdown-gpios = <&expander0 9 GPIO_ACTIVE_HIGH>;
};
/* M.2 is B-keyed, so w-disable is for WWAN */
rfkill-wwan {
compatible = "rfkill-gpio";
label = "m.2 WWAN";
radio-type = "wwan";
/* rfkill-gpio inverts internally */
shutdown-gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
};
};
/* SRDS #2 - SFP+ 10GE */
&cp0_eth0 {
managed = "in-band-status";
phys = <&cp0_comphy2 0>;
phy-mode = "10gbase-r";
sfp = <&sfp>;
status = "okay";
};
&cp0_i2c0 {
expander0: gpio-expander@20 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
pcie1-0-clkreq-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie1.0-clkreq";
};
pcie1-0-perst-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie1.0-perst";
};
m2-ful-card-power-off {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2-ful-card-power-off";
};
/* mini-PCIe can be either WWAN or WLAN */
pcie1-0-w-disable-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie1.0-w-disable";
};
usb3-ilimit-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
input;
line-name = "usb3-current-limit";
};
usb3-power-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb3-power";
};
m2-reset-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m.2 reset";
};
m2-devslp-hog {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "m.2 devslp";
};
};
/* The MCP3021 supports standard and fast modes */
adc@4c {
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
};
&cp0_i2c1 {
/*
* Routed to SFP, M.2, mikrobus, and miniPCIe
* SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
* address pins tied low, which takes addresses 0x50 and 0x51.
* Mikrobus doesn't specify beyond an I2C bus being present.
* PCIe uses ARP to assign addresses, or 0x63-0x64.
*/
clock-frequency = <100000>;
pinctrl-0 = <&clearfog_i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
/* SRDS #5 - miniPCIe */
&cp0_pcie2 {
num-lanes = <1>;
phys = <&cp0_comphy5 2>;
status = "okay";
};
&cp0_pinctrl {
clearfog_i2c1_pins: i2c1-pins {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_mmc0_cd_pins: cp0-sdhci-cd-pins-0 {
marvell,pins = "mpp43";
marvell,function = "sdio";
};
cp0_mmc0_pins: cp0-sdhci-pins-0 {
marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59",
"mpp60", "mpp61";
marvell,function = "sdio";
};
mikro_spi_pins: mikro-spi-pins {
marvell,pins = "mpp12";
marvell,function = "spi1";
};
mikro_uart_pins: mikro-uart-pins {
marvell,pins = "mpp2", "mpp3";
marvell,function = "uart1";
};
};
/* SRDS #0 - SATA on M.2 connector */
&cp0_sata0 {
phys = <&cp0_comphy0 1>;
status = "okay";
};
&cp0_sdhci0 {
bus-width = <4>;
cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
no-1-8-v;
pinctrl-0 = <&cp0_mmc0_pins &cp0_mmc0_cd_pins>;
pinctrl-names = "default";
status = "okay";
vmmc-supply = <®_3p3v>;
vqmmc-supply = <®_3p3v>;
};
&cp0_spi1 {
/* CS1 for mikrobus */
pinctrl-0 = <&cp0_spi1_pins &mikro_spi_pins>;
};
&cp0_uart0 {
/* mikrobus uart */
pinctrl-0 = <&mikro_uart_pins>;
pinctrl-names = "default";
status = "okay";
};
/* SRDS #1 - USB 3.0 host */
&cp0_usb3_0 {
phy-names = "usb";
phys = <&cp0_comphy1 0>;
status = "okay";
};
/* SRDS #4 - M.2 USB 3.0 */
&cp0_usb3_1 {
phy-names = "usb";
phys = <&cp0_comphy4 1>;
status = "okay";
};
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