summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
blob: 57e41cacd48341e0d185b30b35a45cf775870ca7 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2020 Marvell International Ltd.
 *
 * Device tree for the CN9130-DB board (setup "B").
 */

#include "cn9130-db.dtsi"

/ {
	model = "Marvell Armada CN9130-DB setup B";
};

/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
 */

&cp0_nand_controller {
	status = "okay";
};