summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/nvidia/tegra186.dtsi
blob: f0bb6ced49765761293d185e80238a794f18cbb8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>

/ {
	compatible = "nvidia,tegra186";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	misc@100000 {
		compatible = "nvidia,tegra186-misc";
		reg = <0x0 0x00100000 0x0 0xf000>,
		      <0x0 0x0010f000 0x0 0x1000>;
	};

	gpio: gpio@2200000 {
		compatible = "nvidia,tegra186-gpio";
		reg-names = "security", "gpio";
		reg = <0x0 0x2200000 0x0 0x10000>,
		      <0x0 0x2210000 0x0 0x10000>;
		interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <2>;
		interrupt-controller;
		#gpio-cells = <2>;
		gpio-controller;
	};

	ethernet@2490000 {
		compatible = "nvidia,tegra186-eqos",
			     "snps,dwc-qos-ethernet-4.10";
		reg = <0x0 0x02490000 0x0 0x10000>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
			 <&bpmp TEGRA186_CLK_EQOS_RX>,
			 <&bpmp TEGRA186_CLK_EQOS_TX>,
			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
		resets = <&bpmp TEGRA186_RESET_EQOS>;
		reset-names = "eqos";
		status = "disabled";

		snps,write-requests = <1>;
		snps,read-requests = <3>;
		snps,burst-map = <0x7>;
		snps,txpbl = <32>;
		snps,rxpbl = <8>;
	};

	memory-controller@2c00000 {
		compatible = "nvidia,tegra186-mc";
		reg = <0x0 0x02c00000 0x0 0xb0000>;
		status = "disabled";
	};

	uarta: serial@3100000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x03100000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTA>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTA>;
		reset-names = "serial";
		status = "disabled";
	};

	uartb: serial@3110000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x03110000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTB>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTB>;
		reset-names = "serial";
		status = "disabled";
	};

	uartd: serial@3130000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x03130000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTD>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTD>;
		reset-names = "serial";
		status = "disabled";
	};

	uarte: serial@3140000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x03140000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTE>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTE>;
		reset-names = "serial";
		status = "disabled";
	};

	uartf: serial@3150000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x03150000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTF>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTF>;
		reset-names = "serial";
		status = "disabled";
	};

	gen1_i2c: i2c@3160000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
		reg = <0x0 0x03160000 0x0 0x10000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C1>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C1>;
		reset-names = "i2c";
		status = "disabled";
	};

	cam_i2c: i2c@3180000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
		reg = <0x0 0x03180000 0x0 0x10000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C3>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C3>;
		reset-names = "i2c";
		status = "disabled";
	};

	/* shares pads with dpaux1 */
	dp_aux_ch1_i2c: i2c@3190000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
		reg = <0x0 0x03190000 0x0 0x10000>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C4>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C4>;
		reset-names = "i2c";
		status = "disabled";
	};

	/* controlled by BPMP, should not be enabled */
	pwr_i2c: i2c@31a0000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
		reg = <0x0 0x031a0000 0x0 0x10000>;
		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C5>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C5>;
		reset-names = "i2c";
		status = "disabled";
	};

	/* shares pads with dpaux0 */
	dp_aux_ch0_i2c: i2c@31b0000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
		reg = <0x0 0x031b0000 0x0 0x10000>;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C6>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C6>;
		reset-names = "i2c";
		status = "disabled";
	};

	gen7_i2c: i2c@31c0000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
		reg = <0x0 0x031c0000 0x0 0x10000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C7>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C7>;
		reset-names = "i2c";
		status = "disabled";
	};

	gen9_i2c: i2c@31e0000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
		reg = <0x0 0x031e0000 0x0 0x10000>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C9>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C9>;
		reset-names = "i2c";
		status = "disabled";
	};

	sdmmc1: sdhci@3400000 {
		compatible = "nvidia,tegra186-sdhci";
		reg = <0x0 0x03400000 0x0 0x10000>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
		clock-names = "sdhci";
		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
		reset-names = "sdhci";
		iommus = <&smmu TEGRA186_SID_SDMMC1>;
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
		pinctrl-0 = <&sdmmc1_3v3>;
		pinctrl-1 = <&sdmmc1_1v8>;
		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
		nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
		nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
		nvidia,default-tap = <0x5>;
		nvidia,default-trim = <0xb>;
		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
				  <&bpmp TEGRA186_CLK_PLLP_OUT0>;
		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
		status = "disabled";
	};

	sdmmc2: sdhci@3420000 {
		compatible = "nvidia,tegra186-sdhci";
		reg = <0x0 0x03420000 0x0 0x10000>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
		clock-names = "sdhci";
		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
		reset-names = "sdhci";
		iommus = <&smmu TEGRA186_SID_SDMMC2>;
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
		pinctrl-0 = <&sdmmc2_3v3>;
		pinctrl-1 = <&sdmmc2_1v8>;
		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
		nvidia,default-tap = <0x5>;
		nvidia,default-trim = <0xb>;
		status = "disabled";
	};

	sdmmc3: sdhci@3440000 {
		compatible = "nvidia,tegra186-sdhci";
		reg = <0x0 0x03440000 0x0 0x10000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
		clock-names = "sdhci";
		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
		reset-names = "sdhci";
		iommus = <&smmu TEGRA186_SID_SDMMC3>;
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
		pinctrl-0 = <&sdmmc3_3v3>;
		pinctrl-1 = <&sdmmc3_1v8>;
		nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
		nvidia,default-tap = <0x5>;
		nvidia,default-trim = <0xb>;
		status = "disabled";
	};

	sdmmc4: sdhci@3460000 {
		compatible = "nvidia,tegra186-sdhci";
		reg = <0x0 0x03460000 0x0 0x10000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
		clock-names = "sdhci";
		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
				  <&bpmp TEGRA186_CLK_PLLC4_VCO>;
		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
		reset-names = "sdhci";
		iommus = <&smmu TEGRA186_SID_SDMMC4>;
		nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
		nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
		nvidia,default-tap = <0x9>;
		nvidia,default-trim = <0x5>;
		nvidia,dqs-trim = <63>;
		mmc-hs400-1_8v;
		supports-cqe;
		status = "disabled";
	};

	hda@3510000 {
		compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
		reg = <0x0 0x03510000 0x0 0x10000>;
		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_HDA>,
			 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
			 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
		resets = <&bpmp TEGRA186_RESET_HDA>,
			 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
			 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
		status = "disabled";
	};

	padctl: padctl@3520000 {
		compatible = "nvidia,tegra186-xusb-padctl";
		reg = <0x0 0x03520000 0x0 0x1000>,
		      <0x0 0x03540000 0x0 0x1000>;
		reg-names = "padctl", "ao";

		resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
		reset-names = "padctl";

		status = "disabled";

		pads {
			usb2 {
				clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
				clock-names = "trk";
				status = "disabled";

				lanes {
					usb2-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-1 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-2 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			hsic {
				clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
				clock-names = "trk";
				status = "disabled";

				lanes {
					hsic-0 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			usb3 {
				status = "disabled";

				lanes {
					usb3-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb3-1 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb3-2 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};
		};

		ports {
			usb2-0 {
				status = "disabled";
			};

			usb2-1 {
				status = "disabled";
			};

			usb2-2 {
				status = "disabled";
			};

			hsic-0 {
				status = "disabled";
			};

			usb3-0 {
				status = "disabled";
			};

			usb3-1 {
				status = "disabled";
			};

			usb3-2 {
				status = "disabled";
			};
		};
	};

	usb@3530000 {
		compatible = "nvidia,tegra186-xusb";
		reg = <0x0 0x03530000 0x0 0x8000>,
		      <0x0 0x03538000 0x0 0x1000>;
		reg-names = "hcd", "fpci";

		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
			 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
			 <&bpmp TEGRA186_CLK_XUSB_SS>,
			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
			 <&bpmp TEGRA186_CLK_CLK_M>,
			 <&bpmp TEGRA186_CLK_XUSB_FS>,
			 <&bpmp TEGRA186_CLK_PLLU>,
			 <&bpmp TEGRA186_CLK_CLK_M>,
			 <&bpmp TEGRA186_CLK_PLLE>;
		clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
			      "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
			      "pll_u_480m", "clk_m", "pll_e";

		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
		power-domain-names = "xusb_host", "xusb_ss";
		nvidia,xusb-padctl = <&padctl>;

		status = "disabled";

		#address-cells = <1>;
		#size-cells = <0>;
	};

	fuse@3820000 {
		compatible = "nvidia,tegra186-efuse";
		reg = <0x0 0x03820000 0x0 0x10000>;
		clocks = <&bpmp TEGRA186_CLK_FUSE>;
		clock-names = "fuse";
	};

	gic: interrupt-controller@3881000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x03881000 0x0 0x1000>,
		      <0x0 0x03882000 0x0 0x2000>;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-parent = <&gic>;
	};

	cec@3960000 {
		compatible = "nvidia,tegra186-cec";
		reg = <0x0 0x03960000 0x0 0x10000>;
		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_CEC>;
		clock-names = "cec";
		status = "disabled";
	};

	hsp_top0: hsp@3c00000 {
		compatible = "nvidia,tegra186-hsp";
		reg = <0x0 0x03c00000 0x0 0xa0000>;
		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "doorbell";
		#mbox-cells = <2>;
		status = "disabled";
	};

	gen2_i2c: i2c@c240000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
		reg = <0x0 0x0c240000 0x0 0x10000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C2>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C2>;
		reset-names = "i2c";
		status = "disabled";
	};

	gen8_i2c: i2c@c250000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
		reg = <0x0 0x0c250000 0x0 0x10000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C8>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C8>;
		reset-names = "i2c";
		status = "disabled";
	};

	uartc: serial@c280000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x0c280000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTC>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTC>;
		reset-names = "serial";
		status = "disabled";
	};

	uartg: serial@c290000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x0c290000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTG>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTG>;
		reset-names = "serial";
		status = "disabled";
	};

	rtc: rtc@c2a0000 {
		compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
		reg = <0 0x0c2a0000 0 0x10000>;
		interrupt-parent = <&pmc>;
		interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
		clock-names = "rtc";
		status = "disabled";
	};

	gpio_aon: gpio@c2f0000 {
		compatible = "nvidia,tegra186-gpio-aon";
		reg-names = "security", "gpio";
		reg = <0x0 0xc2f0000 0x0 0x1000>,
		      <0x0 0xc2f1000 0x0 0x1000>;
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	pmc: pmc@c360000 {
		compatible = "nvidia,tegra186-pmc";
		reg = <0 0x0c360000 0 0x10000>,
		      <0 0x0c370000 0 0x10000>,
		      <0 0x0c380000 0 0x10000>,
		      <0 0x0c390000 0 0x10000>;
		reg-names = "pmc", "wake", "aotag", "scratch";

		#interrupt-cells = <2>;
		interrupt-controller;

		sdmmc1_3v3: sdmmc1-3v3 {
			pins = "sdmmc1-hv";
			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
		};

		sdmmc1_1v8: sdmmc1-1v8 {
			pins = "sdmmc1-hv";
			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
		};

		sdmmc2_3v3: sdmmc2-3v3 {
			pins = "sdmmc2-hv";
			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
		};

		sdmmc2_1v8: sdmmc2-1v8 {
			pins = "sdmmc2-hv";
			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
		};

		sdmmc3_3v3: sdmmc3-3v3 {
			pins = "sdmmc3-hv";
			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
		};

		sdmmc3_1v8: sdmmc3-1v8 {
			pins = "sdmmc3-hv";
			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
		};
	};

	ccplex@e000000 {
		compatible = "nvidia,tegra186-ccplex-cluster";
		reg = <0x0 0x0e000000 0x0 0x3fffff>;

		nvidia,bpmp = <&bpmp>;
	};

	pcie@10003000 {
		compatible = "nvidia,tegra186-pcie";
		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
		device_type = "pci";
		reg = <0x0 0x10003000 0x0 0x00000800   /* PADS registers */
		       0x0 0x10003800 0x0 0x00000800   /* AFI registers */
		       0x0 0x40000000 0x0 0x10000000>; /* configuration space */
		reg-names = "pads", "afi", "cs";

		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
		interrupt-names = "intr", "msi";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

		bus-range = <0x00 0xff>;
		#address-cells = <3>;
		#size-cells = <2>;

		ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000   /* port 0 configuration space */
			  0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */
			  0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */
			  0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */
			  0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
			  0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */

		clocks = <&bpmp TEGRA186_CLK_AFI>,
			 <&bpmp TEGRA186_CLK_PCIE>,
			 <&bpmp TEGRA186_CLK_PLLE>;
		clock-names = "afi", "pex", "pll_e";

		resets = <&bpmp TEGRA186_RESET_AFI>,
			 <&bpmp TEGRA186_RESET_PCIE>,
			 <&bpmp TEGRA186_RESET_PCIEXCLK>;
		reset-names = "afi", "pex", "pcie_x";

		status = "disabled";

		pci@1,0 {
			device_type = "pci";
			assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
			reg = <0x000800 0 0 0 0>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <2>;
		};

		pci@2,0 {
			device_type = "pci";
			assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
			reg = <0x001000 0 0 0 0>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <1>;
		};

		pci@3,0 {
			device_type = "pci";
			assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
			reg = <0x001800 0 0 0 0>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <1>;
		};
	};

	smmu: iommu@12000000 {
		compatible = "arm,mmu-500";
		reg = <0 0x12000000 0 0x800000>;
		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
		stream-match-mask = <0x7f80>;
		#global-interrupts = <1>;
		#iommu-cells = <1>;
	};

	host1x@13e00000 {
		compatible = "nvidia,tegra186-host1x", "simple-bus";
		reg = <0x0 0x13e00000 0x0 0x10000>,
		      <0x0 0x13e10000 0x0 0x10000>;
		reg-names = "hypervisor", "vm";
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
		             <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_HOST1X>;
		clock-names = "host1x";
		resets = <&bpmp TEGRA186_RESET_HOST1X>;
		reset-names = "host1x";

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x15000000 0x0 0x15000000 0x01000000>;
		iommus = <&smmu TEGRA186_SID_HOST1X>;

		dpaux1: dpaux@15040000 {
			compatible = "nvidia,tegra186-dpaux";
			reg = <0x15040000 0x10000>;
			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
				 <&bpmp TEGRA186_CLK_PLLDP>;
			clock-names = "dpaux", "parent";
			resets = <&bpmp TEGRA186_RESET_DPAUX1>;
			reset-names = "dpaux";
			status = "disabled";

			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

			state_dpaux1_aux: pinmux-aux {
				groups = "dpaux-io";
				function = "aux";
			};

			state_dpaux1_i2c: pinmux-i2c {
				groups = "dpaux-io";
				function = "i2c";
			};

			state_dpaux1_off: pinmux-off {
				groups = "dpaux-io";
				function = "off";
			};

			i2c-bus {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		display-hub@15200000 {
			compatible = "nvidia,tegra186-display", "simple-bus";
			reg = <0x15200000 0x00040000>;
			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
			reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
				      "wgrp3", "wgrp4", "wgrp5";
			clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
				 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
				 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
			clock-names = "disp", "dsc", "hub";
			status = "disabled";

			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0x15200000 0x15200000 0x40000>;

			display@15200000 {
				compatible = "nvidia,tegra186-dc";
				reg = <0x15200000 0x10000>;
				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
				clock-names = "dc";
				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
				reset-names = "dc";

				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;

				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
				nvidia,head = <0>;
			};

			display@15210000 {
				compatible = "nvidia,tegra186-dc";
				reg = <0x15210000 0x10000>;
				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
				clock-names = "dc";
				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
				reset-names = "dc";

				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;

				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
				nvidia,head = <1>;
			};

			display@15220000 {
				compatible = "nvidia,tegra186-dc";
				reg = <0x15220000 0x10000>;
				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
				clock-names = "dc";
				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
				reset-names = "dc";

				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;

				nvidia,outputs = <&sor0 &sor1>;
				nvidia,head = <2>;
			};
		};

		dsia: dsi@15300000 {
			compatible = "nvidia,tegra186-dsi";
			reg = <0x15300000 0x10000>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA186_CLK_DSI>,
				 <&bpmp TEGRA186_CLK_DSIA_LP>,
				 <&bpmp TEGRA186_CLK_PLLD>;
			clock-names = "dsi", "lp", "parent";
			resets = <&bpmp TEGRA186_RESET_DSI>;
			reset-names = "dsi";
			status = "disabled";

			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
		};

		vic@15340000 {
			compatible = "nvidia,tegra186-vic";
			reg = <0x15340000 0x40000>;
			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA186_CLK_VIC>;
			clock-names = "vic";
			resets = <&bpmp TEGRA186_RESET_VIC>;
			reset-names = "vic";

			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
		};

		dsib: dsi@15400000 {
			compatible = "nvidia,tegra186-dsi";
			reg = <0x15400000 0x10000>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA186_CLK_DSIB>,
				 <&bpmp TEGRA186_CLK_DSIB_LP>,
				 <&bpmp TEGRA186_CLK_PLLD>;
			clock-names = "dsi", "lp", "parent";
			resets = <&bpmp TEGRA186_RESET_DSIB>;
			reset-names = "dsi";
			status = "disabled";

			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
		};

		sor0: sor@15540000 {
			compatible = "nvidia,tegra186-sor";
			reg = <0x15540000 0x10000>;
			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA186_CLK_SOR0>,
				 <&bpmp TEGRA186_CLK_SOR0_OUT>,
				 <&bpmp TEGRA186_CLK_PLLD2>,
				 <&bpmp TEGRA186_CLK_PLLDP>,
				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
				 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
			clock-names = "sor", "out", "parent", "dp", "safe",
				      "pad";
			resets = <&bpmp TEGRA186_RESET_SOR0>;
			reset-names = "sor";
			pinctrl-0 = <&state_dpaux_aux>;
			pinctrl-1 = <&state_dpaux_i2c>;
			pinctrl-2 = <&state_dpaux_off>;
			pinctrl-names = "aux", "i2c", "off";
			status = "disabled";

			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
			nvidia,interface = <0>;
		};

		sor1: sor@15580000 {
			compatible = "nvidia,tegra186-sor1";
			reg = <0x15580000 0x10000>;
			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA186_CLK_SOR1>,
				 <&bpmp TEGRA186_CLK_SOR1_OUT>,
				 <&bpmp TEGRA186_CLK_PLLD3>,
				 <&bpmp TEGRA186_CLK_PLLDP>,
				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
				 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
			clock-names = "sor", "out", "parent", "dp", "safe",
				      "pad";
			resets = <&bpmp TEGRA186_RESET_SOR1>;
			reset-names = "sor";
			pinctrl-0 = <&state_dpaux1_aux>;
			pinctrl-1 = <&state_dpaux1_i2c>;
			pinctrl-2 = <&state_dpaux1_off>;
			pinctrl-names = "aux", "i2c", "off";
			status = "disabled";

			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
			nvidia,interface = <1>;
		};

		dpaux: dpaux@155c0000 {
			compatible = "nvidia,tegra186-dpaux";
			reg = <0x155c0000 0x10000>;
			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA186_CLK_DPAUX>,
				 <&bpmp TEGRA186_CLK_PLLDP>;
			clock-names = "dpaux", "parent";
			resets = <&bpmp TEGRA186_RESET_DPAUX>;
			reset-names = "dpaux";
			status = "disabled";

			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

			state_dpaux_aux: pinmux-aux {
				groups = "dpaux-io";
				function = "aux";
			};

			state_dpaux_i2c: pinmux-i2c {
				groups = "dpaux-io";
				function = "i2c";
			};

			state_dpaux_off: pinmux-off {
				groups = "dpaux-io";
				function = "off";
			};

			i2c-bus {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		padctl@15880000 {
			compatible = "nvidia,tegra186-dsi-padctl";
			reg = <0x15880000 0x10000>;
			resets = <&bpmp TEGRA186_RESET_DSI>;
			reset-names = "dsi";
			status = "disabled";
		};

		dsic: dsi@15900000 {
			compatible = "nvidia,tegra186-dsi";
			reg = <0x15900000 0x10000>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA186_CLK_DSIC>,
				 <&bpmp TEGRA186_CLK_DSIC_LP>,
				 <&bpmp TEGRA186_CLK_PLLD>;
			clock-names = "dsi", "lp", "parent";
			resets = <&bpmp TEGRA186_RESET_DSIC>;
			reset-names = "dsi";
			status = "disabled";

			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
		};

		dsid: dsi@15940000 {
			compatible = "nvidia,tegra186-dsi";
			reg = <0x15940000 0x10000>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA186_CLK_DSID>,
				 <&bpmp TEGRA186_CLK_DSID_LP>,
				 <&bpmp TEGRA186_CLK_PLLD>;
			clock-names = "dsi", "lp", "parent";
			resets = <&bpmp TEGRA186_RESET_DSID>;
			reset-names = "dsi";
			status = "disabled";

			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
		};
	};

	gpu@17000000 {
		compatible = "nvidia,gp10b";
		reg = <0x0 0x17000000 0x0 0x1000000>,
		      <0x0 0x18000000 0x0 0x1000000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "stall", "nonstall";

		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
			 <&bpmp TEGRA186_CLK_GPU>;
		clock-names = "gpu", "pwr";
		resets = <&bpmp TEGRA186_RESET_GPU>;
		reset-names = "gpu";
		status = "disabled";

		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
	};

	sysram@30000000 {
		compatible = "nvidia,tegra186-sysram", "mmio-sram";
		reg = <0x0 0x30000000 0x0 0x50000>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;

		cpu_bpmp_tx: shmem@4e000 {
			compatible = "nvidia,tegra186-bpmp-shmem";
			reg = <0x0 0x4e000 0x0 0x1000>;
			label = "cpu-bpmp-tx";
			pool;
		};

		cpu_bpmp_rx: shmem@4f000 {
			compatible = "nvidia,tegra186-bpmp-shmem";
			reg = <0x0 0x4f000 0x0 0x1000>;
			label = "cpu-bpmp-rx";
			pool;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "nvidia,tegra186-denver";
			device_type = "cpu";
			reg = <0x000>;
		};

		cpu@1 {
			compatible = "nvidia,tegra186-denver";
			device_type = "cpu";
			reg = <0x001>;
		};

		cpu@2 {
			compatible = "arm,cortex-a57";
			device_type = "cpu";
			reg = <0x100>;
		};

		cpu@3 {
			compatible = "arm,cortex-a57";
			device_type = "cpu";
			reg = <0x101>;
		};

		cpu@4 {
			compatible = "arm,cortex-a57";
			device_type = "cpu";
			reg = <0x102>;
		};

		cpu@5 {
			compatible = "arm,cortex-a57";
			device_type = "cpu";
			reg = <0x103>;
		};
	};

	bpmp: bpmp {
		compatible = "nvidia,tegra186-bpmp";
		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
				    TEGRA_HSP_DB_MASTER_BPMP>;
		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		#power-domain-cells = <1>;

		bpmp_i2c: i2c {
			compatible = "nvidia,tegra186-bpmp-i2c";
			nvidia,bpmp-bus-id = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		bpmp_thermal: thermal {
			compatible = "nvidia,tegra186-bpmp-thermal";
			#thermal-sensor-cells = <1>;
		};
	};

	thermal-zones {
		a57 {
			polling-delay = <0>;
			polling-delay-passive = <1000>;

			thermal-sensors =
				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;

			trips {
				critical {
					temperature = <101000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
			};
		};

		denver {
			polling-delay = <0>;
			polling-delay-passive = <1000>;

			thermal-sensors =
				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;

			trips {
				critical {
					temperature = <101000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
			};
		};

		gpu {
			polling-delay = <0>;
			polling-delay-passive = <1000>;

			thermal-sensors =
				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;

			trips {
				critical {
					temperature = <101000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
			};
		};

		pll {
			polling-delay = <0>;
			polling-delay-passive = <1000>;

			thermal-sensors =
				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;

			trips {
				critical {
					temperature = <101000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
			};
		};

		always_on {
			polling-delay = <0>;
			polling-delay-passive = <1000>;

			thermal-sensors =
				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;

			trips {
				critical {
					temperature = <101000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&gic>;
	};
};