summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
blob: 887dffe1491087a8dfd2eb0e981928506db2af9a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
 *
 * Copyright (C) 2021 Renesas Electronics Corp.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

/ {
	aliases {
		serial1 = &scif2;
		i2c3 = &i2c3;
	};

	osc1: cec-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12000000>;
	};

	hdmi-out {
		compatible = "hdmi-connector";
		type = "d";

		port {
			hdmi_con_out: endpoint {
				remote-endpoint = <&adv7535_out>;
			};
		};
	};
};

&cpu_dai {
	sound-dai = <&ssi0>;
};

&dsi {
	status = "okay";

	ports {
		port@1 {
			dsi0_out: endpoint {
				data-lanes = <1 2 3 4>;
				remote-endpoint = <&adv7535_in>;
			};
		};
	};
};

&du {
	status = "okay";
};

&i2c1 {
	adv7535: hdmi@3d {
		compatible = "adi,adv7535";
		reg = <0x3d>;

		interrupt-parent = <&pinctrl>;
		interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
		clocks = <&osc1>;
		clock-names = "cec";
		avdd-supply = <&reg_1p8v>;
		dvdd-supply = <&reg_1p8v>;
		pvdd-supply = <&reg_1p8v>;
		a2vdd-supply = <&reg_1p8v>;
		v3p3-supply = <&reg_3p3v>;
		v1p2-supply = <&reg_1p8v>;

		adi,dsi-lanes = <4>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7535_in: endpoint {
					remote-endpoint = <&dsi0_out>;
				};
			};

			port@1 {
				reg = <1>;
				adv7535_out: endpoint {
					remote-endpoint = <&hdmi_con_out>;
				};
			};
		};
	};
};

&i2c3 {
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-names = "default";
	clock-frequency = <400000>;

	status = "okay";

	wm8978: codec@1a {
		compatible = "wlf,wm8978";
		#sound-dai-cells = <0>;
		reg = <0x1a>;
	};

	versa3: clock-generator@68 {
		compatible = "renesas,5p35023";
		reg = <0x68>;
		#clock-cells = <1>;
		clocks = <&x1>;

		renesas,settings = [
			80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
			00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
			80 b0 45 c4 95
		];

		assigned-clocks = <&versa3 0>, <&versa3 1>,
				  <&versa3 2>, <&versa3 3>,
				  <&versa3 4>, <&versa3 5>;
		assigned-clock-rates = <24000000>, <11289600>,
				       <11289600>, <12000000>,
				       <25000000>, <12288000>;
	};
};

#if PMOD_MTU3
&mtu3 {
	pinctrl-0 = <&mtu3_pins>;
	pinctrl-names = "default";

	status = "okay";
};

#if MTU3_COUNTER_Z_PHASE_SIGNAL
/* SDHI cd pin is muxed with counter Z phase signal */
&sdhi1 {
	status = "disabled";
};
#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */

&spi1 {
	status = "disabled";
};
#endif /* PMOD_MTU3 */

/*
 * To enable SCIF2 (SER0) on PMOD1 (CN7)
 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
 * SW2 should be at position 2->3 so that SER0_TX line is activated
 * SW3 should be at position 2->3 so that SER0_RX line is activated
 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
 */
#if PMOD1_SER0
&scif2 {
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

	uart-has-rtscts;
	status = "okay";
};
#endif

&ssi0 {
	pinctrl-0 = <&ssi0_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&vccq_sdhi1 {
	gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
};