summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
blob: d759478e1c84606a8a843a6411496d8b8016b5c1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
 * Copyright (c) 2020 Engicam srl
 * Copyright (c) 2020 Amarula Solutions(India)
 */

/dts-v1/;
#include "px30.dtsi"
#include "px30-engicam-edimm2.2.dtsi"
#include "px30-engicam-px30-core.dtsi"

/ {
	model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
	compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
		     "rockchip,px30";

	chosen {
		stdout-path = "serial2:115200n8";
	};
};

&pinctrl {
	bt {
		bt_enable_h: bt-enable-h {
			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	sdio-pwrseq {
		wifi_enable_h: wifi-enable-h {
			rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&sdio_pwrseq {
	reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
};

&vcc3v3_btreg {
	enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
};