arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts


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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (c) 2016 Xunlong Software. Co., Ltd.
 * (http://www.orangepi.org)
 *
 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
 */

/dts-v1/;
#include "rk3328-orangepi-r1-plus.dts"

/ {
	model = "Xunlong Orange Pi R1 Plus LTS";
	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
};

&gmac2io {
	phy-handle = <&yt8531c>;
	tx_delay = <0x19>;
	rx_delay = <0x05>;

	mdio {
		/delete-node/ ethernet-phy@1;

		yt8531c: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;

			motorcomm,auto-sleep-disabled;
			motorcomm,clk-out-frequency-hz = <125000000>;
			motorcomm,keep-pll-enabled;
			motorcomm,rx-clk-drv-microamp = <5020>;
			motorcomm,rx-data-drv-microamp = <5020>;

			pinctrl-0 = <&eth_phy_reset_pin>;
			pinctrl-names = "default";
			reset-assert-us = <15000>;
			reset-deassert-us = <50000>;
			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
		};
	};
};