summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
blob: 0e0b234581c637c89983eb04a3754aa2eaa0c101 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for AM625 SoC Family MCU Domain peripherals
 *
 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

&cbass_mcu {
	mcu_pmx0: pinctrl@4084000 {
		bootph-all;
		compatible = "pinctrl-single";
		reg = <0x00 0x04084000 0x00 0x88>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	mcu_esm: esm@4100000 {
		bootph-pre-ram;
		compatible = "ti,j721e-esm";
		reg = <0x00 0x4100000 0x00 0x1000>;
		ti,esm-pins = <0>, <1>, <2>, <85>;
	};

	/*
	 * The MCU domain timer interrupts are routed only to the ESM module,
	 * and not currently available for Linux. The MCU domain timers are
	 * of limited use without interrupts, and likely reserved by the ESM.
	 */
	mcu_timer0: timer@4800000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x4800000 0x00 0x400>;
		clocks = <&k3_clks 35 2>;
		clock-names = "fck";
		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	mcu_timer1: timer@4810000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x4810000 0x00 0x400>;
		clocks = <&k3_clks 48 2>;
		clock-names = "fck";
		power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	mcu_timer2: timer@4820000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x4820000 0x00 0x400>;
		clocks = <&k3_clks 49 2>;
		clock-names = "fck";
		power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	mcu_timer3: timer@4830000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x4830000 0x00 0x400>;
		clocks = <&k3_clks 50 2>;
		clock-names = "fck";
		power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	mcu_uart0: serial@4a00000 {
		compatible = "ti,am64-uart", "ti,am654-uart";
		reg = <0x00 0x04a00000 0x00 0x100>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 149 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	mcu_i2c0: i2c@4900000 {
		compatible = "ti,am64-i2c", "ti,omap4-i2c";
		reg = <0x00 0x04900000 0x00 0x100>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 106 2>;
		clock-names = "fck";
		status = "disabled";
	};

	mcu_spi0: spi@4b00000 {
		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
		reg = <0x00 0x04b00000 0x00 0x400>;
		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 147 0>;
		status = "disabled";
	};

	mcu_spi1: spi@4b10000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x04b10000 0x00 0x400>;
		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 148 0>;
		status = "disabled";
	};

	mcu_gpio_intr: interrupt-controller@4210000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x04210000 0x00 0x200>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <5>;
		ti,interrupt-ranges = <0 104 4>;
	};

	mcu_gpio0: gpio@4201000 {
		compatible = "ti,am64-gpio", "ti,keystone-gpio";
		reg = <0x00 0x4201000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&mcu_gpio_intr>;
		interrupts = <30>, <31>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <24>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 79 0>;
		clock-names = "gpio";
	};

	mcu_rti0: watchdog@4880000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x00 0x04880000 0x00 0x100>;
		clocks = <&k3_clks 131 0>;
		power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 131 0>;
		assigned-clock-parents = <&k3_clks 131 2>;
		/* Tightly coupled to M4F */
		status = "reserved";
	};

	mcu_mcan0: can@4e08000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x4e08000 0x00 0x200>,
		      <0x00 0x4e00000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
		clock-names = "hclk", "cclk";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	mcu_mcan1: can@4e18000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x4e18000 0x00 0x200>,
		      <0x00 0x4e10000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
		clock-names = "hclk", "cclk";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};
};