summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
blob: e5be78a58682d542a3ce90a0956409b8bcef9a91 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
 *
 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
 */

&cbass_mcu_wakeup {
	dmsc: system-controller@44083000 {
		compatible = "ti,k2g-sci";
		ti,host-id = <12>;

		mbox-names = "rx", "tx";

		mboxes = <&secure_proxy_main 11>,
			 <&secure_proxy_main 13>;

		reg-names = "debug_messages";
		reg = <0x00 0x44083000 0x00 0x1000>;

		k3_pds: power-controller {
			compatible = "ti,sci-pm-domain";
			#power-domain-cells = <2>;
		};

		k3_clks: clock-controller {
			compatible = "ti,k2g-sci-clk";
			#clock-cells = <2>;
		};

		k3_reset: reset-controller {
			compatible = "ti,sci-reset";
			#reset-cells = <2>;
		};
	};

	mcu_conf: syscon@40f00000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x00 0x40f00000 0x00 0x20000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x40f00000 0x20000>;

		phy_gmii_sel: phy@4040 {
			compatible = "ti,am654-phy-gmii-sel";
			reg = <0x4040 0x4>;
			#phy-cells = <1>;
		};
	};

	chipid@43000014 {
		compatible = "ti,am654-chipid";
		reg = <0x00 0x43000014 0x00 0x4>;
	};

	wkup_pmx0: pinctrl@4301c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x00 0x4301c000 0x00 0x178>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	mcu_ram: sram@41c00000 {
		compatible = "mmio-sram";
		reg = <0x00 0x41c00000 0x00 0x100000>;
		ranges = <0x00 0x00 0x41c00000 0x100000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	wkup_uart0: serial@42300000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x42300000 0x00 0x100>;
		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 287 2>;
		clock-names = "fclk";
	};

	mcu_uart0: serial@40a00000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x40a00000 0x00 0x100>;
		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <96000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 149 2>;
		clock-names = "fclk";
	};

	wkup_gpio_intr: interrupt-controller@42200000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x42200000 0x00 0x400>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <137>;
		ti,interrupt-ranges = <16 960 16>;
	};

	wkup_gpio0: gpio@42110000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x42110000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&wkup_gpio_intr>;
		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <85>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 113 0>;
		clock-names = "gpio";
	};

	wkup_gpio1: gpio@42100000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x42100000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&wkup_gpio_intr>;
		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <85>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 114 0>;
		clock-names = "gpio";
	};

	mcu_navss: bus@28380000 {
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
		dma-coherent;
		dma-ranges;
		ti,sci-dev-id = <232>;

		mcu_ringacc: ringacc@2b800000 {
			compatible = "ti,am654-navss-ringacc";
			reg =	<0x00 0x2b800000 0x00 0x400000>,
				<0x00 0x2b000000 0x00 0x400000>,
				<0x00 0x28590000 0x00 0x100>,
				<0x00 0x2a500000 0x00 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <286>;
			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <235>;
			msi-parent = <&main_udmass_inta>;
		};

		mcu_udmap: dma-controller@285c0000 {
			compatible = "ti,j721e-navss-mcu-udmap";
			reg =	<0x00 0x285c0000 0x00 0x100>,
				<0x00 0x2a800000 0x00 0x40000>,
				<0x00 0x2aa00000 0x00 0x40000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&dmsc>;
			ti,sci-dev-id = <236>;
			ti,ringacc = <&mcu_ringacc>;

			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>; /* TX_HCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>; /* RX_HCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};
	};

	mcu_cpsw: ethernet@46000000 {
		compatible = "ti,j721e-cpsw-nuss";
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x00 0x46000000 0x00 0x200000>;
		reg-names = "cpsw_nuss";
		ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
		dma-coherent;
		clocks = <&k3_clks 18 21>;
		clock-names = "fck";
		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;

		dmas = <&mcu_udmap 0xf000>,
		       <&mcu_udmap 0xf001>,
		       <&mcu_udmap 0xf002>,
		       <&mcu_udmap 0xf003>,
		       <&mcu_udmap 0xf004>,
		       <&mcu_udmap 0xf005>,
		       <&mcu_udmap 0xf006>,
		       <&mcu_udmap 0xf007>,
		       <&mcu_udmap 0x7000>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			cpsw_port1: port@1 {
				reg = <1>;
				ti,mac-only;
				label = "port1";
				ti,syscon-efuse = <&mcu_conf 0x200>;
				phys = <&phy_gmii_sel 1>;
			};
		};

		davinci_mdio: mdio@f00 {
			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
			reg = <0x00 0xf00 0x00 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&k3_clks 18 21>;
			clock-names = "fck";
			bus_freq = <1000000>;
		};

		cpts@3d000 {
			compatible = "ti,am65-cpts";
			reg = <0x00 0x3d000 0x00 0x400>;
			clocks = <&k3_clks 18 2>;
			clock-names = "cpts";
			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cpts";
			ti,cpts-ext-ts-inputs = <4>;
			ti,cpts-periodic-outputs = <2>;
		};
	};

	mcu_i2c0: i2c@40b00000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x40b00000 0x00 0x100>;
		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 194 1>;
		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
	};

	mcu_i2c1: i2c@40b10000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x40b10000 0x00 0x100>;
		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 195 1>;
		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
	};

	wkup_i2c0: i2c@42120000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x42120000 0x00 0x100>;
		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 197 1>;
		power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
	};

	fss: syscon@47000000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x00 0x47000000 0x00 0x100>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hbmc_mux: hbmc-mux {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x4 0x2>; /* HBMC select */
		};

		hbmc: hyperbus@47034000 {
			compatible = "ti,am654-hbmc";
			reg = <0x00 0x47034000 0x00 0x100>,
				<0x05 0x00000000 0x01 0x0000000>;
			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
			clocks = <&k3_clks 102 0>;
			assigned-clocks = <&k3_clks 102 5>;
			assigned-clock-rates = <333333333>;
			#address-cells = <2>;
			#size-cells = <1>;
			mux-controls = <&hbmc_mux 0>;
		};

		ospi0: spi@47040000 {
			compatible = "ti,am654-ospi", "cdns,qspi-nor";
			reg = <0x0 0x47040000 0x0 0x100>,
			      <0x5 0x00000000 0x1 0x0000000>;
			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
			cdns,fifo-depth = <256>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x0>;
			clocks = <&k3_clks 103 0>;
			assigned-clocks = <&k3_clks 103 0>;
			assigned-clock-parents = <&k3_clks 103 2>;
			assigned-clock-rates = <166666666>;
			power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	tscadc0: tscadc@40200000 {
		compatible = "ti,am3359-tscadc";
		reg = <0x00 0x40200000 0x00 0x1000>;
		interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 0 1>;
		assigned-clocks = <&k3_clks 0 3>;
		assigned-clock-rates = <60000000>;
		clock-names = "adc_tsc_fck";
		dmas = <&main_udmap 0x7400>,
			<&main_udmap 0x7401>;
		dma-names = "fifo0", "fifo1";

		adc {
			#io-channel-cells = <1>;
			compatible = "ti,am3359-adc";
		};
	};

	mcu_r5fss0: r5fss@41000000 {
		compatible = "ti,j7200-r5fss";
		ti,cluster-mode = <1>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x41000000 0x00 0x41000000 0x20000>,
			 <0x41400000 0x00 0x41400000 0x20000>;
		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;

		mcu_r5fss0_core0: r5f@41000000 {
			compatible = "ti,j7200-r5f";
			reg = <0x41000000 0x00010000>,
			      <0x41010000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <250>;
			ti,sci-proc-ids = <0x01 0xff>;
			resets = <&k3_reset 250 1>;
			firmware-name = "j7200-mcu-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		mcu_r5fss0_core1: r5f@41400000 {
			compatible = "ti,j7200-r5f";
			reg = <0x41400000 0x00008000>,
			      <0x41410000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <251>;
			ti,sci-proc-ids = <0x02 0xff>;
			resets = <&k3_reset 251 1>;
			firmware-name = "j7200-mcu-r5f0_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	mcu_crypto: crypto@40900000 {
		compatible = "ti,j721e-sa2ul";
		reg = <0x00 0x40900000 0x00 0x1200>;
		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
		       <&mcu_udmap 0x7503>;
		dma-names = "tx", "rx1", "rx2";
		dma-coherent;

		rng: rng@40910000 {
			compatible = "inside-secure,safexcel-eip76";
			reg = <0x00 0x40910000 0x00 0x7d>;
			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled"; /* Used by OP-TEE */
		};
	};
};