summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
blob: e172fa05c9a008cbc1d9ac3ec8074c9918595185 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
// SPDX-License-Identifier: GPL-2.0+
/*
 * Clock specification for Xilinx ZynqMP
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */

#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
	pss_ref_clk: pss_ref_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>;
	};

	video_clk: video_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};

	pss_alt_ref_clk: pss_alt_ref_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	gt_crx_ref_clk: gt_crx_ref_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <108000000>;
	};

	aux_ref_clk: aux_ref_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};
};

&zynqmp_firmware {
	zynqmp_clk: clock-controller {
		#clock-cells = <1>;
		compatible = "xlnx,zynqmp-clk";
		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
			 <&aux_ref_clk>, <&gt_crx_ref_clk>;
		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
			      "aux_ref_clk", "gt_crx_ref_clk";
	};
};

&can0 {
	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&can1 {
	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&cpu0 {
	clocks = <&zynqmp_clk ACPU>;
};

&fpd_dma_chan1 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan2 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan3 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan4 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan5 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan6 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan7 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan8 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan1 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan2 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan3 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan4 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan5 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan6 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan7 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan8 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&nand0 {
	clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&gem0 {
	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
		 <&zynqmp_clk GEM_TSU>;
	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};

&gem1 {
	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
		 <&zynqmp_clk GEM_TSU>;
	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};

&gem2 {
	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
		 <&zynqmp_clk GEM_TSU>;
	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};

&gem3 {
	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
		 <&zynqmp_clk GEM_TSU>;
	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};

&gpio {
	clocks = <&zynqmp_clk LPD_LSBUS>;
};

&i2c0 {
	clocks = <&zynqmp_clk I2C0_REF>;
};

&i2c1 {
	clocks = <&zynqmp_clk I2C1_REF>;
};

&pcie {
	clocks = <&zynqmp_clk PCIE_REF>;
};

&qspi {
	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&sata {
	clocks = <&zynqmp_clk SATA_REF>;
};

&sdhci0 {
	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&sdhci1 {
	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&spi0 {
	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&spi1 {
	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&ttc0 {
	clocks = <&zynqmp_clk LPD_LSBUS>;
};

&ttc1 {
	clocks = <&zynqmp_clk LPD_LSBUS>;
};

&ttc2 {
	clocks = <&zynqmp_clk LPD_LSBUS>;
};

&ttc3 {
	clocks = <&zynqmp_clk LPD_LSBUS>;
};

&uart0 {
	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&uart1 {
	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&dwc3_0 {
	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};

&dwc3_1 {
	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};

&watchdog0 {
	clocks = <&zynqmp_clk WDT>;
};

&lpd_watchdog {
	clocks = <&zynqmp_clk LPD_WDT>;
};

&xilinx_ams {
	clocks = <&zynqmp_clk AMS_REF>;
};

&zynqmp_dpdma {
	clocks = <&zynqmp_clk DPDMA_REF>;
};

&zynqmp_dpsub {
	clocks = <&zynqmp_clk TOPSW_LSBUS>,
		 <&zynqmp_clk DP_AUDIO_REF>,
		 <&zynqmp_clk DP_VIDEO_REF>;
};