summaryrefslogtreecommitdiff
path: root/arch/blackfin/kernel/cacheinit.c
blob: 62cbba7364b0d066b5559e4f1a7add76567722ef (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
/*
 *               Copyright 2004-2007 Analog Devices Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/cpu.h>

#include <asm/cacheflush.h>
#include <asm/blackfin.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h>

#if defined(CONFIG_BFIN_ICACHE)
void bfin_icache_init(void)
{
	unsigned long *table = icplb_table;
	unsigned long ctrl;
	int i;

	for (i = 0; i < MAX_CPLBS; i++) {
		unsigned long addr = *table++;
		unsigned long data = *table++;
		if (addr == (unsigned long)-1)
			break;
		bfin_write32(ICPLB_ADDR0 + i * 4, addr);
		bfin_write32(ICPLB_DATA0 + i * 4, data);
	}
	ctrl = bfin_read_IMEM_CONTROL();
	ctrl |= IMC | ENICPLB;
	bfin_write_IMEM_CONTROL(ctrl);
}
#endif

#if defined(CONFIG_BFIN_DCACHE)
void bfin_dcache_init(void)
{
	unsigned long *table = dcplb_table;
	unsigned long ctrl;
	int i;

	for (i = 0; i < MAX_CPLBS; i++) {
		unsigned long addr = *table++;
		unsigned long data = *table++;
		if (addr == (unsigned long)-1)
			break;
		bfin_write32(DCPLB_ADDR0 + i * 4, addr);
		bfin_write32(DCPLB_DATA0 + i * 4, data);
	}
	ctrl = bfin_read_DMEM_CONTROL();
	ctrl |= DMEM_CNTR;
	bfin_write_DMEM_CONTROL(ctrl);
}
#endif