summaryrefslogtreecommitdiff
path: root/arch/c6x/boot/dts/tms320c6678.dtsi
blob: da1e3f2bf06220b76e00bc99bf4f06ca8db85f93 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
// SPDX-License-Identifier: GPL-2.0

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			reg = <0>;
			model = "ti,c66x";
		};
		cpu@1 {
			device_type = "cpu";
			reg = <1>;
			model = "ti,c66x";
		};
		cpu@2 {
			device_type = "cpu";
			reg = <2>;
			model = "ti,c66x";
		};
		cpu@3 {
			device_type = "cpu";
			reg = <3>;
			model = "ti,c66x";
		};
		cpu@4 {
			device_type = "cpu";
			reg = <4>;
			model = "ti,c66x";
		};
		cpu@5 {
			device_type = "cpu";
			reg = <5>;
			model = "ti,c66x";
		};
		cpu@6 {
			device_type = "cpu";
			reg = <6>;
			model = "ti,c66x";
		};
		cpu@7 {
			device_type = "cpu";
			reg = <7>;
			model = "ti,c66x";
		};
	};

	soc {
		compatible = "simple-bus";
		model = "tms320c6678";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		core_pic: interrupt-controller {
			compatible = "ti,c64x+core-pic";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		megamod_pic: interrupt-controller@1800000 {
		       compatible = "ti,c64x+megamod-pic";
		       interrupt-controller;
		       #interrupt-cells = <1>;
		       reg = <0x1800000 0x1000>;
		       interrupt-parent = <&core_pic>;
		};

		cache-controller@1840000 {
			compatible = "ti,c64x+cache";
			reg = <0x01840000 0x8400>;
		};

		timer8: timer@2280000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x01 >;
			reg = <0x2280000 0x40>;
		};

		timer9: timer@2290000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x02 >;
			reg = <0x2290000 0x40>;
		};

		timer10: timer@22A0000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x04 >;
			reg = <0x22A0000 0x40>;
		};

		timer11: timer@22B0000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x08 >;
			reg = <0x22B0000 0x40>;
		};

		timer12: timer@22C0000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x10 >;
			reg = <0x22C0000 0x40>;
		};

		timer13: timer@22D0000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x20 >;
			reg = <0x22D0000 0x40>;
		};

		timer14: timer@22E0000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x40 >;
			reg = <0x22E0000 0x40>;
		};

		timer15: timer@22F0000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x80 >;
			reg = <0x22F0000 0x40>;
		};

		clock-controller@2310000 {
			compatible = "ti,c6678-pll", "ti,c64x+pll";
			reg = <0x02310000 0x200>;
			ti,c64x+pll-bypass-delay = <200>;
			ti,c64x+pll-reset-delay = <12000>;
			ti,c64x+pll-lock-delay = <80000>;
		};

		device-state-controller@2620000 {
			compatible = "ti,c64x+dscr";
			reg = <0x02620000 0x1000>;

			ti,dscr-devstat = <0x20>;
			ti,dscr-silicon-rev = <0x18 28 0xf>;

			ti,dscr-mac-fuse-regs = <0x110 1 2 3 4
						 0x114 5 6 0 0>;

		};
	};
};