summaryrefslogtreecommitdiff
path: root/arch/csky/kernel/perf_event.c
blob: e5f18420ce641970da50f5419e6a370521d5438a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.

#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/perf_event.h>
#include <linux/platform_device.h>

#define CSKY_PMU_MAX_EVENTS 32
#define DEFAULT_COUNT_WIDTH 48

#define HPCR		"<0, 0x0>"      /* PMU Control reg */
#define HPSPR		"<0, 0x1>"      /* Start PC reg */
#define HPEPR		"<0, 0x2>"      /* End PC reg */
#define HPSIR		"<0, 0x3>"      /* Soft Counter reg */
#define HPCNTENR	"<0, 0x4>"      /* Count Enable reg */
#define HPINTENR	"<0, 0x5>"      /* Interrupt Enable reg */
#define HPOFSR		"<0, 0x6>"      /* Interrupt Status reg */

/* The events for a given PMU register set. */
struct pmu_hw_events {
	/*
	 * The events that are active on the PMU for the given index.
	 */
	struct perf_event *events[CSKY_PMU_MAX_EVENTS];

	/*
	 * A 1 bit for an index indicates that the counter is being used for
	 * an event. A 0 means that the counter can be used.
	 */
	unsigned long used_mask[BITS_TO_LONGS(CSKY_PMU_MAX_EVENTS)];
};

static uint64_t (*hw_raw_read_mapping[CSKY_PMU_MAX_EVENTS])(void);
static void (*hw_raw_write_mapping[CSKY_PMU_MAX_EVENTS])(uint64_t val);

static struct csky_pmu_t {
	struct pmu			pmu;
	struct pmu_hw_events __percpu	*hw_events;
	struct platform_device		*plat_device;
	uint32_t			count_width;
	uint32_t			hpcr;
	u64				max_period;
} csky_pmu;
static int csky_pmu_irq;

#define to_csky_pmu(p)  (container_of(p, struct csky_pmu, pmu))

#define cprgr(reg)				\
({						\
	unsigned int tmp;			\
	asm volatile("cprgr %0, "reg"\n"	\
		     : "=r"(tmp)		\
		     :				\
		     : "memory");		\
	tmp;					\
})

#define cpwgr(reg, val)		\
({				\
	asm volatile(		\
	"cpwgr %0, "reg"\n"	\
	:			\
	: "r"(val)		\
	: "memory");		\
})

#define cprcr(reg)				\
({						\
	unsigned int tmp;			\
	asm volatile("cprcr %0, "reg"\n"	\
		     : "=r"(tmp)		\
		     :				\
		     : "memory");		\
	tmp;					\
})

#define cpwcr(reg, val)		\
({				\
	asm volatile(		\
	"cpwcr %0, "reg"\n"	\
	:			\
	: "r"(val)		\
	: "memory");		\
})

/* cycle counter */
uint64_t csky_pmu_read_cc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x3>");
		lo  = cprgr("<0, 0x2>");
		hi  = cprgr("<0, 0x3>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_cc(uint64_t val)
{
	cpwgr("<0, 0x2>", (uint32_t)  val);
	cpwgr("<0, 0x3>", (uint32_t) (val >> 32));
}

/* instruction counter */
static uint64_t csky_pmu_read_ic(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x5>");
		lo  = cprgr("<0, 0x4>");
		hi  = cprgr("<0, 0x5>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_ic(uint64_t val)
{
	cpwgr("<0, 0x4>", (uint32_t)  val);
	cpwgr("<0, 0x5>", (uint32_t) (val >> 32));
}

/* l1 icache access counter */
static uint64_t csky_pmu_read_icac(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x7>");
		lo  = cprgr("<0, 0x6>");
		hi  = cprgr("<0, 0x7>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_icac(uint64_t val)
{
	cpwgr("<0, 0x6>", (uint32_t)  val);
	cpwgr("<0, 0x7>", (uint32_t) (val >> 32));
}

/* l1 icache miss counter */
static uint64_t csky_pmu_read_icmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x9>");
		lo  = cprgr("<0, 0x8>");
		hi  = cprgr("<0, 0x9>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_icmc(uint64_t val)
{
	cpwgr("<0, 0x8>", (uint32_t)  val);
	cpwgr("<0, 0x9>", (uint32_t) (val >> 32));
}

/* l1 dcache access counter */
static uint64_t csky_pmu_read_dcac(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0xb>");
		lo  = cprgr("<0, 0xa>");
		hi  = cprgr("<0, 0xb>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_dcac(uint64_t val)
{
	cpwgr("<0, 0xa>", (uint32_t)  val);
	cpwgr("<0, 0xb>", (uint32_t) (val >> 32));
}

/* l1 dcache miss counter */
static uint64_t csky_pmu_read_dcmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0xd>");
		lo  = cprgr("<0, 0xc>");
		hi  = cprgr("<0, 0xd>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_dcmc(uint64_t val)
{
	cpwgr("<0, 0xc>", (uint32_t)  val);
	cpwgr("<0, 0xd>", (uint32_t) (val >> 32));
}

/* l2 cache access counter */
static uint64_t csky_pmu_read_l2ac(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0xf>");
		lo  = cprgr("<0, 0xe>");
		hi  = cprgr("<0, 0xf>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_l2ac(uint64_t val)
{
	cpwgr("<0, 0xe>", (uint32_t)  val);
	cpwgr("<0, 0xf>", (uint32_t) (val >> 32));
}

/* l2 cache miss counter */
static uint64_t csky_pmu_read_l2mc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x11>");
		lo  = cprgr("<0, 0x10>");
		hi  = cprgr("<0, 0x11>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_l2mc(uint64_t val)
{
	cpwgr("<0, 0x10>", (uint32_t)  val);
	cpwgr("<0, 0x11>", (uint32_t) (val >> 32));
}

/* I-UTLB miss counter */
static uint64_t csky_pmu_read_iutlbmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x15>");
		lo  = cprgr("<0, 0x14>");
		hi  = cprgr("<0, 0x15>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_iutlbmc(uint64_t val)
{
	cpwgr("<0, 0x14>", (uint32_t)  val);
	cpwgr("<0, 0x15>", (uint32_t) (val >> 32));
}

/* D-UTLB miss counter */
static uint64_t csky_pmu_read_dutlbmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x17>");
		lo  = cprgr("<0, 0x16>");
		hi  = cprgr("<0, 0x17>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_dutlbmc(uint64_t val)
{
	cpwgr("<0, 0x16>", (uint32_t)  val);
	cpwgr("<0, 0x17>", (uint32_t) (val >> 32));
}

/* JTLB miss counter */
static uint64_t csky_pmu_read_jtlbmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x19>");
		lo  = cprgr("<0, 0x18>");
		hi  = cprgr("<0, 0x19>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_jtlbmc(uint64_t val)
{
	cpwgr("<0, 0x18>", (uint32_t)  val);
	cpwgr("<0, 0x19>", (uint32_t) (val >> 32));
}

/* software counter */
static uint64_t csky_pmu_read_softc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x1b>");
		lo  = cprgr("<0, 0x1a>");
		hi  = cprgr("<0, 0x1b>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_softc(uint64_t val)
{
	cpwgr("<0, 0x1a>", (uint32_t)  val);
	cpwgr("<0, 0x1b>", (uint32_t) (val >> 32));
}

/* conditional branch mispredict counter */
static uint64_t csky_pmu_read_cbmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x1d>");
		lo  = cprgr("<0, 0x1c>");
		hi  = cprgr("<0, 0x1d>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_cbmc(uint64_t val)
{
	cpwgr("<0, 0x1c>", (uint32_t)  val);
	cpwgr("<0, 0x1d>", (uint32_t) (val >> 32));
}

/* conditional branch instruction counter */
static uint64_t csky_pmu_read_cbic(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x1f>");
		lo  = cprgr("<0, 0x1e>");
		hi  = cprgr("<0, 0x1f>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_cbic(uint64_t val)
{
	cpwgr("<0, 0x1e>", (uint32_t)  val);
	cpwgr("<0, 0x1f>", (uint32_t) (val >> 32));
}

/* indirect branch mispredict counter */
static uint64_t csky_pmu_read_ibmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x21>");
		lo  = cprgr("<0, 0x20>");
		hi  = cprgr("<0, 0x21>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_ibmc(uint64_t val)
{
	cpwgr("<0, 0x20>", (uint32_t)  val);
	cpwgr("<0, 0x21>", (uint32_t) (val >> 32));
}

/* indirect branch instruction counter */
static uint64_t csky_pmu_read_ibic(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x23>");
		lo  = cprgr("<0, 0x22>");
		hi  = cprgr("<0, 0x23>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_ibic(uint64_t val)
{
	cpwgr("<0, 0x22>", (uint32_t)  val);
	cpwgr("<0, 0x23>", (uint32_t) (val >> 32));
}

/* LSU spec fail counter */
static uint64_t csky_pmu_read_lsfc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x25>");
		lo  = cprgr("<0, 0x24>");
		hi  = cprgr("<0, 0x25>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_lsfc(uint64_t val)
{
	cpwgr("<0, 0x24>", (uint32_t)  val);
	cpwgr("<0, 0x25>", (uint32_t) (val >> 32));
}

/* store instruction counter */
static uint64_t csky_pmu_read_sic(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x27>");
		lo  = cprgr("<0, 0x26>");
		hi  = cprgr("<0, 0x27>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_sic(uint64_t val)
{
	cpwgr("<0, 0x26>", (uint32_t)  val);
	cpwgr("<0, 0x27>", (uint32_t) (val >> 32));
}

/* dcache read access counter */
static uint64_t csky_pmu_read_dcrac(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x29>");
		lo  = cprgr("<0, 0x28>");
		hi  = cprgr("<0, 0x29>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_dcrac(uint64_t val)
{
	cpwgr("<0, 0x28>", (uint32_t)  val);
	cpwgr("<0, 0x29>", (uint32_t) (val >> 32));
}

/* dcache read miss counter */
static uint64_t csky_pmu_read_dcrmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x2b>");
		lo  = cprgr("<0, 0x2a>");
		hi  = cprgr("<0, 0x2b>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_dcrmc(uint64_t val)
{
	cpwgr("<0, 0x2a>", (uint32_t)  val);
	cpwgr("<0, 0x2b>", (uint32_t) (val >> 32));
}

/* dcache write access counter */
static uint64_t csky_pmu_read_dcwac(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x2d>");
		lo  = cprgr("<0, 0x2c>");
		hi  = cprgr("<0, 0x2d>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_dcwac(uint64_t val)
{
	cpwgr("<0, 0x2c>", (uint32_t)  val);
	cpwgr("<0, 0x2d>", (uint32_t) (val >> 32));
}

/* dcache write miss counter */
static uint64_t csky_pmu_read_dcwmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x2f>");
		lo  = cprgr("<0, 0x2e>");
		hi  = cprgr("<0, 0x2f>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_dcwmc(uint64_t val)
{
	cpwgr("<0, 0x2e>", (uint32_t)  val);
	cpwgr("<0, 0x2f>", (uint32_t) (val >> 32));
}

/* l2cache read access counter */
static uint64_t csky_pmu_read_l2rac(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x31>");
		lo  = cprgr("<0, 0x30>");
		hi  = cprgr("<0, 0x31>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_l2rac(uint64_t val)
{
	cpwgr("<0, 0x30>", (uint32_t)  val);
	cpwgr("<0, 0x31>", (uint32_t) (val >> 32));
}

/* l2cache read miss counter */
static uint64_t csky_pmu_read_l2rmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x33>");
		lo  = cprgr("<0, 0x32>");
		hi  = cprgr("<0, 0x33>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_l2rmc(uint64_t val)
{
	cpwgr("<0, 0x32>", (uint32_t)  val);
	cpwgr("<0, 0x33>", (uint32_t) (val >> 32));
}

/* l2cache write access counter */
static uint64_t csky_pmu_read_l2wac(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x35>");
		lo  = cprgr("<0, 0x34>");
		hi  = cprgr("<0, 0x35>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_l2wac(uint64_t val)
{
	cpwgr("<0, 0x34>", (uint32_t)  val);
	cpwgr("<0, 0x35>", (uint32_t) (val >> 32));
}

/* l2cache write miss counter */
static uint64_t csky_pmu_read_l2wmc(void)
{
	uint32_t lo, hi, tmp;
	uint64_t result;

	do {
		tmp = cprgr("<0, 0x37>");
		lo  = cprgr("<0, 0x36>");
		hi  = cprgr("<0, 0x37>");
	} while (hi != tmp);

	result = (uint64_t) (hi) << 32;
	result |= lo;

	return result;
}

static void csky_pmu_write_l2wmc(uint64_t val)
{
	cpwgr("<0, 0x36>", (uint32_t)  val);
	cpwgr("<0, 0x37>", (uint32_t) (val >> 32));
}

#define HW_OP_UNSUPPORTED	0xffff
static const int csky_pmu_hw_map[PERF_COUNT_HW_MAX] = {
	[PERF_COUNT_HW_CPU_CYCLES]		= 0x1,
	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x2,
	[PERF_COUNT_HW_CACHE_REFERENCES]	= HW_OP_UNSUPPORTED,
	[PERF_COUNT_HW_CACHE_MISSES]		= HW_OP_UNSUPPORTED,
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0xf,
	[PERF_COUNT_HW_BRANCH_MISSES]		= 0xe,
	[PERF_COUNT_HW_BUS_CYCLES]		= HW_OP_UNSUPPORTED,
	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= HW_OP_UNSUPPORTED,
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= HW_OP_UNSUPPORTED,
	[PERF_COUNT_HW_REF_CPU_CYCLES]		= HW_OP_UNSUPPORTED,
};

#define C(_x)			PERF_COUNT_HW_CACHE_##_x
#define CACHE_OP_UNSUPPORTED	0xffff
static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	[C(L1D)] = {
#ifdef CONFIG_CPU_CK810
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= 0x5,
			[C(RESULT_MISS)]	= 0x6,
		},
#else
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= 0x14,
			[C(RESULT_MISS)]	= 0x15,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= 0x16,
			[C(RESULT_MISS)]	= 0x17,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
#endif
	},
	[C(L1I)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= 0x3,
			[C(RESULT_MISS)]	= 0x4,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(LL)] = {
#ifdef CONFIG_CPU_CK810
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= 0x7,
			[C(RESULT_MISS)]	= 0x8,
		},
#else
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= 0x18,
			[C(RESULT_MISS)]	= 0x19,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= 0x1a,
			[C(RESULT_MISS)]	= 0x1b,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
#endif
	},
	[C(DTLB)] = {
#ifdef CONFIG_CPU_CK810
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
#else
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= 0x14,
			[C(RESULT_MISS)]	= 0xb,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= 0x16,
			[C(RESULT_MISS)]	= 0xb,
		},
#endif
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(ITLB)] = {
#ifdef CONFIG_CPU_CK810
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
#else
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= 0x3,
			[C(RESULT_MISS)]	= 0xa,
		},
#endif
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(BPU)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(NODE)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
};

int  csky_pmu_event_set_period(struct perf_event *event)
{
	struct hw_perf_event *hwc = &event->hw;
	s64 left = local64_read(&hwc->period_left);
	s64 period = hwc->sample_period;
	int ret = 0;

	if (unlikely(left <= -period)) {
		left = period;
		local64_set(&hwc->period_left, left);
		hwc->last_period = period;
		ret = 1;
	}

	if (unlikely(left <= 0)) {
		left += period;
		local64_set(&hwc->period_left, left);
		hwc->last_period = period;
		ret = 1;
	}

	if (left > (s64)csky_pmu.max_period)
		left = csky_pmu.max_period;

	/*
	 * The hw event starts counting from this event offset,
	 * mark it to be able to extract future "deltas":
	 */
	local64_set(&hwc->prev_count, (u64)(-left));

	if (hw_raw_write_mapping[hwc->idx] != NULL)
		hw_raw_write_mapping[hwc->idx]((u64)(-left) &
						csky_pmu.max_period);

	cpwcr(HPOFSR, ~BIT(hwc->idx) & cprcr(HPOFSR));

	perf_event_update_userpage(event);

	return ret;
}

static void csky_perf_event_update(struct perf_event *event,
				   struct hw_perf_event *hwc)
{
	uint64_t prev_raw_count = local64_read(&hwc->prev_count);
	/*
	 * Sign extend count value to 64bit, otherwise delta calculation
	 * would be incorrect when overflow occurs.
	 */
	uint64_t new_raw_count = sign_extend64(
		hw_raw_read_mapping[hwc->idx](), csky_pmu.count_width - 1);
	int64_t delta = new_raw_count - prev_raw_count;

	/*
	 * We aren't afraid of hwc->prev_count changing beneath our feet
	 * because there's no way for us to re-enter this function anytime.
	 */
	local64_set(&hwc->prev_count, new_raw_count);
	local64_add(delta, &event->count);
	local64_sub(delta, &hwc->period_left);
}

static void csky_pmu_reset(void *info)
{
	cpwcr(HPCR, BIT(31) | BIT(30) | BIT(1));
}

static void csky_pmu_read(struct perf_event *event)
{
	csky_perf_event_update(event, &event->hw);
}

static int csky_pmu_cache_event(u64 config)
{
	unsigned int cache_type, cache_op, cache_result;

	cache_type	= (config >>  0) & 0xff;
	cache_op	= (config >>  8) & 0xff;
	cache_result	= (config >> 16) & 0xff;

	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
		return -EINVAL;
	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
		return -EINVAL;
	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
		return -EINVAL;

	return csky_pmu_cache_map[cache_type][cache_op][cache_result];
}

static int csky_pmu_event_init(struct perf_event *event)
{
	struct hw_perf_event *hwc = &event->hw;
	int ret;

	switch (event->attr.type) {
	case PERF_TYPE_HARDWARE:
		if (event->attr.config >= PERF_COUNT_HW_MAX)
			return -ENOENT;
		ret = csky_pmu_hw_map[event->attr.config];
		if (ret == HW_OP_UNSUPPORTED)
			return -ENOENT;
		hwc->idx = ret;
		break;
	case PERF_TYPE_HW_CACHE:
		ret = csky_pmu_cache_event(event->attr.config);
		if (ret == CACHE_OP_UNSUPPORTED)
			return -ENOENT;
		hwc->idx = ret;
		break;
	case PERF_TYPE_RAW:
		if (hw_raw_read_mapping[event->attr.config] == NULL)
			return -ENOENT;
		hwc->idx = event->attr.config;
		break;
	default:
		return -ENOENT;
	}

	if (event->attr.exclude_user)
		csky_pmu.hpcr = BIT(2);
	else if (event->attr.exclude_kernel)
		csky_pmu.hpcr = BIT(3);
	else
		csky_pmu.hpcr = BIT(2) | BIT(3);

	csky_pmu.hpcr |= BIT(1) | BIT(0);

	return 0;
}

/* starts all counters */
static void csky_pmu_enable(struct pmu *pmu)
{
	cpwcr(HPCR, csky_pmu.hpcr);
}

/* stops all counters */
static void csky_pmu_disable(struct pmu *pmu)
{
	cpwcr(HPCR, BIT(1));
}

static void csky_pmu_start(struct perf_event *event, int flags)
{
	unsigned long flg;
	struct hw_perf_event *hwc = &event->hw;
	int idx = hwc->idx;

	if (WARN_ON_ONCE(idx == -1))
		return;

	if (flags & PERF_EF_RELOAD)
		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));

	hwc->state = 0;

	csky_pmu_event_set_period(event);

	local_irq_save(flg);

	cpwcr(HPINTENR, BIT(idx) | cprcr(HPINTENR));
	cpwcr(HPCNTENR, BIT(idx) | cprcr(HPCNTENR));

	local_irq_restore(flg);
}

static void csky_pmu_stop_event(struct perf_event *event)
{
	unsigned long flg;
	struct hw_perf_event *hwc = &event->hw;
	int idx = hwc->idx;

	local_irq_save(flg);

	cpwcr(HPINTENR, ~BIT(idx) & cprcr(HPINTENR));
	cpwcr(HPCNTENR, ~BIT(idx) & cprcr(HPCNTENR));

	local_irq_restore(flg);
}

static void csky_pmu_stop(struct perf_event *event, int flags)
{
	if (!(event->hw.state & PERF_HES_STOPPED)) {
		csky_pmu_stop_event(event);
		event->hw.state |= PERF_HES_STOPPED;
	}

	if ((flags & PERF_EF_UPDATE) &&
	    !(event->hw.state & PERF_HES_UPTODATE)) {
		csky_perf_event_update(event, &event->hw);
		event->hw.state |= PERF_HES_UPTODATE;
	}
}

static void csky_pmu_del(struct perf_event *event, int flags)
{
	struct pmu_hw_events *hw_events = this_cpu_ptr(csky_pmu.hw_events);
	struct hw_perf_event *hwc = &event->hw;

	csky_pmu_stop(event, PERF_EF_UPDATE);

	hw_events->events[hwc->idx] = NULL;

	perf_event_update_userpage(event);
}

/* allocate hardware counter and optionally start counting */
static int csky_pmu_add(struct perf_event *event, int flags)
{
	struct pmu_hw_events *hw_events = this_cpu_ptr(csky_pmu.hw_events);
	struct hw_perf_event *hwc = &event->hw;

	hw_events->events[hwc->idx] = event;

	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;

	if (flags & PERF_EF_START)
		csky_pmu_start(event, PERF_EF_RELOAD);

	perf_event_update_userpage(event);

	return 0;
}

static irqreturn_t csky_pmu_handle_irq(int irq_num, void *dev)
{
	struct perf_sample_data data;
	struct pmu_hw_events *cpuc = this_cpu_ptr(csky_pmu.hw_events);
	struct pt_regs *regs;
	int idx;

	/*
	 * Did an overflow occur?
	 */
	if (!cprcr(HPOFSR))
		return IRQ_NONE;

	/*
	 * Handle the counter(s) overflow(s)
	 */
	regs = get_irq_regs();

	csky_pmu_disable(&csky_pmu.pmu);

	for (idx = 0; idx < CSKY_PMU_MAX_EVENTS; ++idx) {
		struct perf_event *event = cpuc->events[idx];
		struct hw_perf_event *hwc;

		/* Ignore if we don't have an event. */
		if (!event)
			continue;
		/*
		 * We have a single interrupt for all counters. Check that
		 * each counter has overflowed before we process it.
		 */
		if (!(cprcr(HPOFSR) & BIT(idx)))
			continue;

		hwc = &event->hw;
		csky_perf_event_update(event, &event->hw);
		perf_sample_data_init(&data, 0, hwc->last_period);
		csky_pmu_event_set_period(event);

		if (perf_event_overflow(event, &data, regs))
			csky_pmu_stop_event(event);
	}

	csky_pmu_enable(&csky_pmu.pmu);

	/*
	 * Handle the pending perf events.
	 *
	 * Note: this call *must* be run with interrupts disabled. For
	 * platforms that can have the PMU interrupts raised as an NMI, this
	 * will not work.
	 */
	irq_work_run();

	return IRQ_HANDLED;
}

static int csky_pmu_request_irq(irq_handler_t handler)
{
	int err, irqs;
	struct platform_device *pmu_device = csky_pmu.plat_device;

	if (!pmu_device)
		return -ENODEV;

	irqs = min(pmu_device->num_resources, num_possible_cpus());
	if (irqs < 1) {
		pr_err("no irqs for PMUs defined\n");
		return -ENODEV;
	}

	csky_pmu_irq = platform_get_irq(pmu_device, 0);
	if (csky_pmu_irq < 0)
		return -ENODEV;
	err = request_percpu_irq(csky_pmu_irq, handler, "csky-pmu",
				 this_cpu_ptr(csky_pmu.hw_events));
	if (err) {
		pr_err("unable to request IRQ%d for CSKY PMU counters\n",
		       csky_pmu_irq);
		return err;
	}

	return 0;
}

static void csky_pmu_free_irq(void)
{
	int irq;
	struct platform_device *pmu_device = csky_pmu.plat_device;

	irq = platform_get_irq(pmu_device, 0);
	if (irq >= 0)
		free_percpu_irq(irq, this_cpu_ptr(csky_pmu.hw_events));
}

int init_hw_perf_events(void)
{
	csky_pmu.hw_events = alloc_percpu_gfp(struct pmu_hw_events,
					      GFP_KERNEL);
	if (!csky_pmu.hw_events) {
		pr_info("failed to allocate per-cpu PMU data.\n");
		return -ENOMEM;
	}

	csky_pmu.pmu = (struct pmu) {
		.pmu_enable	= csky_pmu_enable,
		.pmu_disable	= csky_pmu_disable,
		.event_init	= csky_pmu_event_init,
		.add		= csky_pmu_add,
		.del		= csky_pmu_del,
		.start		= csky_pmu_start,
		.stop		= csky_pmu_stop,
		.read		= csky_pmu_read,
	};

	memset((void *)hw_raw_read_mapping, 0,
		sizeof(hw_raw_read_mapping[CSKY_PMU_MAX_EVENTS]));

	hw_raw_read_mapping[0x1]  = csky_pmu_read_cc;
	hw_raw_read_mapping[0x2]  = csky_pmu_read_ic;
	hw_raw_read_mapping[0x3]  = csky_pmu_read_icac;
	hw_raw_read_mapping[0x4]  = csky_pmu_read_icmc;
	hw_raw_read_mapping[0x5]  = csky_pmu_read_dcac;
	hw_raw_read_mapping[0x6]  = csky_pmu_read_dcmc;
	hw_raw_read_mapping[0x7]  = csky_pmu_read_l2ac;
	hw_raw_read_mapping[0x8]  = csky_pmu_read_l2mc;
	hw_raw_read_mapping[0xa]  = csky_pmu_read_iutlbmc;
	hw_raw_read_mapping[0xb]  = csky_pmu_read_dutlbmc;
	hw_raw_read_mapping[0xc]  = csky_pmu_read_jtlbmc;
	hw_raw_read_mapping[0xd]  = csky_pmu_read_softc;
	hw_raw_read_mapping[0xe]  = csky_pmu_read_cbmc;
	hw_raw_read_mapping[0xf]  = csky_pmu_read_cbic;
	hw_raw_read_mapping[0x10] = csky_pmu_read_ibmc;
	hw_raw_read_mapping[0x11] = csky_pmu_read_ibic;
	hw_raw_read_mapping[0x12] = csky_pmu_read_lsfc;
	hw_raw_read_mapping[0x13] = csky_pmu_read_sic;
	hw_raw_read_mapping[0x14] = csky_pmu_read_dcrac;
	hw_raw_read_mapping[0x15] = csky_pmu_read_dcrmc;
	hw_raw_read_mapping[0x16] = csky_pmu_read_dcwac;
	hw_raw_read_mapping[0x17] = csky_pmu_read_dcwmc;
	hw_raw_read_mapping[0x18] = csky_pmu_read_l2rac;
	hw_raw_read_mapping[0x19] = csky_pmu_read_l2rmc;
	hw_raw_read_mapping[0x1a] = csky_pmu_read_l2wac;
	hw_raw_read_mapping[0x1b] = csky_pmu_read_l2wmc;

	memset((void *)hw_raw_write_mapping, 0,
		sizeof(hw_raw_write_mapping[CSKY_PMU_MAX_EVENTS]));

	hw_raw_write_mapping[0x1]  = csky_pmu_write_cc;
	hw_raw_write_mapping[0x2]  = csky_pmu_write_ic;
	hw_raw_write_mapping[0x3]  = csky_pmu_write_icac;
	hw_raw_write_mapping[0x4]  = csky_pmu_write_icmc;
	hw_raw_write_mapping[0x5]  = csky_pmu_write_dcac;
	hw_raw_write_mapping[0x6]  = csky_pmu_write_dcmc;
	hw_raw_write_mapping[0x7]  = csky_pmu_write_l2ac;
	hw_raw_write_mapping[0x8]  = csky_pmu_write_l2mc;
	hw_raw_write_mapping[0xa]  = csky_pmu_write_iutlbmc;
	hw_raw_write_mapping[0xb]  = csky_pmu_write_dutlbmc;
	hw_raw_write_mapping[0xc]  = csky_pmu_write_jtlbmc;
	hw_raw_write_mapping[0xd]  = csky_pmu_write_softc;
	hw_raw_write_mapping[0xe]  = csky_pmu_write_cbmc;
	hw_raw_write_mapping[0xf]  = csky_pmu_write_cbic;
	hw_raw_write_mapping[0x10] = csky_pmu_write_ibmc;
	hw_raw_write_mapping[0x11] = csky_pmu_write_ibic;
	hw_raw_write_mapping[0x12] = csky_pmu_write_lsfc;
	hw_raw_write_mapping[0x13] = csky_pmu_write_sic;
	hw_raw_write_mapping[0x14] = csky_pmu_write_dcrac;
	hw_raw_write_mapping[0x15] = csky_pmu_write_dcrmc;
	hw_raw_write_mapping[0x16] = csky_pmu_write_dcwac;
	hw_raw_write_mapping[0x17] = csky_pmu_write_dcwmc;
	hw_raw_write_mapping[0x18] = csky_pmu_write_l2rac;
	hw_raw_write_mapping[0x19] = csky_pmu_write_l2rmc;
	hw_raw_write_mapping[0x1a] = csky_pmu_write_l2wac;
	hw_raw_write_mapping[0x1b] = csky_pmu_write_l2wmc;

	return 0;
}

static int csky_pmu_starting_cpu(unsigned int cpu)
{
	enable_percpu_irq(csky_pmu_irq, 0);
	return 0;
}

static int csky_pmu_dying_cpu(unsigned int cpu)
{
	disable_percpu_irq(csky_pmu_irq);
	return 0;
}

int csky_pmu_device_probe(struct platform_device *pdev,
			  const struct of_device_id *of_table)
{
	struct device_node *node = pdev->dev.of_node;
	int ret;

	ret = init_hw_perf_events();
	if (ret) {
		pr_notice("[perf] failed to probe PMU!\n");
		return ret;
	}

	if (of_property_read_u32(node, "count-width",
				 &csky_pmu.count_width)) {
		csky_pmu.count_width = DEFAULT_COUNT_WIDTH;
	}
	csky_pmu.max_period = BIT_ULL(csky_pmu.count_width) - 1;

	csky_pmu.plat_device = pdev;

	/* Ensure the PMU has sane values out of reset. */
	on_each_cpu(csky_pmu_reset, &csky_pmu, 1);

	ret = csky_pmu_request_irq(csky_pmu_handle_irq);
	if (ret) {
		csky_pmu.pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
		pr_notice("[perf] PMU request irq fail!\n");
	}

	ret = cpuhp_setup_state(CPUHP_AP_PERF_CSKY_ONLINE, "AP_PERF_ONLINE",
				csky_pmu_starting_cpu,
				csky_pmu_dying_cpu);
	if (ret) {
		csky_pmu_free_irq();
		free_percpu(csky_pmu.hw_events);
		return ret;
	}

	ret = perf_pmu_register(&csky_pmu.pmu, "cpu", PERF_TYPE_RAW);
	if (ret) {
		csky_pmu_free_irq();
		free_percpu(csky_pmu.hw_events);
	}

	return ret;
}

static const struct of_device_id csky_pmu_of_device_ids[] = {
	{.compatible = "csky,csky-pmu"},
	{},
};

static int csky_pmu_dev_probe(struct platform_device *pdev)
{
	return csky_pmu_device_probe(pdev, csky_pmu_of_device_ids);
}

static struct platform_driver csky_pmu_driver = {
	.driver = {
		   .name = "csky-pmu",
		   .of_match_table = csky_pmu_of_device_ids,
		   },
	.probe = csky_pmu_dev_probe,
};

static int __init csky_pmu_probe(void)
{
	int ret;

	ret = platform_driver_register(&csky_pmu_driver);
	if (ret)
		pr_notice("[perf] PMU initialization failed\n");
	else
		pr_notice("[perf] PMU initialization done\n");

	return ret;
}

device_initcall(csky_pmu_probe);