summaryrefslogtreecommitdiff
path: root/arch/mips/Kconfig
blob: ada18f3be2298f2141c100bbd36dd4f6a4c94d1f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
# SPDX-License-Identifier: GPL-2.0
config MIPS
	bool
	default y
	select ARCH_32BIT_OFF_T if !64BIT
	select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
	select ARCH_HAS_CPU_FINALIZE_INIT
	select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
	select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
	select ARCH_HAS_FORTIFY_SOURCE
	select ARCH_HAS_KCOV
	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
	select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
	select ARCH_HAS_STRNCPY_FROM_USER
	select ARCH_HAS_STRNLEN_USER
	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
	select ARCH_HAS_UBSAN_SANITIZE_ALL
	select ARCH_HAS_GCOV_PROFILE_ALL
	select ARCH_KEEP_MEMBLOCK
	select ARCH_USE_BUILTIN_BSWAP
	select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
	select ARCH_USE_MEMTEST
	select ARCH_USE_QUEUED_RWLOCKS
	select ARCH_USE_QUEUED_SPINLOCKS
	select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
	select ARCH_WANT_IPC_PARSE_VERSION
	select ARCH_WANT_LD_ORPHAN_WARN
	select BUILDTIME_TABLE_SORT
	select CLONE_BACKWARDS
	select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
	select CPU_PM if CPU_IDLE
	select GENERIC_ATOMIC64 if !64BIT
	select GENERIC_CMOS_UPDATE
	select GENERIC_CPU_AUTOPROBE
	select GENERIC_GETTIMEOFDAY
	select GENERIC_IOMAP
	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
	select GENERIC_ISA_DMA if EISA
	select GENERIC_LIB_ASHLDI3
	select GENERIC_LIB_ASHRDI3
	select GENERIC_LIB_CMPDI2
	select GENERIC_LIB_LSHRDI3
	select GENERIC_LIB_UCMPDI2
	select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
	select GENERIC_SMP_IDLE_THREAD
	select GENERIC_TIME_VSYSCALL
	select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
	select HAS_IOPORT if !NO_IOPORT_MAP || ISA
	select HAVE_ARCH_COMPILER_H
	select HAVE_ARCH_JUMP_LABEL
	select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
	select HAVE_ARCH_MMAP_RND_BITS if MMU
	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
	select HAVE_ARCH_SECCOMP_FILTER
	select HAVE_ARCH_TRACEHOOK
	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
	select HAVE_ASM_MODVERSIONS
	select HAVE_CONTEXT_TRACKING_USER
	select HAVE_TIF_NOHZ
	select HAVE_C_RECORDMCOUNT
	select HAVE_DEBUG_KMEMLEAK
	select HAVE_DEBUG_STACKOVERFLOW
	select HAVE_DMA_CONTIGUOUS
	select HAVE_DYNAMIC_FTRACE
	select HAVE_EBPF_JIT if !CPU_MICROMIPS
	select HAVE_EXIT_THREAD
	select HAVE_FAST_GUP
	select HAVE_FTRACE_MCOUNT_RECORD
	select HAVE_FUNCTION_GRAPH_TRACER
	select HAVE_FUNCTION_TRACER
	select HAVE_GCC_PLUGINS
	select HAVE_GENERIC_VDSO
	select HAVE_IOREMAP_PROT
	select HAVE_IRQ_EXIT_ON_IRQ_STACK
	select HAVE_IRQ_TIME_ACCOUNTING
	select HAVE_KPROBES
	select HAVE_KRETPROBES
	select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
	select HAVE_MOD_ARCH_SPECIFIC
	select HAVE_NMI
	select HAVE_PATA_PLATFORM
	select HAVE_PERF_EVENTS
	select HAVE_PERF_REGS
	select HAVE_PERF_USER_STACK_DUMP
	select HAVE_REGS_AND_STACK_ACCESS_API
	select HAVE_RSEQ
	select HAVE_SPARSE_SYSCALL_NR
	select HAVE_STACKPROTECTOR
	select HAVE_SYSCALL_TRACEPOINTS
	select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
	select IRQ_FORCED_THREADING
	select ISA if EISA
	select MODULES_USE_ELF_REL if MODULES
	select MODULES_USE_ELF_RELA if MODULES && 64BIT
	select PERF_USE_VMALLOC
	select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
	select RTC_LIB
	select SYSCTL_EXCEPTION_TRACE
	select TRACE_IRQFLAGS_SUPPORT
	select ARCH_HAS_ELFCORE_COMPAT
	select HAVE_ARCH_KCSAN if 64BIT

config MIPS_FIXUP_BIGPHYS_ADDR
	bool

config MIPS_GENERIC
	bool

config MACH_INGENIC
	bool
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_ZBOOT
	select DMA_NONCOHERENT
	select IRQ_MIPS_CPU
	select PINCTRL
	select GPIOLIB
	select COMMON_CLK
	select GENERIC_IRQ_CHIP
	select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
	select USE_OF
	select CPU_SUPPORTS_CPUFREQ
	select MIPS_EXTERNAL_TIMER

menu "Machine selection"

choice
	prompt "System type"
	default MIPS_GENERIC_KERNEL

config MIPS_GENERIC_KERNEL
	bool "Generic board-agnostic MIPS kernel"
	select MIPS_GENERIC
	select BOOT_RAW
	select BUILTIN_DTB
	select CEVT_R4K
	select CLKSRC_MIPS_GIC
	select COMMON_CLK
	select CPU_MIPSR2_IRQ_EI
	select CPU_MIPSR2_IRQ_VI
	select CSRC_R4K
	select DMA_NONCOHERENT
	select HAVE_PCI
	select IRQ_MIPS_CPU
	select MIPS_AUTO_PFN_OFFSET
	select MIPS_CPU_SCACHE
	select MIPS_GIC
	select MIPS_L1_CACHE_SHIFT_7
	select NO_EXCEPT_FILL
	select PCI_DRIVERS_GENERIC
	select SMP_UP if SMP
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_MIPS32_R1
	select SYS_HAS_CPU_MIPS32_R2
	select SYS_HAS_CPU_MIPS32_R6
	select SYS_HAS_CPU_MIPS64_R1
	select SYS_HAS_CPU_MIPS64_R2
	select SYS_HAS_CPU_MIPS64_R6
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_HIGHMEM
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_MICROMIPS
	select SYS_SUPPORTS_MIPS16
	select SYS_SUPPORTS_MIPS_CPS
	select SYS_SUPPORTS_MULTITHREADING
	select SYS_SUPPORTS_RELOCATABLE
	select SYS_SUPPORTS_SMARTMIPS
	select SYS_SUPPORTS_ZBOOT
	select UHI_BOOT
	select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
	select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
	select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
	select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
	select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
	select USE_OF
	help
	  Select this to build a kernel which aims to support multiple boards,
	  generally using a flattened device tree passed from the bootloader
	  using the boot protocol defined in the UHI (Unified Hosting
	  Interface) specification.

config MIPS_ALCHEMY
	bool "Alchemy processor based machines"
	select PHYS_ADDR_T_64BIT
	select CEVT_R4K
	select CSRC_R4K
	select IRQ_MIPS_CPU
	select DMA_NONCOHERENT		# Au1000,1500,1100 aren't, rest is
	select MIPS_FIXUP_BIGPHYS_ADDR if PCI
	select SYS_HAS_CPU_MIPS32_R1
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_APM_EMULATION
	select GPIOLIB
	select SYS_SUPPORTS_ZBOOT
	select COMMON_CLK

config AR7
	bool "Texas Instruments AR7"
	select BOOT_ELF32
	select COMMON_CLK
	select DMA_NONCOHERENT
	select CEVT_R4K
	select CSRC_R4K
	select IRQ_MIPS_CPU
	select NO_EXCEPT_FILL
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_MIPS32_R1
	select SYS_HAS_EARLY_PRINTK
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_MIPS16
	select SYS_SUPPORTS_ZBOOT_UART16550
	select GPIOLIB
	select VLYNQ
	help
	  Support for the Texas Instruments AR7 System-on-a-Chip
	  family: TNETD7100, 7200 and 7300.

config ATH25
	bool "Atheros AR231x/AR531x SoC support"
	select CEVT_R4K
	select CSRC_R4K
	select DMA_NONCOHERENT
	select IRQ_MIPS_CPU
	select IRQ_DOMAIN
	select SYS_HAS_CPU_MIPS32_R1
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_HAS_EARLY_PRINTK
	help
	  Support for Atheros AR231x and Atheros AR531x based boards

config ATH79
	bool "Atheros AR71XX/AR724X/AR913X based boards"
	select ARCH_HAS_RESET_CONTROLLER
	select BOOT_RAW
	select CEVT_R4K
	select CSRC_R4K
	select DMA_NONCOHERENT
	select GPIOLIB
	select PINCTRL
	select COMMON_CLK
	select IRQ_MIPS_CPU
	select SYS_HAS_CPU_MIPS32_R2
	select SYS_HAS_EARLY_PRINTK
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_MIPS16
	select SYS_SUPPORTS_ZBOOT_UART_PROM
	select USE_OF
	select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
	help
	  Support for the Atheros AR71XX/AR724X/AR913X SoCs.

config BMIPS_GENERIC
	bool "Broadcom Generic BMIPS kernel"
	select ARCH_HAS_RESET_CONTROLLER
	select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
	select BOOT_RAW
	select NO_EXCEPT_FILL
	select USE_OF
	select CEVT_R4K
	select CSRC_R4K
	select SYNC_R4K
	select COMMON_CLK
	select BCM6345_L1_IRQ
	select BCM7038_L1_IRQ
	select BCM7120_L2_IRQ
	select BRCMSTB_L2_IRQ
	select IRQ_MIPS_CPU
	select DMA_NONCOHERENT
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_HIGHMEM
	select SYS_HAS_CPU_BMIPS32_3300
	select SYS_HAS_CPU_BMIPS4350
	select SYS_HAS_CPU_BMIPS4380
	select SYS_HAS_CPU_BMIPS5000
	select SWAP_IO_SPACE
	select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
	select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
	select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
	select HARDIRQS_SW_RESEND
	select HAVE_PCI
	select PCI_DRIVERS_GENERIC
	select FW_CFE
	help
	  Build a generic DT-based kernel image that boots on select
	  BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
	  box chips.  Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
	  must be set appropriately for your board.

config BCM47XX
	bool "Broadcom BCM47XX based boards"
	select BOOT_RAW
	select CEVT_R4K
	select CSRC_R4K
	select DMA_NONCOHERENT
	select HAVE_PCI
	select IRQ_MIPS_CPU
	select SYS_HAS_CPU_MIPS32_R1
	select NO_EXCEPT_FILL
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_MIPS16
	select SYS_SUPPORTS_ZBOOT
	select SYS_HAS_EARLY_PRINTK
	select USE_GENERIC_EARLY_PRINTK_8250
	select GPIOLIB
	select LEDS_GPIO_REGISTER
	select BCM47XX_NVRAM
	select BCM47XX_SPROM
	select BCM47XX_SSB if !BCM47XX_BCMA
	help
	  Support for BCM47XX based boards

config BCM63XX
	bool "Broadcom BCM63XX based boards"
	select BOOT_RAW
	select CEVT_R4K
	select CSRC_R4K
	select SYNC_R4K
	select DMA_NONCOHERENT
	select IRQ_MIPS_CPU
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_HAS_EARLY_PRINTK
	select SYS_HAS_CPU_BMIPS32_3300
	select SYS_HAS_CPU_BMIPS4350
	select SYS_HAS_CPU_BMIPS4380
	select SWAP_IO_SPACE
	select GPIOLIB
	select MIPS_L1_CACHE_SHIFT_4
	select HAVE_LEGACY_CLK
	help
	  Support for BCM63XX based boards

config MIPS_COBALT
	bool "Cobalt Server"
	select CEVT_R4K
	select CSRC_R4K
	select CEVT_GT641XX
	select DMA_NONCOHERENT
	select FORCE_PCI
	select I8253
	select I8259
	select IRQ_MIPS_CPU
	select IRQ_GT641XX
	select PCI_GT64XXX_PCI0
	select SYS_HAS_CPU_NEVADA
	select SYS_HAS_EARLY_PRINTK
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select USE_GENERIC_EARLY_PRINTK_8250

config MACH_DECSTATION
	bool "DECstations"
	select BOOT_ELF32
	select CEVT_DS1287
	select CEVT_R4K if CPU_R4X00
	select CSRC_IOASIC
	select CSRC_R4K if CPU_R4X00
	select CPU_DADDI_WORKAROUNDS if 64BIT
	select CPU_R4000_WORKAROUNDS if 64BIT
	select CPU_R4400_WORKAROUNDS if 64BIT
	select DMA_NONCOHERENT
	select NO_IOPORT_MAP
	select IRQ_MIPS_CPU
	select SYS_HAS_CPU_R3000
	select SYS_HAS_CPU_R4X00
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_128HZ
	select SYS_SUPPORTS_256HZ
	select SYS_SUPPORTS_1024HZ
	select MIPS_L1_CACHE_SHIFT_4
	help
	  This enables support for DEC's MIPS based workstations.  For details
	  see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
	  DECstation porting pages on <http://decstation.unix-ag.org/>.

	  If you have one of the following DECstation Models you definitely
	  want to choose R4xx0 for the CPU Type:

		DECstation 5000/50
		DECstation 5000/150
		DECstation 5000/260
		DECsystem 5900/260

	  otherwise choose R3000.

config MACH_JAZZ
	bool "Jazz family of machines"
	select ARC_MEMORY
	select ARC_PROMLIB
	select ARCH_MIGHT_HAVE_PC_PARPORT
	select ARCH_MIGHT_HAVE_PC_SERIO
	select DMA_OPS
	select FW_ARC
	select FW_ARC32
	select ARCH_MAY_HAVE_PC_FDC
	select CEVT_R4K
	select CSRC_R4K
	select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
	select GENERIC_ISA_DMA
	select HAVE_PCSPKR_PLATFORM
	select IRQ_MIPS_CPU
	select I8253
	select I8259
	select ISA
	select SYS_HAS_CPU_R4X00
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_100HZ
	select SYS_SUPPORTS_LITTLE_ENDIAN
	help
	  This a family of machines based on the MIPS R4030 chipset which was
	  used by several vendors to build RISC/os and Windows NT workstations.
	  Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
	  Olivetti M700-10 workstations.

config MACH_INGENIC_SOC
	bool "Ingenic SoC based machines"
	select MIPS_GENERIC
	select MACH_INGENIC
	select SYS_SUPPORTS_ZBOOT_UART16550
	select CPU_SUPPORTS_CPUFREQ
	select MIPS_EXTERNAL_TIMER

config LANTIQ
	bool "Lantiq based platforms"
	select DMA_NONCOHERENT
	select IRQ_MIPS_CPU
	select CEVT_R4K
	select CSRC_R4K
	select NO_EXCEPT_FILL
	select SYS_HAS_CPU_MIPS32_R1
	select SYS_HAS_CPU_MIPS32_R2
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_MIPS16
	select SYS_SUPPORTS_MULTITHREADING
	select SYS_SUPPORTS_VPE_LOADER
	select SYS_HAS_EARLY_PRINTK
	select GPIOLIB
	select SWAP_IO_SPACE
	select BOOT_RAW
	select HAVE_LEGACY_CLK
	select USE_OF
	select PINCTRL
	select PINCTRL_LANTIQ
	select ARCH_HAS_RESET_CONTROLLER
	select RESET_CONTROLLER

config MACH_LOONGSON32
	bool "Loongson 32-bit family of machines"
	select SYS_SUPPORTS_ZBOOT
	help
	  This enables support for the Loongson-1 family of machines.

	  Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
	  the Institute of Computing Technology (ICT), Chinese Academy of
	  Sciences (CAS).

config MACH_LOONGSON2EF
	bool "Loongson-2E/F family of machines"
	select SYS_SUPPORTS_ZBOOT
	help
	  This enables the support of early Loongson-2E/F family of machines.

config MACH_LOONGSON64
	bool "Loongson 64-bit family of machines"
	select ARCH_SPARSEMEM_ENABLE
	select ARCH_MIGHT_HAVE_PC_PARPORT
	select ARCH_MIGHT_HAVE_PC_SERIO
	select GENERIC_ISA_DMA_SUPPORT_BROKEN
	select BOOT_ELF32
	select BOARD_SCACHE
	select CSRC_R4K
	select CEVT_R4K
	select FORCE_PCI
	select ISA
	select I8259
	select IRQ_MIPS_CPU
	select NO_EXCEPT_FILL
	select NR_CPUS_DEFAULT_64
	select USE_GENERIC_EARLY_PRINTK_8250
	select PCI_DRIVERS_GENERIC
	select SYS_HAS_CPU_LOONGSON64
	select SYS_HAS_EARLY_PRINTK
	select SYS_SUPPORTS_SMP
	select SYS_SUPPORTS_HOTPLUG_CPU
	select SYS_SUPPORTS_NUMA
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_HIGHMEM
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_ZBOOT
	select SYS_SUPPORTS_RELOCATABLE
	select ZONE_DMA32
	select COMMON_CLK
	select USE_OF
	select BUILTIN_DTB
	select PCI_HOST_GENERIC
	select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
	help
	  This enables the support of Loongson-2/3 family of machines.

	  Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
	  GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
	  and Loongson-2F which will be removed), developed by the Institute
	  of Computing Technology (ICT), Chinese Academy of Sciences (CAS).

config MIPS_MALTA
	bool "MIPS Malta board"
	select ARCH_MAY_HAVE_PC_FDC
	select ARCH_MIGHT_HAVE_PC_PARPORT
	select ARCH_MIGHT_HAVE_PC_SERIO
	select BOOT_ELF32
	select BOOT_RAW
	select BUILTIN_DTB
	select CEVT_R4K
	select CLKSRC_MIPS_GIC
	select COMMON_CLK
	select CSRC_R4K
	select DMA_NONCOHERENT
	select GENERIC_ISA_DMA
	select HAVE_PCSPKR_PLATFORM
	select HAVE_PCI
	select I8253
	select I8259
	select IRQ_MIPS_CPU
	select MIPS_BONITO64
	select MIPS_CPU_SCACHE
	select MIPS_GIC
	select MIPS_L1_CACHE_SHIFT_6
	select MIPS_MSC
	select PCI_GT64XXX_PCI0
	select SMP_UP if SMP
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_MIPS32_R1
	select SYS_HAS_CPU_MIPS32_R2
	select SYS_HAS_CPU_MIPS32_R3_5
	select SYS_HAS_CPU_MIPS32_R5
	select SYS_HAS_CPU_MIPS32_R6
	select SYS_HAS_CPU_MIPS64_R1
	select SYS_HAS_CPU_MIPS64_R2
	select SYS_HAS_CPU_MIPS64_R6
	select SYS_HAS_CPU_NEVADA
	select SYS_HAS_CPU_RM7000
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_HIGHMEM
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_MICROMIPS
	select SYS_SUPPORTS_MIPS16
	select SYS_SUPPORTS_MIPS_CPS
	select SYS_SUPPORTS_MULTITHREADING
	select SYS_SUPPORTS_RELOCATABLE
	select SYS_SUPPORTS_SMARTMIPS
	select SYS_SUPPORTS_VPE_LOADER
	select SYS_SUPPORTS_ZBOOT
	select USE_OF
	select WAR_ICACHE_REFILLS
	select ZONE_DMA32 if 64BIT
	help
	  This enables support for the MIPS Technologies Malta evaluation
	  board.

config MACH_PIC32
	bool "Microchip PIC32 Family"
	help
	  This enables support for the Microchip PIC32 family of platforms.

	  Microchip PIC32 is a family of general-purpose 32 bit MIPS core
	  microcontrollers.

config MACH_NINTENDO64
	bool "Nintendo 64 console"
	select CEVT_R4K
	select CSRC_R4K
	select SYS_HAS_CPU_R4300
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_ZBOOT
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select DMA_NONCOHERENT
	select IRQ_MIPS_CPU

config RALINK
	bool "Ralink based machines"
	select CEVT_R4K
	select COMMON_CLK
	select CSRC_R4K
	select BOOT_RAW
	select DMA_NONCOHERENT
	select IRQ_MIPS_CPU
	select USE_OF
	select SYS_HAS_CPU_MIPS32_R2
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_MIPS16
	select SYS_SUPPORTS_ZBOOT
	select SYS_HAS_EARLY_PRINTK
	select ARCH_HAS_RESET_CONTROLLER
	select RESET_CONTROLLER

config MACH_REALTEK_RTL
	bool "Realtek RTL838x/RTL839x based machines"
	select MIPS_GENERIC
	select DMA_NONCOHERENT
	select IRQ_MIPS_CPU
	select CSRC_R4K
	select CEVT_R4K
	select SYS_HAS_CPU_MIPS32_R1
	select SYS_HAS_CPU_MIPS32_R2
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_MIPS16
	select SYS_SUPPORTS_MULTITHREADING
	select SYS_SUPPORTS_VPE_LOADER
	select BOOT_RAW
	select PINCTRL
	select USE_OF

config SGI_IP22
	bool "SGI IP22 (Indy/Indigo2)"
	select ARC_MEMORY
	select ARC_PROMLIB
	select FW_ARC
	select FW_ARC32
	select ARCH_MIGHT_HAVE_PC_SERIO
	select BOOT_ELF32
	select CEVT_R4K
	select CSRC_R4K
	select DEFAULT_SGI_PARTITION
	select DMA_NONCOHERENT
	select HAVE_EISA
	select I8253
	select I8259
	select IP22_CPU_SCACHE
	select IRQ_MIPS_CPU
	select GENERIC_ISA_DMA_SUPPORT_BROKEN
	select SGI_HAS_I8042
	select SGI_HAS_INDYDOG
	select SGI_HAS_HAL2
	select SGI_HAS_SEEQ
	select SGI_HAS_WD93
	select SGI_HAS_ZILOG
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_R4X00
	select SYS_HAS_CPU_R5000
	select SYS_HAS_EARLY_PRINTK
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select WAR_R4600_V1_INDEX_ICACHEOP
	select WAR_R4600_V1_HIT_CACHEOP
	select WAR_R4600_V2_HIT_CACHEOP
	select MIPS_L1_CACHE_SHIFT_7
	help
	  This are the SGI Indy, Challenge S and Indigo2, as well as certain
	  OEM variants like the Tandem CMN B006S. To compile a Linux kernel
	  that runs on these, say Y here.

config SGI_IP27
	bool "SGI IP27 (Origin200/2000)"
	select ARCH_HAS_PHYS_TO_DMA
	select ARCH_SPARSEMEM_ENABLE
	select FW_ARC
	select FW_ARC64
	select ARC_CMDLINE_ONLY
	select BOOT_ELF64
	select DEFAULT_SGI_PARTITION
	select FORCE_PCI
	select SYS_HAS_EARLY_PRINTK
	select HAVE_PCI
	select IRQ_MIPS_CPU
	select IRQ_DOMAIN_HIERARCHY
	select NR_CPUS_DEFAULT_64
	select PCI_DRIVERS_GENERIC
	select PCI_XTALK_BRIDGE
	select SYS_HAS_CPU_R10000
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_NUMA
	select SYS_SUPPORTS_SMP
	select WAR_R10000_LLSC
	select MIPS_L1_CACHE_SHIFT_7
	select NUMA
	select HAVE_ARCH_NODEDATA_EXTENSION
	help
	  This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
	  workstations.  To compile a Linux kernel that runs on these, say Y
	  here.

config SGI_IP28
	bool "SGI IP28 (Indigo2 R10k)"
	select ARC_MEMORY
	select ARC_PROMLIB
	select FW_ARC
	select FW_ARC64
	select ARCH_MIGHT_HAVE_PC_SERIO
	select BOOT_ELF64
	select CEVT_R4K
	select CSRC_R4K
	select DEFAULT_SGI_PARTITION
	select DMA_NONCOHERENT
	select GENERIC_ISA_DMA_SUPPORT_BROKEN
	select IRQ_MIPS_CPU
	select HAVE_EISA
	select I8253
	select I8259
	select SGI_HAS_I8042
	select SGI_HAS_INDYDOG
	select SGI_HAS_HAL2
	select SGI_HAS_SEEQ
	select SGI_HAS_WD93
	select SGI_HAS_ZILOG
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_R10000
	select SYS_HAS_EARLY_PRINTK
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select WAR_R10000_LLSC
	select MIPS_L1_CACHE_SHIFT_7
	help
	  This is the SGI Indigo2 with R10000 processor.  To compile a Linux
	  kernel that runs on these, say Y here.

config SGI_IP30
	bool "SGI IP30 (Octane/Octane2)"
	select ARCH_HAS_PHYS_TO_DMA
	select FW_ARC
	select FW_ARC64
	select BOOT_ELF64
	select CEVT_R4K
	select CSRC_R4K
	select FORCE_PCI
	select SYNC_R4K if SMP
	select ZONE_DMA32
	select HAVE_PCI
	select IRQ_MIPS_CPU
	select IRQ_DOMAIN_HIERARCHY
	select PCI_DRIVERS_GENERIC
	select PCI_XTALK_BRIDGE
	select SYS_HAS_EARLY_PRINTK
	select SYS_HAS_CPU_R10000
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_SMP
	select WAR_R10000_LLSC
	select MIPS_L1_CACHE_SHIFT_7
	select ARC_MEMORY
	help
	  These are the SGI Octane and Octane2 graphics workstations.  To
	  compile a Linux kernel that runs on these, say Y here.

config SGI_IP32
	bool "SGI IP32 (O2)"
	select ARC_MEMORY
	select ARC_PROMLIB
	select ARCH_HAS_PHYS_TO_DMA
	select FW_ARC
	select FW_ARC32
	select BOOT_ELF32
	select CEVT_R4K
	select CSRC_R4K
	select DMA_NONCOHERENT
	select HAVE_PCI
	select IRQ_MIPS_CPU
	select R5000_CPU_SCACHE
	select RM7000_CPU_SCACHE
	select SYS_HAS_CPU_R5000
	select SYS_HAS_CPU_R10000 if BROKEN
	select SYS_HAS_CPU_RM7000
	select SYS_HAS_CPU_NEVADA
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select WAR_ICACHE_REFILLS
	help
	  If you want this kernel to run on SGI O2 workstation, say Y here.

config SIBYTE_CRHONE
	bool "Sibyte BCM91125C-CRhone"
	select BOOT_ELF32
	select SIBYTE_BCM1125
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_SB1
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_HIGHMEM
	select SYS_SUPPORTS_LITTLE_ENDIAN

config SIBYTE_RHONE
	bool "Sibyte BCM91125E-Rhone"
	select BOOT_ELF32
	select SIBYTE_SB1250
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_SB1
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_LITTLE_ENDIAN

config SIBYTE_SWARM
	bool "Sibyte BCM91250A-SWARM"
	select BOOT_ELF32
	select HAVE_PATA_PLATFORM
	select SIBYTE_SB1250
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_SB1
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_HIGHMEM
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select ZONE_DMA32 if 64BIT
	select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI

config SIBYTE_LITTLESUR
	bool "Sibyte BCM91250C2-LittleSur"
	select BOOT_ELF32
	select HAVE_PATA_PLATFORM
	select SIBYTE_SB1250
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_SB1
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_HIGHMEM
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select ZONE_DMA32 if 64BIT

config SIBYTE_SENTOSA
	bool "Sibyte BCM91250E-Sentosa"
	select BOOT_ELF32
	select SIBYTE_SB1250
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_SB1
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI

config SIBYTE_BIGSUR
	bool "Sibyte BCM91480B-BigSur"
	select BOOT_ELF32
	select NR_CPUS_DEFAULT_4
	select SIBYTE_BCM1x80
	select SWAP_IO_SPACE
	select SYS_HAS_CPU_SB1
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_HIGHMEM
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select ZONE_DMA32 if 64BIT
	select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI

config SNI_RM
	bool "SNI RM200/300/400"
	select ARC_MEMORY
	select ARC_PROMLIB
	select FW_ARC if CPU_LITTLE_ENDIAN
	select FW_ARC32 if CPU_LITTLE_ENDIAN
	select FW_SNIPROM if CPU_BIG_ENDIAN
	select ARCH_MAY_HAVE_PC_FDC
	select ARCH_MIGHT_HAVE_PC_PARPORT
	select ARCH_MIGHT_HAVE_PC_SERIO
	select BOOT_ELF32
	select CEVT_R4K
	select CSRC_R4K
	select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
	select DMA_NONCOHERENT
	select GENERIC_ISA_DMA
	select HAVE_EISA
	select HAVE_PCSPKR_PLATFORM
	select HAVE_PCI
	select IRQ_MIPS_CPU
	select I8253
	select I8259
	select ISA
	select MIPS_L1_CACHE_SHIFT_6
	select SWAP_IO_SPACE if CPU_BIG_ENDIAN
	select SYS_HAS_CPU_R4X00
	select SYS_HAS_CPU_R5000
	select SYS_HAS_CPU_R10000
	select R5000_CPU_SCACHE
	select SYS_HAS_EARLY_PRINTK
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_HIGHMEM
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select WAR_R4600_V2_HIT_CACHEOP
	help
	  The SNI RM200/300/400 are MIPS-based machines manufactured by
	  Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
	  Technology and now in turn merged with Fujitsu.  Say Y here to
	  support this machine type.

config MACH_TX49XX
	bool "Toshiba TX49 series based machines"
	select WAR_TX49XX_ICACHE_INDEX_INV

config MIKROTIK_RB532
	bool "Mikrotik RB532 boards"
	select CEVT_R4K
	select CSRC_R4K
	select DMA_NONCOHERENT
	select HAVE_PCI
	select IRQ_MIPS_CPU
	select SYS_HAS_CPU_MIPS32_R1
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SWAP_IO_SPACE
	select BOOT_RAW
	select GPIOLIB
	select MIPS_L1_CACHE_SHIFT_4
	help
	  Support the Mikrotik(tm) RouterBoard 532 series,
	  based on the IDT RC32434 SoC.

config CAVIUM_OCTEON_SOC
	bool "Cavium Networks Octeon SoC based boards"
	select CEVT_R4K
	select ARCH_HAS_PHYS_TO_DMA
	select HAVE_RAPIDIO
	select PHYS_ADDR_T_64BIT
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
	select EDAC_SUPPORT
	select EDAC_ATOMIC_SCRUB
	select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
	select SYS_HAS_EARLY_PRINTK
	select SYS_HAS_CPU_CAVIUM_OCTEON
	select HAVE_PCI
	select HAVE_PLAT_DELAY
	select HAVE_PLAT_FW_INIT_CMDLINE
	select HAVE_PLAT_MEMCPY
	select ZONE_DMA32
	select GPIOLIB
	select USE_OF
	select ARCH_SPARSEMEM_ENABLE
	select SYS_SUPPORTS_SMP
	select NR_CPUS_DEFAULT_64
	select MIPS_NR_CPU_NR_MAP_1024
	select BUILTIN_DTB
	select MTD
	select MTD_COMPLEX_MAPPINGS
	select SWIOTLB
	select SYS_SUPPORTS_RELOCATABLE
	help
	  This option supports all of the Octeon reference boards from Cavium
	  Networks. It builds a kernel that dynamically determines the Octeon
	  CPU type and supports all known board reference implementations.
	  Some of the supported boards are:
		EBT3000
		EBH3000
		EBH3100
		Thunder
		Kodama
		Hikari
	  Say Y here for most Octeon reference boards.

endchoice

source "arch/mips/alchemy/Kconfig"
source "arch/mips/ath25/Kconfig"
source "arch/mips/ath79/Kconfig"
source "arch/mips/bcm47xx/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/bmips/Kconfig"
source "arch/mips/generic/Kconfig"
source "arch/mips/ingenic/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/lantiq/Kconfig"
source "arch/mips/pic32/Kconfig"
source "arch/mips/ralink/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
source "arch/mips/txx9/Kconfig"
source "arch/mips/cavium-octeon/Kconfig"
source "arch/mips/loongson2ef/Kconfig"
source "arch/mips/loongson32/Kconfig"
source "arch/mips/loongson64/Kconfig"

endmenu

config GENERIC_HWEIGHT
	bool
	default y

config GENERIC_CALIBRATE_DELAY
	bool
	default y

config SCHED_OMIT_FRAME_POINTER
	bool
	default y

#
# Select some configuration options automatically based on user selections.
#
config FW_ARC
	bool

config ARCH_MAY_HAVE_PC_FDC
	bool

config BOOT_RAW
	bool

config CEVT_BCM1480
	bool

config CEVT_DS1287
	bool

config CEVT_GT641XX
	bool

config CEVT_R4K
	bool

config CEVT_SB1250
	bool

config CEVT_TXX9
	bool

config CSRC_BCM1480
	bool

config CSRC_IOASIC
	bool

config CSRC_R4K
	select CLOCKSOURCE_WATCHDOG if CPU_FREQ
	bool

config CSRC_SB1250
	bool

config MIPS_CLOCK_VSYSCALL
	def_bool CSRC_R4K || CLKSRC_MIPS_GIC

config GPIO_TXX9
	select GPIOLIB
	bool

config FW_CFE
	bool

config ARCH_SUPPORTS_UPROBES
	def_bool y

config DMA_NONCOHERENT
	bool
	#
	# MIPS allows mixing "slightly different" Cacheability and Coherency
	# Attribute bits.  It is believed that the uncached access through
	# KSEG1 and the implementation specific "uncached accelerated" used
	# by pgprot_writcombine can be mixed, and the latter sometimes provides
	# significant advantages.
	#
	select ARCH_HAS_SETUP_DMA_OPS
	select ARCH_HAS_DMA_WRITE_COMBINE
	select ARCH_HAS_DMA_PREP_COHERENT
	select ARCH_HAS_SYNC_DMA_FOR_CPU
	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
	select ARCH_HAS_DMA_SET_UNCACHED
	select DMA_NONCOHERENT_MMAP
	select NEED_DMA_MAP_STATE

config SYS_HAS_EARLY_PRINTK
	bool

config SYS_SUPPORTS_HOTPLUG_CPU
	bool

config MIPS_BONITO64
	bool

config MIPS_MSC
	bool

config SYNC_R4K
	bool

config NO_IOPORT_MAP
	def_bool n

config GENERIC_CSUM
	def_bool CPU_NO_LOAD_STORE_LR

config GENERIC_ISA_DMA
	bool
	select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
	select ISA_DMA_API

config GENERIC_ISA_DMA_SUPPORT_BROKEN
	bool
	select GENERIC_ISA_DMA

config HAVE_PLAT_DELAY
	bool

config HAVE_PLAT_FW_INIT_CMDLINE
	bool

config HAVE_PLAT_MEMCPY
	bool

config ISA_DMA_API
	bool

config SYS_SUPPORTS_RELOCATABLE
	bool
	help
	  Selected if the platform supports relocating the kernel.
	  The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
	  to allow access to command line and entropy sources.

#
# Endianness selection.  Sufficiently obscure so many users don't know what to
# answer,so we try hard to limit the available choices.  Also the use of a
# choice statement should be more obvious to the user.
#
choice
	prompt "Endianness selection"
	help
	  Some MIPS machines can be configured for either little or big endian
	  byte order. These modes require different kernels and a different
	  Linux distribution.  In general there is one preferred byteorder for a
	  particular system but some systems are just as commonly used in the
	  one or the other endianness.

config CPU_BIG_ENDIAN
	bool "Big endian"
	depends on SYS_SUPPORTS_BIG_ENDIAN

config CPU_LITTLE_ENDIAN
	bool "Little endian"
	depends on SYS_SUPPORTS_LITTLE_ENDIAN

endchoice

config EXPORT_UASM
	bool

config SYS_SUPPORTS_APM_EMULATION
	bool

config SYS_SUPPORTS_BIG_ENDIAN
	bool

config SYS_SUPPORTS_LITTLE_ENDIAN
	bool

config MIPS_HUGE_TLB_SUPPORT
	def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE

config IRQ_TXX9
	bool

config IRQ_GT641XX
	bool

config PCI_GT64XXX_PCI0
	bool

config PCI_XTALK_BRIDGE
	bool

config NO_EXCEPT_FILL
	bool

config MIPS_SPRAM
	bool

config SWAP_IO_SPACE
	bool

config SGI_HAS_INDYDOG
	bool

config SGI_HAS_HAL2
	bool

config SGI_HAS_SEEQ
	bool

config SGI_HAS_WD93
	bool

config SGI_HAS_ZILOG
	bool

config SGI_HAS_I8042
	bool

config DEFAULT_SGI_PARTITION
	bool

config FW_ARC32
	bool

config FW_SNIPROM
	bool

config BOOT_ELF32
	bool

config MIPS_L1_CACHE_SHIFT_4
	bool

config MIPS_L1_CACHE_SHIFT_5
	bool

config MIPS_L1_CACHE_SHIFT_6
	bool

config MIPS_L1_CACHE_SHIFT_7
	bool

config MIPS_L1_CACHE_SHIFT
	int
	default "7" if MIPS_L1_CACHE_SHIFT_7
	default "6" if MIPS_L1_CACHE_SHIFT_6
	default "5" if MIPS_L1_CACHE_SHIFT_5
	default "4" if MIPS_L1_CACHE_SHIFT_4
	default "5"

config ARC_CMDLINE_ONLY
	bool

config ARC_CONSOLE
	bool "ARC console support"
	depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)

config ARC_MEMORY
	bool

config ARC_PROMLIB
	bool

config FW_ARC64
	bool

config BOOT_ELF64
	bool

menu "CPU selection"

choice
	prompt "CPU type"
	default CPU_R4X00

config CPU_LOONGSON64
	bool "Loongson 64-bit CPU"
	depends on SYS_HAS_CPU_LOONGSON64
	select ARCH_HAS_PHYS_TO_DMA
	select CPU_MIPSR2
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_HUGEPAGES
	select CPU_SUPPORTS_MSA
	select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
	select CPU_MIPSR2_IRQ_VI
	select WEAK_ORDERING
	select WEAK_REORDERING_BEYOND_LLSC
	select MIPS_ASID_BITS_VARIABLE
	select MIPS_PGD_C0_CONTEXT
	select MIPS_L1_CACHE_SHIFT_6
	select MIPS_FP_SUPPORT
	select GPIOLIB
	select SWIOTLB
	select HAVE_KVM
	help
	  The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
	  cores implements the MIPS64R2 instruction set with many extensions,
	  including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
	  3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
	  Loongson-2E/2F is not covered here and will be removed in future.

config LOONGSON3_ENHANCEMENT
	bool "New Loongson-3 CPU Enhancements"
	default n
	depends on CPU_LOONGSON64
	help
	  New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
	  R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
	  FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
	  Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
	  Fast TLB refill support, etc.

	  This option enable those enhancements which are not probed at run
	  time. If you want a generic kernel to run on all Loongson 3 machines,
	  please say 'N' here. If you want a high-performance kernel to run on
	  new Loongson-3 machines only, please say 'Y' here.

config CPU_LOONGSON3_WORKAROUNDS
	bool "Loongson-3 LLSC Workarounds"
	default y if SMP
	depends on CPU_LOONGSON64
	help
	  Loongson-3 processors have the llsc issues which require workarounds.
	  Without workarounds the system may hang unexpectedly.

	  Say Y, unless you know what you are doing.

config CPU_LOONGSON3_CPUCFG_EMULATION
	bool "Emulate the CPUCFG instruction on older Loongson cores"
	default y
	depends on CPU_LOONGSON64
	help
	  Loongson-3A R4 and newer have the CPUCFG instruction available for
	  userland to query CPU capabilities, much like CPUID on x86. This
	  option provides emulation of the instruction on older Loongson
	  cores, back to Loongson-3A1000.

	  If unsure, please say Y.

config CPU_LOONGSON2E
	bool "Loongson 2E"
	depends on SYS_HAS_CPU_LOONGSON2E
	select CPU_LOONGSON2EF
	help
	  The Loongson 2E processor implements the MIPS III instruction set
	  with many extensions.

	  It has an internal FPGA northbridge, which is compatible to
	  bonito64.

config CPU_LOONGSON2F
	bool "Loongson 2F"
	depends on SYS_HAS_CPU_LOONGSON2F
	select CPU_LOONGSON2EF
	help
	  The Loongson 2F processor implements the MIPS III instruction set
	  with many extensions.

	  Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
	  have a similar programming interface with FPGA northbridge used in
	  Loongson2E.

config CPU_LOONGSON1B
	bool "Loongson 1B"
	depends on SYS_HAS_CPU_LOONGSON1B
	select CPU_LOONGSON32
	select LEDS_GPIO_REGISTER
	help
	  The Loongson 1B is a 32-bit SoC, which implements the MIPS32
	  Release 1 instruction set and part of the MIPS32 Release 2
	  instruction set.

config CPU_LOONGSON1C
	bool "Loongson 1C"
	depends on SYS_HAS_CPU_LOONGSON1C
	select CPU_LOONGSON32
	select LEDS_GPIO_REGISTER
	help
	  The Loongson 1C is a 32-bit SoC, which implements the MIPS32
	  Release 1 instruction set and part of the MIPS32 Release 2
	  instruction set.

config CPU_MIPS32_R1
	bool "MIPS32 Release 1"
	depends on SYS_HAS_CPU_MIPS32_R1
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	help
	  Choose this option to build a kernel for release 1 or later of the
	  MIPS32 architecture.  Most modern embedded systems with a 32-bit
	  MIPS processor are based on a MIPS32 processor.  If you know the
	  specific type of processor in your system, choose those that one
	  otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
	  Release 2 of the MIPS32 architecture is available since several
	  years so chances are you even have a MIPS32 Release 2 processor
	  in which case you should choose CPU_MIPS32_R2 instead for better
	  performance.

config CPU_MIPS32_R2
	bool "MIPS32 Release 2"
	depends on SYS_HAS_CPU_MIPS32_R2
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_MSA
	select HAVE_KVM
	help
	  Choose this option to build a kernel for release 2 or later of the
	  MIPS32 architecture.  Most modern embedded systems with a 32-bit
	  MIPS processor are based on a MIPS32 processor.  If you know the
	  specific type of processor in your system, choose those that one
	  otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.

config CPU_MIPS32_R5
	bool "MIPS32 Release 5"
	depends on SYS_HAS_CPU_MIPS32_R5
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_MSA
	select HAVE_KVM
	select MIPS_O32_FP64_SUPPORT
	help
	  Choose this option to build a kernel for release 5 or later of the
	  MIPS32 architecture.  New MIPS processors, starting with the Warrior
	  family, are based on a MIPS32r5 processor. If you own an older
	  processor, you probably need to select MIPS32r1 or MIPS32r2 instead.

config CPU_MIPS32_R6
	bool "MIPS32 Release 6"
	depends on SYS_HAS_CPU_MIPS32_R6
	select CPU_HAS_PREFETCH
	select CPU_NO_LOAD_STORE_LR
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_MSA
	select HAVE_KVM
	select MIPS_O32_FP64_SUPPORT
	help
	  Choose this option to build a kernel for release 6 or later of the
	  MIPS32 architecture.  New MIPS processors, starting with the Warrior
	  family, are based on a MIPS32r6 processor. If you own an older
	  processor, you probably need to select MIPS32r1 or MIPS32r2 instead.

config CPU_MIPS64_R1
	bool "MIPS64 Release 1"
	depends on SYS_HAS_CPU_MIPS64_R1
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_HUGEPAGES
	help
	  Choose this option to build a kernel for release 1 or later of the
	  MIPS64 architecture.  Many modern embedded systems with a 64-bit
	  MIPS processor are based on a MIPS64 processor.  If you know the
	  specific type of processor in your system, choose those that one
	  otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
	  Release 2 of the MIPS64 architecture is available since several
	  years so chances are you even have a MIPS64 Release 2 processor
	  in which case you should choose CPU_MIPS64_R2 instead for better
	  performance.

config CPU_MIPS64_R2
	bool "MIPS64 Release 2"
	depends on SYS_HAS_CPU_MIPS64_R2
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_HUGEPAGES
	select CPU_SUPPORTS_MSA
	select HAVE_KVM
	help
	  Choose this option to build a kernel for release 2 or later of the
	  MIPS64 architecture.  Many modern embedded systems with a 64-bit
	  MIPS processor are based on a MIPS64 processor.  If you know the
	  specific type of processor in your system, choose those that one
	  otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.

config CPU_MIPS64_R5
	bool "MIPS64 Release 5"
	depends on SYS_HAS_CPU_MIPS64_R5
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_HUGEPAGES
	select CPU_SUPPORTS_MSA
	select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
	select HAVE_KVM
	help
	  Choose this option to build a kernel for release 5 or later of the
	  MIPS64 architecture.  This is a intermediate MIPS architecture
	  release partly implementing release 6 features. Though there is no
	  any hardware known to be based on this release.

config CPU_MIPS64_R6
	bool "MIPS64 Release 6"
	depends on SYS_HAS_CPU_MIPS64_R6
	select CPU_HAS_PREFETCH
	select CPU_NO_LOAD_STORE_LR
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_HUGEPAGES
	select CPU_SUPPORTS_MSA
	select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
	select HAVE_KVM
	help
	  Choose this option to build a kernel for release 6 or later of the
	  MIPS64 architecture.  New MIPS processors, starting with the Warrior
	  family, are based on a MIPS64r6 processor. If you own an older
	  processor, you probably need to select MIPS64r1 or MIPS64r2 instead.

config CPU_P5600
	bool "MIPS Warrior P5600"
	depends on SYS_HAS_CPU_P5600
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_MSA
	select CPU_SUPPORTS_CPUFREQ
	select CPU_MIPSR2_IRQ_VI
	select CPU_MIPSR2_IRQ_EI
	select HAVE_KVM
	select MIPS_O32_FP64_SUPPORT
	help
	  Choose this option to build a kernel for MIPS Warrior P5600 CPU.
	  It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
	  MMU with two-levels TLB, UCA, MSA, MDU core level features and system
	  level features like up to six P5600 calculation cores, CM2 with L2
	  cache, IOCU/IOMMU (though might be unused depending on the system-
	  specific IP core configuration), GIC, CPC, virtualisation module,
	  eJTAG and PDtrace.

config CPU_R3000
	bool "R3000"
	depends on SYS_HAS_CPU_R3000
	select CPU_HAS_WB
	select CPU_R3K_TLB
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	help
	  Please make sure to pick the right CPU type. Linux/MIPS is not
	  designed to be generic, i.e. Kernels compiled for R3000 CPUs will
	  *not* work on R4000 machines and vice versa.  However, since most
	  of the supported machines have an R4000 (or similar) CPU, R4x00
	  might be a safe bet.  If the resulting kernel does not work,
	  try to recompile with R3000.

config CPU_R4300
	bool "R4300"
	depends on SYS_HAS_CPU_R4300
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	help
	  MIPS Technologies R4300-series processors.

config CPU_R4X00
	bool "R4x00"
	depends on SYS_HAS_CPU_R4X00
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HUGEPAGES
	help
	  MIPS Technologies R4000-series processors other than 4300, including
	  the R4000, R4400, R4600, and 4700.

config CPU_TX49XX
	bool "R49XX"
	depends on SYS_HAS_CPU_TX49XX
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HUGEPAGES

config CPU_R5000
	bool "R5000"
	depends on SYS_HAS_CPU_R5000
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HUGEPAGES
	help
	  MIPS Technologies R5000-series processors other than the Nevada.

config CPU_R5500
	bool "R5500"
	depends on SYS_HAS_CPU_R5500
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HUGEPAGES
	help
	  NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
	  instruction set.

config CPU_NEVADA
	bool "RM52xx"
	depends on SYS_HAS_CPU_NEVADA
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HUGEPAGES
	help
	  QED / PMC-Sierra RM52xx-series ("Nevada") processors.

config CPU_R10000
	bool "R10000"
	depends on SYS_HAS_CPU_R10000
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_HUGEPAGES
	help
	  MIPS Technologies R10000-series processors.

config CPU_RM7000
	bool "RM7000"
	depends on SYS_HAS_CPU_RM7000
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_HUGEPAGES

config CPU_SB1
	bool "SB1"
	depends on SYS_HAS_CPU_SB1
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_HUGEPAGES
	select WEAK_ORDERING

config CPU_CAVIUM_OCTEON
	bool "Cavium Octeon processor"
	depends on SYS_HAS_CPU_CAVIUM_OCTEON
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_64BIT_KERNEL
	select WEAK_ORDERING
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_HUGEPAGES
	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
	select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
	select MIPS_L1_CACHE_SHIFT_7
	select HAVE_KVM
	help
	  The Cavium Octeon processor is a highly integrated chip containing
	  many ethernet hardware widgets for networking tasks. The processor
	  can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
	  Full details can be found at http://www.caviumnetworks.com.

config CPU_BMIPS
	bool "Broadcom BMIPS"
	depends on SYS_HAS_CPU_BMIPS
	select CPU_MIPS32
	select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
	select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
	select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
	select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
	select CPU_SUPPORTS_32BIT_KERNEL
	select DMA_NONCOHERENT
	select IRQ_MIPS_CPU
	select SWAP_IO_SPACE
	select WEAK_ORDERING
	select CPU_SUPPORTS_HIGHMEM
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_CPUFREQ
	select MIPS_EXTERNAL_TIMER
	select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
	help
	  Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.

endchoice

config CPU_MIPS32_3_5_FEATURES
	bool "MIPS32 Release 3.5 Features"
	depends on SYS_HAS_CPU_MIPS32_R3_5
	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
		   CPU_P5600
	help
	  Choose this option to build a kernel for release 2 or later of the
	  MIPS32 architecture including features from the 3.5 release such as
	  support for Enhanced Virtual Addressing (EVA).

config CPU_MIPS32_3_5_EVA
	bool "Enhanced Virtual Addressing (EVA)"
	depends on CPU_MIPS32_3_5_FEATURES
	select EVA
	default y
	help
	  Choose this option if you want to enable the Enhanced Virtual
	  Addressing (EVA) on your MIPS32 core (such as proAptiv).
	  One of its primary benefits is an increase in the maximum size
	  of lowmem (up to 3GB). If unsure, say 'N' here.

config CPU_MIPS32_R5_FEATURES
	bool "MIPS32 Release 5 Features"
	depends on SYS_HAS_CPU_MIPS32_R5
	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
	help
	  Choose this option to build a kernel for release 2 or later of the
	  MIPS32 architecture including features from release 5 such as
	  support for Extended Physical Addressing (XPA).

config CPU_MIPS32_R5_XPA
	bool "Extended Physical Addressing (XPA)"
	depends on CPU_MIPS32_R5_FEATURES
	depends on !EVA
	depends on !PAGE_SIZE_4KB
	depends on SYS_SUPPORTS_HIGHMEM
	select XPA
	select HIGHMEM
	select PHYS_ADDR_T_64BIT
	default n
	help
	  Choose this option if you want to enable the Extended Physical
	  Addressing (XPA) on your MIPS32 core (such as P5600 series). The
	  benefit is to increase physical addressing equal to or greater
	  than 40 bits. Note that this has the side effect of turning on
	  64-bit addressing which in turn makes the PTEs 64-bit in size.
	  If unsure, say 'N' here.

if CPU_LOONGSON2F
config CPU_NOP_WORKAROUNDS
	bool

config CPU_JUMP_WORKAROUNDS
	bool

config CPU_LOONGSON2F_WORKAROUNDS
	bool "Loongson 2F Workarounds"
	default y
	select CPU_NOP_WORKAROUNDS
	select CPU_JUMP_WORKAROUNDS
	help
	  Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
	  require workarounds.  Without workarounds the system may hang
	  unexpectedly.  For more information please refer to the gas
	  -mfix-loongson2f-nop and -mfix-loongson2f-jump options.

	  Loongson 2F03 and later have fixed these issues and no workarounds
	  are needed.  The workarounds have no significant side effect on them
	  but may decrease the performance of the system so this option should
	  be disabled unless the kernel is intended to be run on 2F01 or 2F02
	  systems.

	  If unsure, please say Y.
endif # CPU_LOONGSON2F

config SYS_SUPPORTS_ZBOOT
	bool
	select HAVE_KERNEL_GZIP
	select HAVE_KERNEL_BZIP2
	select HAVE_KERNEL_LZ4
	select HAVE_KERNEL_LZMA
	select HAVE_KERNEL_LZO
	select HAVE_KERNEL_XZ
	select HAVE_KERNEL_ZSTD

config SYS_SUPPORTS_ZBOOT_UART16550
	bool
	select SYS_SUPPORTS_ZBOOT

config SYS_SUPPORTS_ZBOOT_UART_PROM
	bool
	select SYS_SUPPORTS_ZBOOT

config CPU_LOONGSON2EF
	bool
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_64BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_HUGEPAGES

config CPU_LOONGSON32
	bool
	select CPU_MIPS32
	select CPU_MIPSR2
	select CPU_HAS_PREFETCH
	select CPU_SUPPORTS_32BIT_KERNEL
	select CPU_SUPPORTS_HIGHMEM
	select CPU_SUPPORTS_CPUFREQ

config CPU_BMIPS32_3300
	select SMP_UP if SMP
	bool

config CPU_BMIPS4350
	bool
	select SYS_SUPPORTS_SMP
	select SYS_SUPPORTS_HOTPLUG_CPU

config CPU_BMIPS4380
	bool
	select MIPS_L1_CACHE_SHIFT_6
	select SYS_SUPPORTS_SMP
	select SYS_SUPPORTS_HOTPLUG_CPU
	select CPU_HAS_RIXI

config CPU_BMIPS5000
	bool
	select MIPS_CPU_SCACHE
	select MIPS_L1_CACHE_SHIFT_7
	select SYS_SUPPORTS_SMP
	select SYS_SUPPORTS_HOTPLUG_CPU
	select CPU_HAS_RIXI

config SYS_HAS_CPU_LOONGSON64
	bool
	select CPU_SUPPORTS_CPUFREQ
	select CPU_HAS_RIXI

config SYS_HAS_CPU_LOONGSON2E
	bool

config SYS_HAS_CPU_LOONGSON2F
	bool
	select CPU_SUPPORTS_CPUFREQ
	select CPU_SUPPORTS_ADDRWINCFG if 64BIT

config SYS_HAS_CPU_LOONGSON1B
	bool

config SYS_HAS_CPU_LOONGSON1C
	bool

config SYS_HAS_CPU_MIPS32_R1
	bool

config SYS_HAS_CPU_MIPS32_R2
	bool

config SYS_HAS_CPU_MIPS32_R3_5
	bool

config SYS_HAS_CPU_MIPS32_R5
	bool

config SYS_HAS_CPU_MIPS32_R6
	bool

config SYS_HAS_CPU_MIPS64_R1
	bool

config SYS_HAS_CPU_MIPS64_R2
	bool

config SYS_HAS_CPU_MIPS64_R5
	bool

config SYS_HAS_CPU_MIPS64_R6
	bool

config SYS_HAS_CPU_P5600
	bool

config SYS_HAS_CPU_R3000
	bool

config SYS_HAS_CPU_R4300
	bool

config SYS_HAS_CPU_R4X00
	bool

config SYS_HAS_CPU_TX49XX
	bool

config SYS_HAS_CPU_R5000
	bool

config SYS_HAS_CPU_R5500
	bool

config SYS_HAS_CPU_NEVADA
	bool

config SYS_HAS_CPU_R10000
	bool

config SYS_HAS_CPU_RM7000
	bool

config SYS_HAS_CPU_SB1
	bool

config SYS_HAS_CPU_CAVIUM_OCTEON
	bool

config SYS_HAS_CPU_BMIPS
	bool

config SYS_HAS_CPU_BMIPS32_3300
	bool
	select SYS_HAS_CPU_BMIPS

config SYS_HAS_CPU_BMIPS4350
	bool
	select SYS_HAS_CPU_BMIPS

config SYS_HAS_CPU_BMIPS4380
	bool
	select SYS_HAS_CPU_BMIPS

config SYS_HAS_CPU_BMIPS5000
	bool
	select SYS_HAS_CPU_BMIPS

#
# CPU may reorder R->R, R->W, W->R, W->W
# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
#
config WEAK_ORDERING
	bool

#
# CPU may reorder reads and writes beyond LL/SC
# CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
#
config WEAK_REORDERING_BEYOND_LLSC
	bool
endmenu

#
# These two indicate any level of the MIPS32 and MIPS64 architecture
#
config CPU_MIPS32
	bool
	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
		     CPU_MIPS32_R6 || CPU_P5600

config CPU_MIPS64
	bool
	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
		     CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON

#
# These indicate the revision of the architecture
#
config CPU_MIPSR1
	bool
	default y if CPU_MIPS32_R1 || CPU_MIPS64_R1

config CPU_MIPSR2
	bool
	default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
	select CPU_HAS_RIXI
	select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
	select MIPS_SPRAM

config CPU_MIPSR5
	bool
	default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
	select CPU_HAS_RIXI
	select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
	select MIPS_SPRAM

config CPU_MIPSR6
	bool
	default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
	select CPU_HAS_RIXI
	select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
	select HAVE_ARCH_BITREVERSE
	select MIPS_ASID_BITS_VARIABLE
	select MIPS_CRC_SUPPORT
	select MIPS_SPRAM

config TARGET_ISA_REV
	int
	default 1 if CPU_MIPSR1
	default 2 if CPU_MIPSR2
	default 5 if CPU_MIPSR5
	default 6 if CPU_MIPSR6
	default 0
	help
	  Reflects the ISA revision being targeted by the kernel build. This
	  is effectively the Kconfig equivalent of MIPS_ISA_REV.

config EVA
	bool

config XPA
	bool

config SYS_SUPPORTS_32BIT_KERNEL
	bool
config SYS_SUPPORTS_64BIT_KERNEL
	bool
config CPU_SUPPORTS_32BIT_KERNEL
	bool
config CPU_SUPPORTS_64BIT_KERNEL
	bool
config CPU_SUPPORTS_CPUFREQ
	bool
config CPU_SUPPORTS_ADDRWINCFG
	bool
config CPU_SUPPORTS_HUGEPAGES
	bool
	depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
config MIPS_PGD_C0_CONTEXT
	bool
	depends on 64BIT
	default y if (CPU_MIPSR2 || CPU_MIPSR6)

#
# Set to y for ptrace access to watch registers.
#
config HARDWARE_WATCHPOINTS
	bool
	default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6

menu "Kernel type"

choice
	prompt "Kernel code model"
	help
	  You should only select this option if you have a workload that
	  actually benefits from 64-bit processing or if your machine has
	  large memory.  You will only be presented a single option in this
	  menu if your system does not support both 32-bit and 64-bit kernels.

config 32BIT
	bool "32-bit kernel"
	depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
	select TRAD_SIGNALS
	help
	  Select this option if you want to build a 32-bit kernel.

config 64BIT
	bool "64-bit kernel"
	depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
	help
	  Select this option if you want to build a 64-bit kernel.

endchoice

config MIPS_VA_BITS_48
	bool "48 bits virtual memory"
	depends on 64BIT
	help
	  Support a maximum at least 48 bits of application virtual
	  memory.  Default is 40 bits or less, depending on the CPU.
	  For page sizes 16k and above, this option results in a small
	  memory overhead for page tables.  For 4k page size, a fourth
	  level of page tables is added which imposes both a memory
	  overhead as well as slower TLB fault handling.

	  If unsure, say N.

config ZBOOT_LOAD_ADDRESS
	hex "Compressed kernel load address"
	default 0xffffffff80400000 if BCM47XX
	default 0x0
	depends on SYS_SUPPORTS_ZBOOT
	help
	  The address to load compressed kernel, aka vmlinuz.

	  This is only used if non-zero.

choice
	prompt "Kernel page size"
	default PAGE_SIZE_4KB

config PAGE_SIZE_4KB
	bool "4kB"
	depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
	help
	  This option select the standard 4kB Linux page size.  On some
	  R3000-family processors this is the only available page size.  Using
	  4kB page size will minimize memory consumption and is therefore
	  recommended for low memory systems.

config PAGE_SIZE_8KB
	bool "8kB"
	depends on CPU_CAVIUM_OCTEON
	depends on !MIPS_VA_BITS_48
	help
	  Using 8kB page size will result in higher performance kernel at
	  the price of higher memory consumption.  This option is available
	  only on cnMIPS processors.  Note that you will need a suitable Linux
	  distribution to support this.

config PAGE_SIZE_16KB
	bool "16kB"
	depends on !CPU_R3000
	help
	  Using 16kB page size will result in higher performance kernel at
	  the price of higher memory consumption.  This option is available on
	  all non-R3000 family processors.  Note that you will need a suitable
	  Linux distribution to support this.

config PAGE_SIZE_32KB
	bool "32kB"
	depends on CPU_CAVIUM_OCTEON
	depends on !MIPS_VA_BITS_48
	help
	  Using 32kB page size will result in higher performance kernel at
	  the price of higher memory consumption.  This option is available
	  only on cnMIPS cores.  Note that you will need a suitable Linux
	  distribution to support this.

config PAGE_SIZE_64KB
	bool "64kB"
	depends on !CPU_R3000
	help
	  Using 64kB page size will result in higher performance kernel at
	  the price of higher memory consumption.  This option is available on
	  all non-R3000 family processor.  Not that at the time of this
	  writing this option is still high experimental.

endchoice

config ARCH_FORCE_MAX_ORDER
	int "Maximum zone order"
	default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
	default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
	default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
	default "10"
	help
	  The kernel memory allocator divides physically contiguous memory
	  blocks into "zones", where each zone is a power of two number of
	  pages.  This option selects the largest power of two that the kernel
	  keeps in the memory allocator.  If you need to allocate very large
	  blocks of physically contiguous memory, then you may need to
	  increase this value.

	  The page size is not necessarily 4KB.  Keep this in mind
	  when choosing a value for this option.

config BOARD_SCACHE
	bool

config IP22_CPU_SCACHE
	bool
	select BOARD_SCACHE

#
# Support for a MIPS32 / MIPS64 style S-caches
#
config MIPS_CPU_SCACHE
	bool
	select BOARD_SCACHE

config R5000_CPU_SCACHE
	bool
	select BOARD_SCACHE

config RM7000_CPU_SCACHE
	bool
	select BOARD_SCACHE

config SIBYTE_DMA_PAGEOPS
	bool "Use DMA to clear/copy pages"
	depends on CPU_SB1
	help
	  Instead of using the CPU to zero and copy pages, use a Data Mover
	  channel.  These DMA channels are otherwise unused by the standard
	  SiByte Linux port.  Seems to give a small performance benefit.

config CPU_HAS_PREFETCH
	bool

config CPU_GENERIC_DUMP_TLB
	bool
	default y if !CPU_R3000

config MIPS_FP_SUPPORT
	bool "Floating Point support" if EXPERT
	default y
	help
	  Select y to include support for floating point in the kernel
	  including initialization of FPU hardware, FP context save & restore
	  and emulation of an FPU where necessary. Without this support any
	  userland program attempting to use floating point instructions will
	  receive a SIGILL.

	  If you know that your userland will not attempt to use floating point
	  instructions then you can say n here to shrink the kernel a little.

	  If unsure, say y.

config CPU_R2300_FPU
	bool
	depends on MIPS_FP_SUPPORT
	default y if CPU_R3000

config CPU_R3K_TLB
	bool

config CPU_R4K_FPU
	bool
	depends on MIPS_FP_SUPPORT
	default y if !CPU_R2300_FPU

config CPU_R4K_CACHE_TLB
	bool
	default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)

config MIPS_MT_SMP
	bool "MIPS MT SMP support (1 TC on each available VPE)"
	default y
	depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
	select CPU_MIPSR2_IRQ_VI
	select CPU_MIPSR2_IRQ_EI
	select SYNC_R4K
	select MIPS_MT
	select SMP
	select SMP_UP
	select SYS_SUPPORTS_SMP
	select SYS_SUPPORTS_SCHED_SMT
	select MIPS_PERF_SHARED_TC_COUNTERS
	help
	  This is a kernel model which is known as SMVP. This is supported
	  on cores with the MT ASE and uses the available VPEs to implement
	  virtual processors which supports SMP. This is equivalent to the
	  Intel Hyperthreading feature. For further information go to
	  <http://www.imgtec.com/mips/mips-multithreading.asp>.

config MIPS_MT
	bool

config SCHED_SMT
	bool "SMT (multithreading) scheduler support"
	depends on SYS_SUPPORTS_SCHED_SMT
	default n
	help
	  SMT scheduler support improves the CPU scheduler's decision making
	  when dealing with MIPS MT enabled cores at a cost of slightly
	  increased overhead in some places. If unsure say N here.

config SYS_SUPPORTS_SCHED_SMT
	bool

config SYS_SUPPORTS_MULTITHREADING
	bool

config MIPS_MT_FPAFF
	bool "Dynamic FPU affinity for FP-intensive threads"
	default y
	depends on MIPS_MT_SMP

config MIPSR2_TO_R6_EMULATOR
	bool "MIPS R2-to-R6 emulator"
	depends on CPU_MIPSR6
	depends on MIPS_FP_SUPPORT
	default y
	help
	  Choose this option if you want to run non-R6 MIPS userland code.
	  Even if you say 'Y' here, the emulator will still be disabled by
	  default. You can enable it using the 'mipsr2emu' kernel option.
	  The only reason this is a build-time option is to save ~14K from the
	  final kernel image.

config SYS_SUPPORTS_VPE_LOADER
	bool
	depends on SYS_SUPPORTS_MULTITHREADING
	help
	  Indicates that the platform supports the VPE loader, and provides
	  physical_memsize.

config MIPS_VPE_LOADER
	bool "VPE loader support."
	depends on SYS_SUPPORTS_VPE_LOADER && MODULES
	select CPU_MIPSR2_IRQ_VI
	select CPU_MIPSR2_IRQ_EI
	select MIPS_MT
	help
	  Includes a loader for loading an elf relocatable object
	  onto another VPE and running it.

config MIPS_VPE_LOADER_MT
	bool
	default "y"
	depends on MIPS_VPE_LOADER

config MIPS_VPE_LOADER_TOM
	bool "Load VPE program into memory hidden from linux"
	depends on MIPS_VPE_LOADER
	default y
	help
	  The loader can use memory that is present but has been hidden from
	  Linux using the kernel command line option "mem=xxMB". It's up to
	  you to ensure the amount you put in the option and the space your
	  program requires is less or equal to the amount physically present.

config MIPS_VPE_APSP_API
	bool "Enable support for AP/SP API (RTLX)"
	depends on MIPS_VPE_LOADER

config MIPS_VPE_APSP_API_MT
	bool
	default "y"
	depends on MIPS_VPE_APSP_API

config MIPS_CPS
	bool "MIPS Coherent Processing System support"
	depends on SYS_SUPPORTS_MIPS_CPS
	select MIPS_CM
	select MIPS_CPS_PM if HOTPLUG_CPU
	select SMP
	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
	select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
	select SYS_SUPPORTS_HOTPLUG_CPU
	select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
	select SYS_SUPPORTS_SMP
	select WEAK_ORDERING
	select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
	help
	  Select this if you wish to run an SMP kernel across multiple cores
	  within a MIPS Coherent Processing System. When this option is
	  enabled the kernel will probe for other cores and boot them with
	  no external assistance. It is safe to enable this when hardware
	  support is unavailable.

config MIPS_CPS_PM
	depends on MIPS_CPS
	bool

config MIPS_CM
	bool
	select MIPS_CPC

config MIPS_CPC
	bool

config SB1_PASS_2_WORKAROUNDS
	bool
	depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
	default y

config SB1_PASS_2_1_WORKAROUNDS
	bool
	depends on CPU_SB1 && CPU_SB1_PASS_2
	default y

choice
	prompt "SmartMIPS or microMIPS ASE support"

config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
	bool "None"
	help
	  Select this if you want neither microMIPS nor SmartMIPS support

config CPU_HAS_SMARTMIPS
	depends on SYS_SUPPORTS_SMARTMIPS
	bool "SmartMIPS"
	help
	  SmartMIPS is a extension of the MIPS32 architecture aimed at
	  increased security at both hardware and software level for
	  smartcards.  Enabling this option will allow proper use of the
	  SmartMIPS instructions by Linux applications.  However a kernel with
	  this option will not work on a MIPS core without SmartMIPS core.  If
	  you don't know you probably don't have SmartMIPS and should say N
	  here.

config CPU_MICROMIPS
	depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
	bool "microMIPS"
	help
	  When this option is enabled the kernel will be built using the
	  microMIPS ISA

endchoice

config CPU_HAS_MSA
	bool "Support for the MIPS SIMD Architecture"
	depends on CPU_SUPPORTS_MSA
	depends on MIPS_FP_SUPPORT
	depends on 64BIT || MIPS_O32_FP64_SUPPORT
	help
	  MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
	  and a set of SIMD instructions to operate on them. When this option
	  is enabled the kernel will support allocating & switching MSA
	  vector register contexts. If you know that your kernel will only be
	  running on CPUs which do not support MSA or that your userland will
	  not be making use of it then you may wish to say N here to reduce
	  the size & complexity of your kernel.

	  If unsure, say Y.

config CPU_HAS_WB
	bool

config XKS01
	bool

config CPU_HAS_DIEI
	depends on !CPU_DIEI_BROKEN
	bool

config CPU_DIEI_BROKEN
	bool

config CPU_HAS_RIXI
	bool

config CPU_NO_LOAD_STORE_LR
	bool
	help
	  CPU lacks support for unaligned load and store instructions:
	  LWL, LWR, SWL, SWR (Load/store word left/right).
	  LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
	  systems).

#
# Vectored interrupt mode is an R2 feature
#
config CPU_MIPSR2_IRQ_VI
	bool

#
# Extended interrupt mode is an R2 feature
#
config CPU_MIPSR2_IRQ_EI
	bool

config CPU_HAS_SYNC
	bool
	depends on !CPU_R3000
	default y

#
# CPU non-features
#

# Work around the "daddi" and "daddiu" CPU errata:
#
# - The `daddi' instruction fails to trap on overflow.
#   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
#   erratum #23
#
# - The `daddiu' instruction can produce an incorrect result.
#   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
#   erratum #41
#   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
#   #15
#   "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
#   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
config CPU_DADDI_WORKAROUNDS
	bool

# Work around certain R4000 CPU errata (as implemented by GCC):
#
# - A double-word or a variable shift may give an incorrect result
#   if executed immediately after starting an integer division:
#   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
#   erratum #28
#   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
#   #19
#
# - A double-word or a variable shift may give an incorrect result
#   if executed while an integer multiplication is in progress:
#   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
#   errata #16 & #28
#
# - An integer division may give an incorrect result if started in
#   a delay slot of a taken branch or a jump:
#   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
#   erratum #52
config CPU_R4000_WORKAROUNDS
	bool
	select CPU_R4400_WORKAROUNDS

# Work around certain R4400 CPU errata (as implemented by GCC):
#
# - A double-word or a variable shift may give an incorrect result
#   if executed immediately after starting an integer division:
#   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
#   "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
config CPU_R4400_WORKAROUNDS
	bool

config CPU_R4X00_BUGS64
	bool
	default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)

config MIPS_ASID_SHIFT
	int
	default 6 if CPU_R3000
	default 0

config MIPS_ASID_BITS
	int
	default 0 if MIPS_ASID_BITS_VARIABLE
	default 6 if CPU_R3000
	default 8

config MIPS_ASID_BITS_VARIABLE
	bool

config MIPS_CRC_SUPPORT
	bool

# R4600 erratum.  Due to the lack of errata information the exact
# technical details aren't known.  I've experimentally found that disabling
# interrupts during indexed I-cache flushes seems to be sufficient to deal
# with the issue.
config WAR_R4600_V1_INDEX_ICACHEOP
	bool

# Pleasures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
#
#  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
#      Hit_Invalidate_D and Create_Dirty_Excl_D should only be
#      executed if there is no other dcache activity. If the dcache is
#      accessed for another instruction immediately preceding when these
#      cache instructions are executing, it is possible that the dcache
#      tag match outputs used by these cache instructions will be
#      incorrect. These cache instructions should be preceded by at least
#      four instructions that are not any kind of load or store
#      instruction.
#
#      This is not allowed:    lw
#                              nop
#                              nop
#                              nop
#                              cache       Hit_Writeback_Invalidate_D
#
#      This is allowed:        lw
#                              nop
#                              nop
#                              nop
#                              nop
#                              cache       Hit_Writeback_Invalidate_D
config WAR_R4600_V1_HIT_CACHEOP
	bool

# Writeback and invalidate the primary cache dcache before DMA.
#
# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
# operate correctly if the internal data cache refill buffer is empty.  These
# CACHE instructions should be separated from any potential data cache miss
# by a load instruction to an uncached address to empty the response buffer."
# (Revision 2.0 device errata from IDT available on https://www.idt.com/
# in .pdf format.)
config WAR_R4600_V2_HIT_CACHEOP
	bool

# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
# the line which this instruction itself exists, the following
# operation is not guaranteed."
#
# Workaround: do two phase flushing for Index_Invalidate_I
config WAR_TX49XX_ICACHE_INDEX_INV
	bool

# The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
# opposes it being called that) where invalid instructions in the same
# I-cache line worth of instructions being fetched may case spurious
# exceptions.
config WAR_ICACHE_REFILLS
	bool

# On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
# may cause ll / sc and lld / scd sequences to execute non-atomically.
config WAR_R10000_LLSC
	bool

# 34K core erratum: "Problems Executing the TLBR Instruction"
config WAR_MIPS34K_MISSED_ITLB
	bool

#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
#   caches such as R3000, SB1, R7000 or those that look like they're virtually
#   indexed such as R4000/R4400 SC and MC versions or R10000.  So for the
#   moment we protect the user and offer the highmem option only on machines
#   where it's known to be safe.  This will not offer highmem on a few systems
#   such as MIPS32 and MIPS64 CPUs which may have virtual and physically
#   indexed CPUs but we're playing safe.
# - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
#   know they might have memory configurations that could make use of highmem
#   support.
#
config HIGHMEM
	bool "High Memory Support"
	depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
	select KMAP_LOCAL

config CPU_SUPPORTS_HIGHMEM
	bool

config SYS_SUPPORTS_HIGHMEM
	bool

config SYS_SUPPORTS_SMARTMIPS
	bool

config SYS_SUPPORTS_MICROMIPS
	bool

config SYS_SUPPORTS_MIPS16
	bool
	help
	  This option must be set if a kernel might be executed on a MIPS16-
	  enabled CPU even if MIPS16 is not actually being used.  In other
	  words, it makes the kernel MIPS16-tolerant.

config CPU_SUPPORTS_MSA
	bool

config ARCH_FLATMEM_ENABLE
	def_bool y
	depends on !NUMA && !CPU_LOONGSON2EF

config ARCH_SPARSEMEM_ENABLE
	bool

config NUMA
	bool "NUMA Support"
	depends on SYS_SUPPORTS_NUMA
	select SMP
	select HAVE_SETUP_PER_CPU_AREA
	select NEED_PER_CPU_EMBED_FIRST_CHUNK
	help
	  Say Y to compile the kernel to support NUMA (Non-Uniform Memory
	  Access).  This option improves performance on systems with more
	  than two nodes; on two node systems it is generally better to
	  leave it disabled; on single node systems leave this option
	  disabled.

config SYS_SUPPORTS_NUMA
	bool

config HAVE_ARCH_NODEDATA_EXTENSION
	bool

config RELOCATABLE
	bool "Relocatable kernel"
	depends on SYS_SUPPORTS_RELOCATABLE
	depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
		   CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
		   CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
		   CPU_P5600 || CAVIUM_OCTEON_SOC || \
		   CPU_LOONGSON64
	help
	  This builds a kernel image that retains relocation information
	  so it can be loaded someplace besides the default 1MB.
	  The relocations make the kernel binary about 15% larger,
	  but are discarded at runtime

config RELOCATION_TABLE_SIZE
	hex "Relocation table size"
	depends on RELOCATABLE
	range 0x0 0x01000000
	default "0x00200000" if CPU_LOONGSON64
	default "0x00100000"
	help
	  A table of relocation data will be appended to the kernel binary
	  and parsed at boot to fix up the relocated kernel.

	  This option allows the amount of space reserved for the table to be
	  adjusted, although the default of 1Mb should be ok in most cases.

	  The build will fail and a valid size suggested if this is too small.

	  If unsure, leave at the default value.

config RANDOMIZE_BASE
	bool "Randomize the address of the kernel image"
	depends on RELOCATABLE
	help
	  Randomizes the physical and virtual address at which the
	  kernel image is loaded, as a security feature that
	  deters exploit attempts relying on knowledge of the location
	  of kernel internals.

	  Entropy is generated using any coprocessor 0 registers available.

	  The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.

	  If unsure, say N.

config RANDOMIZE_BASE_MAX_OFFSET
	hex "Maximum kASLR offset" if EXPERT
	depends on RANDOMIZE_BASE
	range 0x0 0x40000000 if EVA || 64BIT
	range 0x0 0x08000000
	default "0x01000000"
	help
	  When kASLR is active, this provides the maximum offset that will
	  be applied to the kernel image. It should be set according to the
	  amount of physical RAM available in the target system minus
	  PHYSICAL_START and must be a power of 2.

	  This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
	  EVA or 64-bit. The default is 16Mb.

config NODES_SHIFT
	int
	default "6"
	depends on NUMA

config HW_PERF_EVENTS
	bool "Enable hardware performance counter support for perf events"
	depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
	default y
	help
	  Enable hardware performance counter support for perf events. If
	  disabled, perf events will use software events only.

config DMI
	bool "Enable DMI scanning"
	depends on MACH_LOONGSON64
	select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
	default y
	help
	  Enabled scanning of DMI to identify machine quirks. Say Y
	  here unless you have verified that your setup is not
	  affected by entries in the DMI blacklist. Required by PNP
	  BIOS code.

config SMP
	bool "Multi-Processing support"
	depends on SYS_SUPPORTS_SMP
	help
	  This enables support for systems with more than one CPU. If you have
	  a system with only one CPU, say N. If you have a system with more
	  than one CPU, say Y.

	  If you say N here, the kernel will run on uni- and multiprocessor
	  machines, but will use only one CPU of a multiprocessor machine. If
	  you say Y here, the kernel will run on many, but not all,
	  uniprocessor machines. On a uniprocessor machine, the kernel
	  will run faster if you say N here.

	  People using multiprocessor machines who say Y here should also say
	  Y to "Enhanced Real Time Clock Support", below.

	  See also the SMP-HOWTO available at
	  <https://www.tldp.org/docs.html#howto>.

	  If you don't know what to do here, say N.

config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
	depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
	help
	  Say Y here to allow turning CPUs off and on. CPUs can be
	  controlled through /sys/devices/system/cpu.
	  (Note: power management support will enable this option
	    automatically on SMP systems. )
	  Say N if you want to disable CPU hotplug.

config SMP_UP
	bool

config SYS_SUPPORTS_MIPS_CPS
	bool

config SYS_SUPPORTS_SMP
	bool

config NR_CPUS_DEFAULT_4
	bool

config NR_CPUS_DEFAULT_8
	bool

config NR_CPUS_DEFAULT_16
	bool

config NR_CPUS_DEFAULT_32
	bool

config NR_CPUS_DEFAULT_64
	bool

config NR_CPUS
	int "Maximum number of CPUs (2-256)"
	range 2 256
	depends on SMP
	default "4" if NR_CPUS_DEFAULT_4
	default "8" if NR_CPUS_DEFAULT_8
	default "16" if NR_CPUS_DEFAULT_16
	default "32" if NR_CPUS_DEFAULT_32
	default "64" if NR_CPUS_DEFAULT_64
	help
	  This allows you to specify the maximum number of CPUs which this
	  kernel will support.  The maximum supported value is 32 for 32-bit
	  kernel and 64 for 64-bit kernels; the minimum value which makes
	  sense is 1 for Qemu (useful only for kernel debugging purposes)
	  and 2 for all others.

	  This is purely to save memory - each supported CPU adds
	  approximately eight kilobytes to the kernel image.  For best
	  performance should round up your number of processors to the next
	  power of two.

config MIPS_PERF_SHARED_TC_COUNTERS
	bool

config MIPS_NR_CPU_NR_MAP_1024
	bool

config MIPS_NR_CPU_NR_MAP
	int
	depends on SMP
	default 1024 if MIPS_NR_CPU_NR_MAP_1024
	default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024

#
# Timer Interrupt Frequency Configuration
#

choice
	prompt "Timer frequency"
	default HZ_250
	help
	  Allows the configuration of the timer frequency.

	config HZ_24
		bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ

	config HZ_48
		bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ

	config HZ_100
		bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ

	config HZ_128
		bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ

	config HZ_250
		bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ

	config HZ_256
		bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ

	config HZ_1000
		bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ

	config HZ_1024
		bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ

endchoice

config SYS_SUPPORTS_24HZ
	bool

config SYS_SUPPORTS_48HZ
	bool

config SYS_SUPPORTS_100HZ
	bool

config SYS_SUPPORTS_128HZ
	bool

config SYS_SUPPORTS_250HZ
	bool

config SYS_SUPPORTS_256HZ
	bool

config SYS_SUPPORTS_1000HZ
	bool

config SYS_SUPPORTS_1024HZ
	bool

config SYS_SUPPORTS_ARBIT_HZ
	bool
	default y if !SYS_SUPPORTS_24HZ && \
		     !SYS_SUPPORTS_48HZ && \
		     !SYS_SUPPORTS_100HZ && \
		     !SYS_SUPPORTS_128HZ && \
		     !SYS_SUPPORTS_250HZ && \
		     !SYS_SUPPORTS_256HZ && \
		     !SYS_SUPPORTS_1000HZ && \
		     !SYS_SUPPORTS_1024HZ

config HZ
	int
	default 24 if HZ_24
	default 48 if HZ_48
	default 100 if HZ_100
	default 128 if HZ_128
	default 250 if HZ_250
	default 256 if HZ_256
	default 1000 if HZ_1000
	default 1024 if HZ_1024

config SCHED_HRTICK
	def_bool HIGH_RES_TIMERS

config KEXEC
	bool "Kexec system call"
	select KEXEC_CORE
	help
	  kexec is a system call that implements the ability to shutdown your
	  current kernel, and to start another kernel.  It is like a reboot
	  but it is independent of the system firmware.   And like a reboot
	  you can start any kernel with it, not just Linux.

	  The name comes from the similarity to the exec system call.

	  It is an ongoing process to be certain the hardware in a machine
	  is properly shutdown, so do not be surprised if this code does not
	  initially work for you.  As of this writing the exact hardware
	  interface is strongly in flux, so no good recommendation can be
	  made.

config CRASH_DUMP
	bool "Kernel crash dumps"
	help
	  Generate crash dump after being started by kexec.
	  This should be normally only set in special crash dump kernels
	  which are loaded in the main kernel with kexec-tools into
	  a specially reserved region and then later executed after
	  a crash by kdump/kexec. The crash dump kernel must be compiled
	  to a memory address not used by the main kernel or firmware using
	  PHYSICAL_START.

config PHYSICAL_START
	hex "Physical address where the kernel is loaded"
	default "0xffffffff84000000"
	depends on CRASH_DUMP
	help
	  This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
	  If you plan to use kernel for capturing the crash dump change
	  this value to start of the reserved region (the "X" value as
	  specified in the "crashkernel=YM@XM" command line boot parameter
	  passed to the panic-ed kernel).

config MIPS_O32_FP64_SUPPORT
	bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
	depends on 32BIT || MIPS32_O32
	help
	  When this is enabled, the kernel will support use of 64-bit floating
	  point registers with binaries using the O32 ABI along with the
	  EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
	  32-bit MIPS systems this support is at the cost of increasing the
	  size and complexity of the compiled FPU emulator. Thus if you are
	  running a MIPS32 system and know that none of your userland binaries
	  will require 64-bit floating point, you may wish to reduce the size
	  of your kernel & potentially improve FP emulation performance by
	  saying N here.

	  Although binutils currently supports use of this flag the details
	  concerning its effect upon the O32 ABI in userland are still being
	  worked on. In order to avoid userland becoming dependent upon current
	  behaviour before the details have been finalised, this option should
	  be considered experimental and only enabled by those working upon
	  said details.

	  If unsure, say N.

config USE_OF
	bool
	select OF
	select OF_EARLY_FLATTREE
	select IRQ_DOMAIN

config UHI_BOOT
	bool

config BUILTIN_DTB
	bool

choice
	prompt "Kernel appended dtb support" if USE_OF
	default MIPS_NO_APPENDED_DTB

	config MIPS_NO_APPENDED_DTB
		bool "None"
		help
		  Do not enable appended dtb support.

	config MIPS_ELF_APPENDED_DTB
		bool "vmlinux"
		help
		  With this option, the boot code will look for a device tree binary
		  DTB) included in the vmlinux ELF section .appended_dtb. By default
		  it is empty and the DTB can be appended using binutils command
		  objcopy:

		    objcopy --update-section .appended_dtb=<filename>.dtb vmlinux

		  This is meant as a backward compatibility convenience for those
		  systems with a bootloader that can't be upgraded to accommodate
		  the documented boot protocol using a device tree.

	config MIPS_RAW_APPENDED_DTB
		bool "vmlinux.bin or vmlinuz.bin"
		help
		  With this option, the boot code will look for a device tree binary
		  DTB) appended to raw vmlinux.bin or vmlinuz.bin.
		  (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).

		  This is meant as a backward compatibility convenience for those
		  systems with a bootloader that can't be upgraded to accommodate
		  the documented boot protocol using a device tree.

		  Beware that there is very little in terms of protection against
		  this option being confused by leftover garbage in memory that might
		  look like a DTB header after a reboot if no actual DTB is appended
		  to vmlinux.bin.  Do not leave this option active in a production kernel
		  if you don't intend to always append a DTB.
endchoice

choice
	prompt "Kernel command line type" if !CMDLINE_OVERRIDE
	default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
					 !MACH_LOONGSON64 && !MIPS_MALTA && \
					 !CAVIUM_OCTEON_SOC
	default MIPS_CMDLINE_FROM_BOOTLOADER

	config MIPS_CMDLINE_FROM_DTB
		depends on USE_OF
		bool "Dtb kernel arguments if available"

	config MIPS_CMDLINE_DTB_EXTEND
		depends on USE_OF
		bool "Extend dtb kernel arguments with bootloader arguments"

	config MIPS_CMDLINE_FROM_BOOTLOADER
		bool "Bootloader kernel arguments if available"

	config MIPS_CMDLINE_BUILTIN_EXTEND
		depends on CMDLINE_BOOL
		bool "Extend builtin kernel arguments with bootloader arguments"
endchoice

endmenu

config LOCKDEP_SUPPORT
	bool
	default y

config STACKTRACE_SUPPORT
	bool
	default y

config PGTABLE_LEVELS
	int
	default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
	default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
	default 2

config MIPS_AUTO_PFN_OFFSET
	bool

menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"

config PCI_DRIVERS_GENERIC
	select PCI_DOMAINS_GENERIC if PCI
	bool

config PCI_DRIVERS_LEGACY
	def_bool !PCI_DRIVERS_GENERIC
	select NO_GENERIC_PCI_IOPORT_MAP
	select PCI_DOMAINS if PCI

#
# ISA support is now enabled via select.  Too many systems still have the one
# or other ISA chip on the board that users don't know about so don't expect
# users to choose the right thing ...
#
config ISA
	bool

config TC
	bool "TURBOchannel support"
	depends on MACH_DECSTATION
	help
	  TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
	  processors.  TURBOchannel programming specifications are available
	  at:
	  <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
	  and:
	  <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
	  Linux driver support status is documented at:
	  <http://www.linux-mips.org/wiki/DECstation>

config MMU
	bool
	default y

config ARCH_MMAP_RND_BITS_MIN
	default 12 if 64BIT
	default 8

config ARCH_MMAP_RND_BITS_MAX
	default 18 if 64BIT
	default 15

config ARCH_MMAP_RND_COMPAT_BITS_MIN
	default 8

config ARCH_MMAP_RND_COMPAT_BITS_MAX
	default 15

config I8253
	bool
	select CLKSRC_I8253
	select CLKEVT_I8253
	select MIPS_EXTERNAL_TIMER
endmenu

config TRAD_SIGNALS
	bool

config MIPS32_COMPAT
	bool

config COMPAT
	bool

config MIPS32_O32
	bool "Kernel support for o32 binaries"
	depends on 64BIT
	select ARCH_WANT_OLD_COMPAT_IPC
	select COMPAT
	select MIPS32_COMPAT
	help
	  Select this option if you want to run o32 binaries.  These are pure
	  32-bit binaries as used by the 32-bit Linux/MIPS port.  Most of
	  existing binaries are in this format.

	  If unsure, say Y.

config MIPS32_N32
	bool "Kernel support for n32 binaries"
	depends on 64BIT
	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
	select COMPAT
	select MIPS32_COMPAT
	help
	  Select this option if you want to run n32 binaries.  These are
	  64-bit binaries using 32-bit quantities for addressing and certain
	  data that would normally be 64-bit.  They are used in special
	  cases.

	  If unsure, say N.

config CC_HAS_MNO_BRANCH_LIKELY
	def_bool y
	depends on $(cc-option,-mno-branch-likely)

# https://github.com/llvm/llvm-project/issues/61045
config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
	def_bool y if CC_IS_CLANG

menu "Power management options"

config ARCH_HIBERNATION_POSSIBLE
	def_bool y
	depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP

config ARCH_SUSPEND_POSSIBLE
	def_bool y
	depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP

source "kernel/power/Kconfig"

endmenu

config MIPS_EXTERNAL_TIMER
	bool

menu "CPU Power Management"

if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
source "drivers/cpufreq/Kconfig"
endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER

source "drivers/cpuidle/Kconfig"

endmenu

source "arch/mips/kvm/Kconfig"

source "arch/mips/vdso/Kconfig"