summaryrefslogtreecommitdiff
path: root/arch/mips/boot/dts/mti/sead3.dts
blob: 2579ca51c0b612b4545e412a25693e395306ed19 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
/dts-v1/;

/memreserve/ 0x00000000 0x00001000;	// reserved
/memreserve/ 0x00001000 0x000ef000;	// ROM data
/memreserve/ 0x000f0000 0x004cc000;	// reserved

#include <dt-bindings/interrupt-controller/mips-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "mti,sead-3";
	interrupt-parent = <&gic>;

	chosen {
		stdout-path = "uart1:115200";
	};

	aliases {
		uart0 = &uart0;
		uart1 = &uart1;
	};

	cpus {
		cpu@0 {
			compatible = "mti,mips14KEc", "mti,mips14Kc";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};

	cpu_intc: interrupt-controller {
		compatible = "mti,cpu-interrupt-controller";

		interrupt-controller;
		#interrupt-cells = <1>;
	};

	gic: interrupt-controller@1b1c0000 {
		compatible = "mti,gic";
		reg = <0x1b1c0000 0x20000>;

		interrupt-controller;
		#interrupt-cells = <3>;

		/*
		 * Declare the interrupt-parent even though the mti,gic
		 * binding doesn't require it, such that the kernel can
		 * figure out that cpu_intc is the root interrupt
		 * controller & should be probed first.
		 */
		interrupt-parent = <&cpu_intc>;

		timer {
			compatible = "mti,gic-timer";
			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
		};
	};

	ehci@1b200000 {
		compatible = "generic-ehci";
		reg = <0x1b200000 0x1000>;

		interrupts = <0>; /* GIC 0 or CPU 6 */

		has-transaction-translator;
	};

	flash@1c000000 {
		compatible = "intel,28f128j3", "cfi-flash";
		reg = <0x1c000000 0x2000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		bank-width = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			user-fs@0 {
				label = "User FS";
				reg = <0x0 0x1fc0000>;
			};

			board-config@3e0000 {
				label = "Board Config";
				reg = <0x1fc0000 0x40000>;
			};
		};
	};

	fpga_regs: system-controller@1f000000 {
		compatible = "mti,sead3-fpga", "syscon", "simple-mfd";
		reg = <0x1f000000 0x200>;

		reboot {
			compatible = "syscon-reboot";
			regmap = <&fpga_regs>;
			offset = <0x50>;
			mask = <0x4d>;
		};

		poweroff {
			compatible = "restart-poweroff";
		};
	};

	system-controller@1f000200 {
		compatible = "mti,sead3-cpld", "syscon", "simple-mfd";
		reg = <0x1f000200 0x300>;

		led@10.0 {
			compatible = "register-bit-led";
			offset = <0x10>;
			mask = <0x1>;
			label = "pled0";
		};
		led@10.1 {
			compatible = "register-bit-led";
			offset = <0x10>;
			mask = <0x2>;
			label = "pled1";
		};
		led@10.2 {
			compatible = "register-bit-led";
			offset = <0x10>;
			mask = <0x4>;
			label = "pled2";
		};
		led@10.3 {
			compatible = "register-bit-led";
			offset = <0x10>;
			mask = <0x8>;
			label = "pled3";
		};
		led@10.4 {
			compatible = "register-bit-led";
			offset = <0x10>;
			mask = <0x10>;
			label = "pled4";
		};
		led@10.5 {
			compatible = "register-bit-led";
			offset = <0x10>;
			mask = <0x20>;
			label = "pled5";
		};
		led@10.6 {
			compatible = "register-bit-led";
			offset = <0x10>;
			mask = <0x40>;
			label = "pled6";
		};
		led@10.7 {
			compatible = "register-bit-led";
			offset = <0x10>;
			mask = <0x80>;
			label = "pled7";
		};

		led@18.0 {
			compatible = "register-bit-led";
			offset = <0x18>;
			mask = <0x1>;
			label = "fled0";
		};
		led@18.1 {
			compatible = "register-bit-led";
			offset = <0x18>;
			mask = <0x2>;
			label = "fled1";
		};
		led@18.2 {
			compatible = "register-bit-led";
			offset = <0x18>;
			mask = <0x4>;
			label = "fled2";
		};
		led@18.3 {
			compatible = "register-bit-led";
			offset = <0x18>;
			mask = <0x8>;
			label = "fled3";
		};
		led@18.4 {
			compatible = "register-bit-led";
			offset = <0x18>;
			mask = <0x10>;
			label = "fled4";
		};
		led@18.5 {
			compatible = "register-bit-led";
			offset = <0x18>;
			mask = <0x20>;
			label = "fled5";
		};
		led@18.6 {
			compatible = "register-bit-led";
			offset = <0x18>;
			mask = <0x40>;
			label = "fled6";
		};
		led@18.7 {
			compatible = "register-bit-led";
			offset = <0x18>;
			mask = <0x80>;
			label = "fled7";
		};

		lcd@200 {
			compatible = "mti,sead3-lcd";
			offset = <0x200>;
		};
	};

	/* UART connected to FTDI & miniUSB socket */
	uart0: uart@1f000900 {
		compatible = "ns16550a";
		reg = <0x1f000900 0x20>;
		reg-io-width = <4>;
		reg-shift = <2>;

		clock-frequency = <14745600>;

		interrupts = <3>; /* GIC 3 or CPU 4 */

		no-loopback-test;
	};

	/* UART connected to RS232 socket */
	uart1: uart@1f000800 {
		compatible = "ns16550a";
		reg = <0x1f000800 0x20>;
		reg-io-width = <4>;
		reg-shift = <2>;

		clock-frequency = <14745600>;

		interrupts = <2>; /* GIC 2 or CPU 4 */

		no-loopback-test;
	};

	eth@1f010000 {
		compatible = "smsc,lan9115";
		reg = <0x1f010000 0x10000>;
		reg-io-width = <4>;

		interrupts = <0>; /* GIC 0 or CPU 6 */

		phy-mode = "mii";
		smsc,irq-push-pull;
		smsc,save-mac-address;
	};
};