summaryrefslogtreecommitdiff
path: root/drivers/clk/ingenic/jz4725b-cgu.c
blob: 15d61793f53b13729a2a37a67e1e1c3519b37f78 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
// SPDX-License-Identifier: GPL-2.0
/*
 * Ingenic JZ4725B SoC CGU driver
 *
 * Copyright (C) 2018 Paul Cercueil
 * Author: Paul Cercueil <paul@crapouillou.net>
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/of.h>

#include <dt-bindings/clock/ingenic,jz4725b-cgu.h>

#include "cgu.h"
#include "pm.h"

/* CGU register offsets */
#define CGU_REG_CPCCR		0x00
#define CGU_REG_LCR		0x04
#define CGU_REG_CPPCR		0x10
#define CGU_REG_CLKGR		0x20
#define CGU_REG_OPCR		0x24
#define CGU_REG_I2SCDR		0x60
#define CGU_REG_LPCDR		0x64
#define CGU_REG_MSCCDR		0x68
#define CGU_REG_SSICDR		0x74
#define CGU_REG_CIMCDR		0x78

/* bits within the LCR register */
#define LCR_SLEEP		BIT(0)

static struct ingenic_cgu *cgu;

static const s8 pll_od_encoding[4] = {
	0x0, 0x1, -1, 0x3,
};

static const u8 jz4725b_cgu_cpccr_div_table[] = {
	1, 2, 3, 4, 6, 8,
};

static const u8 jz4725b_cgu_pll_half_div_table[] = {
	2, 1,
};

static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {

	/* External clocks */

	[JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT },
	[JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },

	[JZ4725B_CLK_PLL] = {
		"pll", CGU_CLK_PLL,
		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
		.pll = {
			.reg = CGU_REG_CPPCR,
			.rate_multiplier = 1,
			.m_shift = 23,
			.m_bits = 9,
			.m_offset = 2,
			.n_shift = 18,
			.n_bits = 5,
			.n_offset = 2,
			.od_shift = 16,
			.od_bits = 2,
			.od_max = 4,
			.od_encoding = pll_od_encoding,
			.stable_bit = 10,
			.bypass_reg = CGU_REG_CPPCR,
			.bypass_bit = 9,
			.enable_bit = 8,
		},
	},

	/* Muxes & dividers */

	[JZ4725B_CLK_PLL_HALF] = {
		"pll half", CGU_CLK_DIV,
		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
		.div = {
			CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
			jz4725b_cgu_pll_half_div_table,
		},
	},

	[JZ4725B_CLK_CCLK] = {
		"cclk", CGU_CLK_DIV,
		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
		.div = {
			CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
			jz4725b_cgu_cpccr_div_table,
		},
	},

	[JZ4725B_CLK_HCLK] = {
		"hclk", CGU_CLK_DIV,
		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
		.div = {
			CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
			jz4725b_cgu_cpccr_div_table,
		},
	},

	[JZ4725B_CLK_PCLK] = {
		"pclk", CGU_CLK_DIV,
		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
		.div = {
			CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
			jz4725b_cgu_cpccr_div_table,
		},
	},

	[JZ4725B_CLK_MCLK] = {
		"mclk", CGU_CLK_DIV,
		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
		.div = {
			CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
			jz4725b_cgu_cpccr_div_table,
		},
	},

	[JZ4725B_CLK_IPU] = {
		"ipu", CGU_CLK_DIV | CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
		.div = {
			CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
			jz4725b_cgu_cpccr_div_table,
		},
		.gate = { CGU_REG_CLKGR, 13 },
	},

	[JZ4725B_CLK_LCD] = {
		"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
		.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 9 },
	},

	[JZ4725B_CLK_I2S] = {
		"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
		.mux = { CGU_REG_CPCCR, 31, 1 },
		.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
	},

	[JZ4725B_CLK_SPI] = {
		"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
		.mux = { CGU_REG_SSICDR, 31, 1 },
		.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 4 },
	},

	[JZ4725B_CLK_MMC_MUX] = {
		"mmc_mux", CGU_CLK_DIV,
		.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
		.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
	},

	[JZ4725B_CLK_UDC] = {
		"udc", CGU_CLK_MUX | CGU_CLK_DIV,
		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
		.mux = { CGU_REG_CPCCR, 29, 1 },
		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
	},

	/* Gate-only clocks */

	[JZ4725B_CLK_UART] = {
		"uart", CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 0 },
	},

	[JZ4725B_CLK_DMA] = {
		"dma", CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 12 },
	},

	[JZ4725B_CLK_ADC] = {
		"adc", CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 7 },
	},

	[JZ4725B_CLK_I2C] = {
		"i2c", CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 3 },
	},

	[JZ4725B_CLK_AIC] = {
		"aic", CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 5 },
	},

	[JZ4725B_CLK_MMC0] = {
		"mmc0", CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 6 },
	},

	[JZ4725B_CLK_MMC1] = {
		"mmc1", CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 16 },
	},

	[JZ4725B_CLK_BCH] = {
		"bch", CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 11 },
	},

	[JZ4725B_CLK_TCU] = {
		"tcu", CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
		.gate = { CGU_REG_CLKGR, 1 },
	},

	[JZ4725B_CLK_EXT512] = {
		"ext/512", CGU_CLK_FIXDIV,
		.parents = { JZ4725B_CLK_EXT },

		/* Doc calls it EXT512, but it seems to be /256... */
		.fixdiv = { 256 },
	},

	[JZ4725B_CLK_RTC] = {
		"rtc", CGU_CLK_MUX,
		.parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
		.mux = { CGU_REG_OPCR, 2, 1},
	},

	[JZ4725B_CLK_UDC_PHY] = {
		"udc_phy", CGU_CLK_GATE,
		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
		.gate = { CGU_REG_OPCR, 6, true },
	},
};

static void __init jz4725b_cgu_init(struct device_node *np)
{
	int retval;

	cgu = ingenic_cgu_new(jz4725b_cgu_clocks,
			      ARRAY_SIZE(jz4725b_cgu_clocks), np);
	if (!cgu) {
		pr_err("%s: failed to initialise CGU\n", __func__);
		return;
	}

	retval = ingenic_cgu_register_clocks(cgu);
	if (retval)
		pr_err("%s: failed to register CGU Clocks\n", __func__);

	ingenic_cgu_register_syscore_ops(cgu);
}
CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);