summaryrefslogtreecommitdiff
path: root/drivers/clk/uniphier/clk-uniphier.h
blob: 01c16ecec48f79608f446ff41bf6caf5a6432c69 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
/*
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __CLK_UNIPHIER_H__
#define __CLK_UNIPHIER_H__

struct clk_hw;
struct device;
struct regmap;

#define UNIPHIER_CLK_CPUGEAR_MAX_PARENTS	16
#define UNIPHIER_CLK_MUX_MAX_PARENTS		8

enum uniphier_clk_type {
	UNIPHIER_CLK_TYPE_CPUGEAR,
	UNIPHIER_CLK_TYPE_FIXED_FACTOR,
	UNIPHIER_CLK_TYPE_FIXED_RATE,
	UNIPHIER_CLK_TYPE_GATE,
	UNIPHIER_CLK_TYPE_MUX,
};

struct uniphier_clk_cpugear_data {
	const char *parent_names[UNIPHIER_CLK_CPUGEAR_MAX_PARENTS];
	unsigned int num_parents;
	unsigned int regbase;
	unsigned int mask;
};

struct uniphier_clk_fixed_factor_data {
	const char *parent_name;
	unsigned int mult;
	unsigned int div;
};

struct uniphier_clk_fixed_rate_data {
	unsigned long fixed_rate;
};

struct uniphier_clk_gate_data {
	const char *parent_name;
	unsigned int reg;
	unsigned int bit;
};

struct uniphier_clk_mux_data {
	const char *parent_names[UNIPHIER_CLK_MUX_MAX_PARENTS];
	unsigned int num_parents;
	unsigned int reg;
	unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
	unsigned int vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
};

struct uniphier_clk_data {
	const char *name;
	enum uniphier_clk_type type;
	int idx;
	union {
		struct uniphier_clk_cpugear_data cpugear;
		struct uniphier_clk_fixed_factor_data factor;
		struct uniphier_clk_fixed_rate_data rate;
		struct uniphier_clk_gate_data gate;
		struct uniphier_clk_mux_data mux;
	} data;
};

#define UNIPHIER_CLK_CPUGEAR(_name, _idx, _regbase, _mask,	\
			     _num_parents, ...)			\
	{							\
		.name = (_name),				\
		.type = UNIPHIER_CLK_TYPE_CPUGEAR,		\
		.idx = (_idx),					\
		.data.cpugear = {				\
			.parent_names = { __VA_ARGS__ },	\
			.num_parents = (_num_parents),		\
			.regbase = (_regbase),			\
			.mask = (_mask)				\
		 },						\
	}

#define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div)	\
	{							\
		.name = (_name),				\
		.type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,		\
		.idx = (_idx),					\
		.data.factor = {				\
			.parent_name = (_parent),		\
			.mult = (_mult),			\
			.div = (_div),				\
		},						\
	}

#define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit)	\
	{							\
		.name = (_name),				\
		.type = UNIPHIER_CLK_TYPE_GATE,			\
		.idx = (_idx),					\
		.data.gate = {					\
			.parent_name = (_parent),		\
			.reg = (_reg),				\
			.bit = (_bit),				\
		},						\
	}

#define UNIPHIER_CLK_DIV(parent, div)				\
	UNIPHIER_CLK_FACTOR(parent "/" #div, -1, parent, 1, div)

#define UNIPHIER_CLK_DIV2(parent, div0, div1)			\
	UNIPHIER_CLK_DIV(parent, div0),				\
	UNIPHIER_CLK_DIV(parent, div1)

#define UNIPHIER_CLK_DIV3(parent, div0, div1, div2)		\
	UNIPHIER_CLK_DIV2(parent, div0, div1),			\
	UNIPHIER_CLK_DIV(parent, div2)

#define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3)	\
	UNIPHIER_CLK_DIV2(parent, div0, div1),			\
	UNIPHIER_CLK_DIV2(parent, div2, div3)

struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
					     struct regmap *regmap,
					     const char *name,
				const struct uniphier_clk_cpugear_data *data);
struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
						  const char *name,
			const struct uniphier_clk_fixed_factor_data *data);
struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
						const char *name,
			const struct uniphier_clk_fixed_rate_data *data);
struct clk_hw *uniphier_clk_register_gate(struct device *dev,
					  struct regmap *regmap,
					  const char *name,
				const struct uniphier_clk_gate_data *data);
struct clk_hw *uniphier_clk_register_mux(struct device *dev,
					 struct regmap *regmap,
					 const char *name,
				const struct uniphier_clk_mux_data *data);

extern const struct uniphier_clk_data uniphier_sld3_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];

#endif /* __CLK_UNIPHIER_H__ */