summaryrefslogtreecommitdiff
path: root/drivers/crypto/cavium/cpt/cptpf.h
blob: 8a2a8e538da4d0e77d19bb8c1b03c6579a5fcdd1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
/*
 * Copyright (C) 2016 Cavium, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 */

#ifndef __CPTPF_H
#define __CPTPF_H

#include "cpt_common.h"

#define CSR_DELAY 30
#define CPT_MAX_CORE_GROUPS 8
#define CPT_MAX_SE_CORES 10
#define CPT_MAX_AE_CORES 6
#define CPT_MAX_TOTAL_CORES (CPT_MAX_SE_CORES + CPT_MAX_AE_CORES)
#define CPT_MAX_VF_NUM 16
#define	CPT_PF_MSIX_VECTORS 3
#define CPT_PF_INT_VEC_E_MBOXX(a) (0x02 + (a))
#define CPT_UCODE_VERSION_SZ 32
struct cpt_device;

struct microcode {
	u8 is_mc_valid;
	u8 is_ae;
	u8 group;
	u8 num_cores;
	u32 code_size;
	u64 core_mask;
	u8 version[CPT_UCODE_VERSION_SZ];
	/* Base info */
	dma_addr_t phys_base;
	void *code;
};

struct cpt_vf_info {
	u8 state;
	u8 priority;
	u8 id;
	u32 qlen;
};

/**
 * cpt device structure
 */
struct cpt_device {
	u16 flags;	/* Flags to hold device status bits */
	u8 num_vf_en; /* Number of VFs enabled (0...CPT_MAX_VF_NUM) */
	struct cpt_vf_info vfinfo[CPT_MAX_VF_NUM]; /* Per VF info */

	void __iomem *reg_base; /* Register start address */
	/* MSI-X */
	u8 num_vec;
	bool msix_enabled;
	struct msix_entry msix_entries[CPT_PF_MSIX_VECTORS];
	bool irq_allocated[CPT_PF_MSIX_VECTORS];
	struct pci_dev *pdev; /* pci device handle */

	struct microcode mcode[CPT_MAX_CORE_GROUPS];
	u8 next_mc_idx; /* next microcode index */
	u8 next_group;
	u8 max_se_cores;
	u8 max_ae_cores;
};

void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx);
#endif /* __CPTPF_H */